scons: Enable -Wextra by default
Make best use of the compiler, and enable -Wextra as well as -Wall. There are a few issues that had to be resolved, but they are all trivial.
This commit is contained in:
parent
7661f1c2bf
commit
12eb034378
33 changed files with 80 additions and 87 deletions
17
SConstruct
17
SConstruct
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@ -554,14 +554,12 @@ if main['GCC'] or main['CLANG']:
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# As gcc and clang share many flags, do the common parts here
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main.Append(CCFLAGS=['-pipe'])
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main.Append(CCFLAGS=['-fno-strict-aliasing'])
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# Enable -Wall and then disable the few warnings that we
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# consistently violate
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main.Append(CCFLAGS=['-Wall', '-Wno-sign-compare', '-Wundef'])
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# Enable -Wall and -Wextra and then disable the few warnings that
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# we consistently violate
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main.Append(CCFLAGS=['-Wall', '-Wundef', '-Wextra',
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'-Wno-sign-compare', '-Wno-unused-parameter'])
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# We always compile using C++11
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main.Append(CXXFLAGS=['-std=c++11'])
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# Add selected sanity checks from -Wextra
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main.Append(CXXFLAGS=['-Wmissing-field-initializers',
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'-Woverloaded-virtual'])
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else:
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print termcap.Yellow + termcap.Bold + 'Error' + termcap.Normal,
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print "Don't know what compiler options to use for your compiler."
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@ -656,14 +654,11 @@ elif main['CLANG']:
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print 'Error: Unable to determine clang version.'
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Exit(1)
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# clang has a few additional warnings that we disable,
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# tautological comparisons are allowed due to unsigned integers
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# being compared to constants that happen to be 0, and extraneous
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# clang has a few additional warnings that we disable, extraneous
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# parantheses are allowed due to Ruby's printing of the AST,
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# finally self assignments are allowed as the generated CPU code
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# is relying on this
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main.Append(CCFLAGS=['-Wno-tautological-compare',
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'-Wno-parentheses',
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main.Append(CCFLAGS=['-Wno-parentheses',
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'-Wno-self-assign',
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# Some versions of libstdc++ (4.8?) seem to
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# use struct hash and class hash
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@ -77,7 +77,8 @@ dramenv.Append(CCFLAGS=['-Wno-unused-value'])
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# If we are using clang, there are more flags to disable
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if main['CLANG']:
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dramenv.Append(CCFLAGS=['-Wno-unused-private-field'])
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dramenv.Append(CCFLAGS=['-Wno-unused-private-field',
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'-Wno-tautological-undefined-compare'])
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# Tell DRAMSim2 to not store any data as this is already covered by
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# the wrapper
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@ -93,10 +93,10 @@ ElfFile('libelf_msize.c')
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m4env = main.Clone()
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if m4env['GCC']:
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m4env.Append(CCFLAGS=['-Wno-pointer-sign'])
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if compareVersions(m4env['GCC_VERSION'], '4.6') >= 0:
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m4env.Append(CCFLAGS=['-Wno-unused-but-set-variable',
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'-Wno-implicit-function-declaration'])
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m4env.Append(CCFLAGS=['-Wno-pointer-sign',
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'-Wno-unused-but-set-variable',
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'-Wno-implicit-function-declaration',
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'-Wno-override-init'])
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if m4env['CLANG']:
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m4env.Append(CCFLAGS=['-Wno-initializer-overrides', '-Wno-pointer-sign'])
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# clang defaults to c99 (while gcc defaults to gnu89) and there is a
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@ -42,6 +42,7 @@ Import('main')
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main.Prepend(CPPPATH=Dir('./include'))
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nomali = main.Clone()
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nomali.Append(CCFLAGS=['-Wno-ignored-qualifiers'])
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nomali_sources = [
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"lib/gpu.cc",
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@ -1018,11 +1018,6 @@ def makeEnv(env, label, objsfx, strip = False, **kwargs):
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# the SWIG generated code
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swig_env.Append(CCFLAGS=['-Wno-unused-label', '-Wno-unused-value'])
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# Add additional warnings here that should not be applied to
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# the SWIG generated code
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new_env.Append(CXXFLAGS=['-Wmissing-declarations',
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'-Wdelete-non-virtual-dtor'])
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if env['GCC']:
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# Depending on the SWIG version, we also need to supress
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# warnings about uninitialized variables and missing field
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@ -1030,7 +1025,8 @@ def makeEnv(env, label, objsfx, strip = False, **kwargs):
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swig_env.Append(CCFLAGS=['-Wno-uninitialized',
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'-Wno-missing-field-initializers',
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'-Wno-unused-but-set-variable',
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'-Wno-maybe-uninitialized'])
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'-Wno-maybe-uninitialized',
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'-Wno-type-limits'])
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# Only gcc >= 4.9 supports UBSan, so check both the version
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# and the command-line option before adding the compiler and
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@ -1041,13 +1037,9 @@ def makeEnv(env, label, objsfx, strip = False, **kwargs):
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new_env.Append(LINKFLAGS='-fsanitize=undefined')
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if env['CLANG']:
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swig_env.Append(CCFLAGS=[
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# Some versions of SWIG can return uninitialized values
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'-Wno-sometimes-uninitialized',
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# Register storage is requested in a lot of places in
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# SWIG-generated code.
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'-Wno-deprecated-register',
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])
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swig_env.Append(CCFLAGS=['-Wno-sometimes-uninitialized',
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'-Wno-deprecated-register',
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'-Wno-tautological-compare'])
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# All supported clang versions have support for UBSan, so if
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# asked to use it, append the compiler and linker flags.
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@ -40,7 +40,7 @@
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namespace AlphaISA {
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typedef const Addr FaultVect;
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typedef Addr FaultVect;
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class AlphaFault : public FaultBase
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{
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@ -78,7 +78,7 @@ inline void startupCPU(ThreadContext *tc, int cpuId)
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inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
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// User Virtual
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inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
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inline bool IsUSeg(Addr a) { assert(USegBase == 0); return a <= USegEnd; }
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// Kernel Direct Mapped
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inline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; }
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@ -58,7 +58,7 @@
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namespace ArmISA
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{
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typedef const Addr FaultOffset;
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typedef Addr FaultOffset;
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class ArmFault : public FaultBase
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{
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@ -209,7 +209,7 @@ getMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
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// We deliberately extend both the Cluster ID and CPU ID fields to allow
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// for simulation of larger systems
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assert((0 <= tc->cpuId()) && (tc->cpuId() < 256));
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assert((0 <= tc->socketId()) && (tc->socketId() < 65536));
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assert(tc->socketId() < 65536);
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if (arm_sys->multiThread) {
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return 0x80000000 | // multiprocessor extensions available
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tc->contextId();
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@ -45,7 +45,7 @@
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namespace MipsISA
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{
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typedef const Addr FaultVect;
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typedef Addr FaultVect;
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enum ExcCode {
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// A dummy value to use when the code isn't defined or doesn't matter.
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@ -2404,7 +2404,7 @@ decode OPCODE_HI default Unknown::unknown() {
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0x3: decode OP_LO {
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format DspHiLoOp {
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0x2: shilo({{
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if (sext<6>(HILOSA) < 0) {
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if ((int64_t)sext<6>(HILOSA) < 0) {
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dspac = (uint64_t)dspac <<
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-sext<6>(HILOSA);
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} else {
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@ -2413,7 +2413,7 @@ decode OPCODE_HI default Unknown::unknown() {
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}
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}});
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0x3: shilov({{
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if (sext<6>(Rs_sw<5:0>) < 0) {
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if ((int64_t)sext<6>(Rs_sw<5:0>) < 0) {
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dspac = (uint64_t)dspac <<
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-sext<6>(Rs_sw<5:0>);
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} else {
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@ -669,13 +669,13 @@ decode OP default Unknown::unknown()
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}});
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0x43: FpUnimpl::fmovq_fcc1();
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0x45: fmovrslez({{
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if (Rs1 <= 0)
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if ((int64_t)Rs1 <= 0)
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Frds = Frs2s;
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else
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Frds = Frds;
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}});
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0x46: fmovrdlez({{
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if (Rs1 <= 0)
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if ((int64_t)Rs1 <= 0)
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Frd = Frs2;
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else
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Frd = Frd;
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@ -740,13 +740,13 @@ decode OP default Unknown::unknown()
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}});
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0x57: FpUnimpl::fcmpeq();
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0x65: fmovrslz({{
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if (Rs1 < 0)
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if ((int64_t)Rs1 < 0)
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Frds = Frs2s;
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else
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Frds = Frds;
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}});
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0x66: fmovrdlz({{
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if (Rs1 < 0)
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if ((int64_t)Rs1 < 0)
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Frd = Frs2;
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else
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Frd = Frd;
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@ -792,26 +792,26 @@ decode OP default Unknown::unknown()
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}});
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0xC3: FpUnimpl::fmovq_fcc3();
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0xC5: fmovrsgz({{
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if (Rs1 > 0)
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if ((int64_t)Rs1 > 0)
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Frds = Frs2s;
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else
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Frds = Frds;
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}});
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0xC6: fmovrdgz({{
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if (Rs1 > 0)
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if ((int64_t)Rs1 > 0)
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Frd = Frs2;
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else
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Frd = Frd;
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}});
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0xC7: FpUnimpl::fmovrqgz();
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0xE5: fmovrsgez({{
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if (Rs1 >= 0)
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if ((int64_t)Rs1 >= 0)
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Frds = Frs2s;
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else
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Frds = Frds;
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}});
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0xE6: fmovrdgez({{
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if (Rs1 >= 0)
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if ((int64_t)Rs1 >= 0)
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Frd = Frs2;
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else
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Frd = Frd;
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@ -89,7 +89,7 @@ namespace BitfieldBackend
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"Bitfield ranges must be specified as <msb, lsb>");
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public:
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operator const uint64_t () const
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operator uint64_t () const
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{
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return this->getBits(first, last);
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}
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@ -129,7 +129,7 @@ namespace BitfieldBackend
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class BitfieldWO : public Bitfield<first, last>
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{
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private:
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operator const uint64_t () const;
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operator uint64_t () const;
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public:
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using Bitfield<first, last>::operator=;
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@ -148,7 +148,7 @@ namespace BitfieldBackend
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class SignedBitfield : public BitfieldBase<Type>
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{
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public:
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operator const int64_t () const
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operator int64_t () const
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{
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return sext<first - last + 1>(this->getBits(first, last));
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}
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@ -188,7 +188,7 @@ namespace BitfieldBackend
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class SignedBitfieldWO : public SignedBitfield<first, last>
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{
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private:
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operator const int64_t () const;
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operator int64_t () const;
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public:
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using SignedBitfield<first, last>::operator=;
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@ -304,10 +304,10 @@ namespace BitfieldBackend
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//do so.
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#define EndSubBitUnion(name) \
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}; \
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inline operator const __DataType () const \
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inline operator __DataType () const \
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{ return __data; } \
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\
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inline const __DataType operator = (const __DataType & _data) \
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inline __DataType operator = (const __DataType & _data) \
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{ return __data = _data;} \
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} name;
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@ -793,13 +793,13 @@ class BaseDynInst : public ExecContext, public RefCounted
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void pcState(const TheISA::PCState &val) { pc = val; }
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/** Read the PC of this instruction. */
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const Addr instAddr() const { return pc.instAddr(); }
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Addr instAddr() const { return pc.instAddr(); }
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/** Read the PC of the next instruction. */
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const Addr nextInstAddr() const { return pc.nextInstAddr(); }
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Addr nextInstAddr() const { return pc.nextInstAddr(); }
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/**Read the micro PC of this instruction. */
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const Addr microPC() const { return pc.microPC(); }
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Addr microPC() const { return pc.microPC(); }
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bool readPredicate()
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{
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@ -105,7 +105,7 @@ class SatCounter
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/**
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* Read the counter's value.
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*/
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const uint8_t read() const
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uint8_t read() const
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{ return counter; }
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private:
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@ -1337,8 +1337,8 @@ TraceCPU::ElasticDataGen::GraphNode::removeRegDep(NodeSeqNum reg_dep)
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if (own_reg_dep == reg_dep) {
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// If register dependency is found, make it zero and return true
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own_reg_dep = 0;
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assert(numRegDep > 0);
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--numRegDep;
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assert(numRegDep >= 0);
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DPRINTFR(TraceCPUData, "\tFor %lli: Marking register dependency %lli "
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"done.\n", seqNum, reg_dep);
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return true;
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@ -1356,8 +1356,8 @@ TraceCPU::ElasticDataGen::GraphNode::removeRobDep(NodeSeqNum rob_dep)
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if (own_rob_dep == rob_dep) {
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// If the rob dependency is found, make it zero and return true
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own_rob_dep = 0;
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assert(numRobDep > 0);
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--numRobDep;
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assert(numRobDep >= 0);
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DPRINTFR(TraceCPUData, "\tFor %lli: Marking ROB dependency %lli "
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"done.\n", seqNum, rob_dep);
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return true;
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@ -316,7 +316,7 @@ class HDLcd: public AmbaDmaDevice
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}
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/** Masked interrupt status register */
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const uint32_t intStatus() const { return int_rawstat & int_mask; }
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uint32_t intStatus() const { return int_rawstat & int_mask; }
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protected: // Pixel output
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class PixelPump : public BasePixelPump
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@ -110,7 +110,7 @@ class Pl011 : public Uart, public AmbaDevice
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void clearInterrupts(uint16_t ints) { setInterrupts(rawInt & ~ints, imsc); }
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/** Masked interrupt status register */
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const inline uint16_t maskInt() const { return rawInt & imsc; }
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inline uint16_t maskInt() const { return rawInt & imsc; }
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/** Wrapper to create an event out of the thing */
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EventWrapper<Pl011, &Pl011::generateInterrupt> intEvent;
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@ -241,8 +241,8 @@ EtherTap::process(int revent)
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packet->length = data_len;
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memcpy(packet->data, data, data_len);
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assert(buffer_offset >= data_len + sizeof(uint32_t));
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buffer_offset -= data_len + sizeof(uint32_t);
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assert(buffer_offset >= 0);
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if (buffer_offset > 0) {
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memmove(buffer, data + data_len, buffer_offset);
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data_len = ntohl(*(uint32_t *)buffer);
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@ -93,6 +93,7 @@ enum ChipCommandRegister {
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/* configuration register */
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enum ConfigurationRegisters {
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CFGR_ZERO = 0x00000000,
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CFGR_LNKSTS = 0x80000000,
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CFGR_SPDSTS = 0x60000000,
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CFGR_SPDSTS1 = 0x40000000,
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@ -395,7 +396,7 @@ static inline int
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SPDSTS_POLARITY(int lnksts)
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{
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return (CFGR_SPDSTS1 | CFGR_SPDSTS0 | CFGR_DUPSTS |
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(lnksts ? CFGR_LNKSTS : 0));
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(lnksts ? CFGR_LNKSTS : CFGR_ZERO));
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}
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#endif /* __DEV_NS_GIGE_REG_H__ */
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@ -106,8 +106,8 @@ class PacketFifo
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unsigned
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reserve(unsigned len = 0)
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{
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assert(avail() >= len);
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_reserved += len;
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assert(avail() >= 0);
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return _reserved;
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}
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@ -91,7 +91,8 @@ Iob::readIob(PacketPtr pkt)
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{
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Addr accessAddr = pkt->getAddr() - iobManAddr;
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if (accessAddr >= IntManAddr && accessAddr < IntManAddr + IntManSize) {
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assert(IntManAddr == 0);
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if (accessAddr < IntManAddr + IntManSize) {
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int index = (accessAddr - IntManAddr) >> 3;
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uint64_t data = intMan[index].cpu << 8 | intMan[index].vector << 0;
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pkt->set(data);
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@ -186,7 +187,8 @@ Iob::writeIob(PacketPtr pkt)
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int index;
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uint64_t data;
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if (accessAddr >= IntManAddr && accessAddr < IntManAddr + IntManSize) {
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assert(IntManAddr == 0);
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if (accessAddr < IntManAddr + IntManSize) {
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index = (accessAddr - IntManAddr) >> 3;
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data = pkt->get<uint64_t>();
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intMan[index].cpu = bits(data,12,8);
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@ -249,7 +249,7 @@ Terminal::read(uint8_t *buf, size_t len)
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if (data_fd < 0)
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panic("Terminal not properly attached.\n");
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size_t ret;
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ssize_t ret;
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do {
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ret = ::read(data_fd, buf, len);
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} while (ret == -1 && errno == EINTR);
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@ -215,7 +215,7 @@ class MemCmd
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bool isPrint() const { return testCmdAttrib(IsPrint); }
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bool isFlush() const { return testCmdAttrib(IsFlush); }
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const Command
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||||
Command
|
||||
responseCommand() const
|
||||
{
|
||||
return commandInfo[cmd].response;
|
||||
|
|
|
@ -93,6 +93,7 @@ class PageTableBase : public Serializable
|
|||
* bit 3 - read-write | read-only
|
||||
*/
|
||||
enum MappingFlags : uint32_t {
|
||||
Zero = 0,
|
||||
Clobber = 1,
|
||||
NotPresent = 2,
|
||||
Uncacheable = 4,
|
||||
|
|
|
@ -234,7 +234,6 @@ class Request
|
|||
void
|
||||
setPhys(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time)
|
||||
{
|
||||
assert(size >= 0);
|
||||
_paddr = paddr;
|
||||
_size = size;
|
||||
_time = time;
|
||||
|
|
|
@ -65,8 +65,8 @@ class AbstractController : public MemObject, public Consumer
|
|||
void init();
|
||||
const Params *params() const { return (const Params *)_params; }
|
||||
|
||||
const NodeID getVersion() const { return m_machineID.getNum(); }
|
||||
const MachineType getType() const { return m_machineID.getType(); }
|
||||
NodeID getVersion() const { return m_machineID.getNum(); }
|
||||
MachineType getType() const { return m_machineID.getType(); }
|
||||
|
||||
void initNetworkPtr(Network* net_ptr) { m_net_ptr = net_ptr; }
|
||||
|
||||
|
|
|
@ -83,12 +83,12 @@ class Message
|
|||
Tick delta = curTime - m_LastEnqueueTime;
|
||||
m_DelayedTicks += delta;
|
||||
}
|
||||
const Tick getDelayedTicks() const {return m_DelayedTicks;}
|
||||
Tick getDelayedTicks() const {return m_DelayedTicks;}
|
||||
|
||||
void setLastEnqueueTime(const Tick& time) { m_LastEnqueueTime = time; }
|
||||
const Tick getLastEnqueueTime() const {return m_LastEnqueueTime;}
|
||||
Tick getLastEnqueueTime() const {return m_LastEnqueueTime;}
|
||||
|
||||
const Tick& getTime() const { return m_time; }
|
||||
Tick getTime() const { return m_time; }
|
||||
void setMsgCounter(uint64_t c) { m_msg_counter = c; }
|
||||
uint64_t getMsgCounter() const { return m_msg_counter; }
|
||||
|
||||
|
|
|
@ -342,7 +342,7 @@ RubyMemoryControl::enqueueToDirectory(MemoryNode *req, Cycles latency)
|
|||
|
||||
// getBank returns an integer that is unique for each
|
||||
// bank across this memory controller.
|
||||
const int
|
||||
int
|
||||
RubyMemoryControl::getBank(const Addr addr) const
|
||||
{
|
||||
int dimm = (addr >> m_dimm_bit_0) & (m_dimms_per_channel - 1);
|
||||
|
@ -353,7 +353,7 @@ RubyMemoryControl::getBank(const Addr addr) const
|
|||
+ bank;
|
||||
}
|
||||
|
||||
const int
|
||||
int
|
||||
RubyMemoryControl::getRank(const Addr addr) const
|
||||
{
|
||||
int bank = getBank(addr);
|
||||
|
@ -364,7 +364,7 @@ RubyMemoryControl::getRank(const Addr addr) const
|
|||
|
||||
// getRank returns an integer that is unique for each rank
|
||||
// and independent of individual bank.
|
||||
const int
|
||||
int
|
||||
RubyMemoryControl::getRank(int bank) const
|
||||
{
|
||||
int rank = (bank / m_banks_per_rank);
|
||||
|
@ -373,7 +373,7 @@ RubyMemoryControl::getRank(int bank) const
|
|||
}
|
||||
|
||||
// Not used!
|
||||
const int
|
||||
int
|
||||
RubyMemoryControl::getChannel(const Addr addr) const
|
||||
{
|
||||
assert(false);
|
||||
|
@ -381,7 +381,7 @@ RubyMemoryControl::getChannel(const Addr addr) const
|
|||
}
|
||||
|
||||
// Not used!
|
||||
const int
|
||||
int
|
||||
RubyMemoryControl::getRow(const Addr addr) const
|
||||
{
|
||||
assert(false);
|
||||
|
|
|
@ -75,12 +75,12 @@ class RubyMemoryControl : public AbstractMemory, public Consumer
|
|||
void print(std::ostream& out) const override;
|
||||
void regStats() override;
|
||||
|
||||
const int getBank(const Addr addr) const;
|
||||
const int getRank(const Addr addr) const;
|
||||
int getBank(const Addr addr) const;
|
||||
int getRank(const Addr addr) const;
|
||||
|
||||
// not used in Ruby memory controller
|
||||
const int getChannel(const Addr addr) const;
|
||||
const int getRow(const Addr addr) const;
|
||||
int getChannel(const Addr addr) const;
|
||||
int getRow(const Addr addr) const;
|
||||
|
||||
//added by SS
|
||||
int getBanksPerRank() { return m_banks_per_rank; };
|
||||
|
@ -92,7 +92,7 @@ class RubyMemoryControl : public AbstractMemory, public Consumer
|
|||
|
||||
private:
|
||||
void enqueueToDirectory(MemoryNode *req, Cycles latency);
|
||||
const int getRank(int bank) const;
|
||||
int getRank(int bank) const;
|
||||
bool queueReady(int bank);
|
||||
void issueRequest(int bank);
|
||||
bool issueRefresh(int bank);
|
||||
|
|
|
@ -79,7 +79,7 @@ class RubySystem : public ClockedObject
|
|||
|
||||
SimpleMemory *getPhysMem() { return m_phys_mem; }
|
||||
Cycles getStartCycle() { return m_start_cycle; }
|
||||
const bool getAccessBackingStore() { return m_access_backing_store; }
|
||||
bool getAccessBackingStore() { return m_access_backing_store; }
|
||||
|
||||
// Public Methods
|
||||
Profiler*
|
||||
|
|
|
@ -290,7 +290,8 @@ Process::allocateMem(Addr vaddr, int64_t size, bool clobber)
|
|||
{
|
||||
int npages = divCeil(size, (int64_t)PageBytes);
|
||||
Addr paddr = system->allocPhysPages(npages);
|
||||
pTable->map(vaddr, paddr, size, clobber ? PageTableBase::Clobber : 0);
|
||||
pTable->map(vaddr, paddr, size,
|
||||
clobber ? PageTableBase::Clobber : PageTableBase::Zero);
|
||||
}
|
||||
|
||||
bool
|
||||
|
@ -454,7 +455,7 @@ bool
|
|||
Process::map(Addr vaddr, Addr paddr, int size, bool cacheable)
|
||||
{
|
||||
pTable->map(vaddr, paddr, size,
|
||||
cacheable ? 0 : PageTableBase::Uncacheable);
|
||||
cacheable ? PageTableBase::Zero : PageTableBase::Uncacheable);
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
|
@ -66,7 +66,7 @@ class GlobalSimLoopExitEvent : public GlobalEvent
|
|||
Tick repeat = 0);
|
||||
|
||||
const std::string getCause() const { return cause; }
|
||||
const int getCode() const { return code; }
|
||||
int getCode() const { return code; }
|
||||
|
||||
void process(); // process event
|
||||
|
||||
|
@ -86,7 +86,7 @@ class LocalSimLoopExitEvent : public Event
|
|||
LocalSimLoopExitEvent(const std::string &_cause, int c, Tick repeat = 0);
|
||||
|
||||
const std::string getCause() const { return cause; }
|
||||
const int getCode() const { return code; }
|
||||
int getCode() const { return code; }
|
||||
|
||||
void process() override; // process event
|
||||
|
||||
|
@ -111,7 +111,7 @@ class CountedDrainEvent : public Event
|
|||
|
||||
void setCount(int _count) { count = _count; }
|
||||
|
||||
const int getCount() const { return count; }
|
||||
int getCount() const { return count; }
|
||||
};
|
||||
|
||||
//
|
||||
|
|
Loading…
Reference in a new issue