sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

one step closer to booting

Browse source 
dev/alpha_access.h:
    removed my attempted hack to get console compling in linux
dev/tsunami.cc:
dev/tsunami.hh:
    added pchip pointer to tsunami
dev/tsunami_cchip.cc:
    made printing better
dev/tsunami_cchip.hh:
    commented out back pointer for now, since the parser has issues with it
dev/tsunamireg.h:
    added pchip registers

--HG--
extra : convert_revision : b4fceb7d08e757d9aaf37df8eb1bcd5ae29ce0da
This commit is contained in:
Ali Saidi 2004-01-21 20:14:10 -05:00
parent cb51c1503c
commit 0e805e1ff3
10 changed files with 543 additions and 18 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
dev/alpha_access.h
View file

@ -39,8 +39,6 @@
#include <ostream>
#include <string>
class Checkpoint;
#else
#include <inttypes.h>
#endif
// This structure hacked up from simos

9
dev/tsunami.cc
View file

@ -36,6 +36,7 @@
#include "dev/scsi_ctrl.hh"
#include "dev/tlaser_clock.hh"
#include "dev/tsunami_cchip.hh"
#include "dev/tsunami_pchip.hh"
#include "dev/tsunami.hh"
#include "sim/builder.hh"
#include "sim/system.hh"
@ -43,10 +44,10 @@
using namespace std;
Tsunami::Tsunami(const string &name, ScsiController *s, EtherDev *e,
TlaserClock *c, TsunamiCChip *cc, SimConsole *con,
TlaserClock *c, TsunamiCChip *cc, TsunamiPChip *pc, SimConsole *con,
IntrControl *ic, int intr_freq)
: SimObject(name), intctrl(ic), cons(con), scsi(s), ethernet(e),
clock(c), cchip(cc), interrupt_frequency(intr_freq)
clock(c), cchip(cc), pchip(pc), interrupt_frequency(intr_freq)
{
for (int i = 0; i < Tsunami::Max_CPUs; i++)
intr_sum_type[i] = 0;
@ -70,6 +71,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(Tsunami)
SimObjectParam<EtherDev *> ethernet;
SimObjectParam<TlaserClock *> clock;
SimObjectParam<TsunamiCChip *> cchip;
SimObjectParam<TsunamiPChip *> pchip;
SimObjectParam<SimConsole *> cons;
SimObjectParam<IntrControl *> intrctrl;
Param<int> interrupt_frequency;
@ -82,6 +84,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(Tsunami)
INIT_PARAM(ethernet, "ethernet controller"),
INIT_PARAM(clock, "turbolaser clock"),
INIT_PARAM(cchip, "cchip"),
INIT_PARAM(pchip, "pchip"),
INIT_PARAM(cons, "system console"),
INIT_PARAM(intrctrl, "interrupt controller"),
INIT_PARAM_DFLT(interrupt_frequency, "frequency of interrupts", 1200)
@ -92,7 +95,7 @@ END_INIT_SIM_OBJECT_PARAMS(Tsunami)
CREATE_SIM_OBJECT(Tsunami)
{
return new Tsunami(getInstanceName(), scsi, ethernet, clock,
cchip, cons, intrctrl, interrupt_frequency);
cchip, pchip, cons, intrctrl, interrupt_frequency);
}
REGISTER_SIM_OBJECT("Tsunami", Tsunami)

7
dev/tsunami.hh
View file

@ -38,6 +38,7 @@ class ScsiController;
class TlaserClock;
class EtherDev;
class TsunamiCChip;
class TsunamiPChip;
class Tsunami : public SimObject
{
@ -54,6 +55,7 @@ class Tsunami : public SimObject
TlaserClock *clock;
TsunamiCChip *cchip;
TsunamiPChip *pchip;
int intr_sum_type[Tsunami::Max_CPUs];
int ipi_pending[Tsunami::Max_CPUs];
@ -62,9 +64,8 @@ class Tsunami : public SimObject
public:
Tsunami(const std::string &name, ScsiController *scsi,
EtherDev *ethernet, TlaserClock *clock, TsunamiCChip *tc,
SimConsole *, IntrControl *intctrl,
int intrFreq);
EtherDev *ethernet, TlaserClock *clock, TsunamiCChip *cc, TsunamiPChip *pc,
SimConsole *, IntrControl *intctrl, int intrFreq);
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string &section);

22
dev/tsunami_cchip.cc
View file

@ -23,9 +23,9 @@
using namespace std;
TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t,
TsunamiCChip::TsunamiCChip(const string &name, /*Tsunami *t,*/
Addr addr, Addr mask, MemoryController *mmu)
: MmapDevice(name, addr, mask, mmu), tsunami(t)
: MmapDevice(name, addr, mask, mmu)/*, tsunami(t) */
{
for(int i=0; i < Tsunami::Max_CPUs; i++) {
dim[i] = 0;
@ -38,7 +38,7 @@ TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t,
Fault
TsunamiCChip::read(MemReqPtr req, uint8_t *data)
{
DPRINTF(Tsunami, "cchip read va=%#x size=%d\n",
DPRINTF(Tsunami, "read va=%#x size=%d\n",
req->vaddr, req->size);
Addr daddr = (req->paddr & addr_mask) >> 6;
@ -106,6 +106,8 @@ TsunamiCChip::read(MemReqPtr req, uint8_t *data)
case TSDEV_CC_MPR3:
panic("TSDEV_CC_MPRx not implemented\n");
return No_Fault;
default:
panic("default in cchip read reached, accessing 0x%x\n");
} // uint64_t
break;
@ -113,7 +115,7 @@ TsunamiCChip::read(MemReqPtr req, uint8_t *data)
case sizeof(uint16_t):
case sizeof(uint8_t):
default:
panic("invalid access size(?) for tsunami register!");
panic("invalid access size(?) for tsunami register!\n");
}
DPRINTFN("Tsunami CChip ERROR: read daddr=%#x size=%d\n", daddr, req->size);
@ -123,7 +125,7 @@ TsunamiCChip::read(MemReqPtr req, uint8_t *data)
Fault
TsunamiCChip::write(MemReqPtr req, const uint8_t *data)
{
DPRINTF(Tsunami, "Tsunami CChip write - va=%#x size=%d \n",
DPRINTF(Tsunami, "write - va=%#x size=%d \n",
req->vaddr, req->size);
Addr daddr = (req->paddr & addr_mask) >> 6;
@ -183,6 +185,8 @@ TsunamiCChip::write(MemReqPtr req, const uint8_t *data)
case TSDEV_CC_MPR3:
panic("TSDEV_CC_MPRx write not implemented\n");
return No_Fault;
default:
panic("default in cchip read reached, accessing 0x%x\n");
}
break;
@ -190,7 +194,7 @@ TsunamiCChip::write(MemReqPtr req, const uint8_t *data)
case sizeof(uint16_t):
case sizeof(uint8_t):
default:
panic("invalid access size(?) for tsunami register!");
panic("invalid access size(?) for tsunami register!\n");
}
DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size);
@ -212,7 +216,7 @@ TsunamiCChip::unserialize(Checkpoint *cp, const std::string &section)
BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
SimObjectParam<Tsunami *> tsunami;
// SimObjectParam<Tsunami *> tsunami;
SimObjectParam<MemoryController *> mmu;
Param<Addr> addr;
Param<Addr> mask;
@ -221,7 +225,7 @@ END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
INIT_PARAM(tsunami, "Tsunami"),
// INIT_PARAM(tsunami, "Tsunami"),
INIT_PARAM(mmu, "Memory Controller"),
INIT_PARAM(addr, "Device Address"),
INIT_PARAM(mask, "Address Mask")
@ -230,7 +234,7 @@ END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
CREATE_SIM_OBJECT(TsunamiCChip)
{
return new TsunamiCChip(getInstanceName(), tsunami, addr, mask, mmu);
return new TsunamiCChip(getInstanceName(), /*tsunami,*/ addr, mask, mmu);
}
REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip)

2
dev/tsunami_cchip.hh
View file

@ -50,7 +50,7 @@ class TsunamiCChip : public MmapDevice
uint64_t drir;
public:
TsunamiCChip(const std::string &name, Tsunami *t,
TsunamiCChip(const std::string &name, /*Tsunami *t,*/
Addr addr, Addr mask, MemoryController *mmu);
virtual Fault read(MemReqPtr req, uint8_t *data);

93
dev/tsunami_dma.cc Normal file
View file

@ -0,0 +1,93 @@
/* $Id$ */
/* @file
* Tsunami DMA fake
*/
#include <deque>
#include <string>
#include <vector>
#include "base/trace.hh"
#include "cpu/exec_context.hh"
#include "dev/console.hh"
#include "dev/etherdev.hh"
#include "dev/scsi_ctrl.hh"
#include "dev/tlaser_clock.hh"
#include "dev/tsunami_dma.hh"
#include "dev/tsunamireg.h"
#include "dev/tsunami.hh"
#include "mem/functional_mem/memory_control.hh"
#include "sim/builder.hh"
#include "sim/system.hh"
using namespace std;
TsunamiDMA::TsunamiDMA(const string &name, /*Tsunami *t,*/
Addr addr, Addr mask, MemoryController *mmu)
: MmapDevice(name, addr, mask, mmu)/*, tsunami(t) */
{
}
Fault
TsunamiDMA::read(MemReqPtr req, uint8_t *data)
{
DPRINTF(Tsunami, "dma read va=%#x size=%d IOPorrt=%#x\n",
req->vaddr, req->size, req->vaddr & 0xfff);
// Addr daddr = (req->paddr & addr_mask) >> 6;
// ExecContext *xc = req->xc;
// int cpuid = xc->cpu_id;
*(uint64_t*)data = 0x00;
return No_Fault;
}
Fault
TsunamiDMA::write(MemReqPtr req, const uint8_t *data)
{
DPRINTF(Tsunami, "dma write - va=%#x size=%d IOPort=%#x\n",
req->vaddr, req->size, req->vaddr & 0xfff);
//Addr daddr = (req->paddr & addr_mask) >> 6;
return No_Fault;
}
void
TsunamiDMA::serialize(std::ostream &os)
{
// code should be written
}
void
TsunamiDMA::unserialize(Checkpoint *cp, const std::string &section)
{
//code should be written
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiDMA)
// SimObjectParam<Tsunami *> tsunami;
SimObjectParam<MemoryController *> mmu;
Param<Addr> addr;
Param<Addr> mask;
END_DECLARE_SIM_OBJECT_PARAMS(TsunamiDMA)
BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiDMA)
// INIT_PARAM(tsunami, "Tsunami"),
INIT_PARAM(mmu, "Memory Controller"),
INIT_PARAM(addr, "Device Address"),
INIT_PARAM(mask, "Address Mask")
END_INIT_SIM_OBJECT_PARAMS(TsunamiDMA)
CREATE_SIM_OBJECT(TsunamiDMA)
{
return new TsunamiDMA(getInstanceName(), /*tsunami,*/ addr, mask, mmu);
}
REGISTER_SIM_OBJECT("TsunamiDMA", TsunamiDMA)

59
dev/tsunami_dma.hh Normal file
View file

@ -0,0 +1,59 @@
/*
* Copyright (c) 2003 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* @file
* Tsunnami Fake DMA memory map
*/
#ifndef __TSUNAMI_DMA_HH__
#define __TSUNAMI_DMA_HH__
#include "mem/functional_mem/mmap_device.hh"
#include "dev/tsunami.hh"
/*
* Tsunami CChip
*/
class TsunamiDMA : public MmapDevice
{
public:
protected:
public:
TsunamiDMA(const std::string &name, /*Tsunami *t,*/
Addr addr, Addr mask, MemoryController *mmu);
virtual Fault read(MemReqPtr req, uint8_t *data);
virtual Fault write(MemReqPtr req, const uint8_t *data);
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string &section);
};
#endif // __TSUNAMI_DMA_HH__

258
dev/tsunami_pchip.cc Normal file
View file

@ -0,0 +1,258 @@
/* $Id$ */
/* @file
* Tsunami PChip (pci)
*/
#include <deque>
#include <string>
#include <vector>
#include "base/trace.hh"
#include "cpu/exec_context.hh"
#include "dev/console.hh"
#include "dev/etherdev.hh"
#include "dev/scsi_ctrl.hh"
#include "dev/tlaser_clock.hh"
#include "dev/tsunami_pchip.hh"
#include "dev/tsunamireg.h"
#include "dev/tsunami.hh"
#include "mem/functional_mem/memory_control.hh"
#include "sim/builder.hh"
#include "sim/system.hh"
using namespace std;
TsunamiPChip::TsunamiPChip(const string &name, /*Tsunami *t,*/
Addr addr, Addr mask, MemoryController *mmu)
: MmapDevice(name, addr, mask, mmu)/*, tsunami(t) */
{
wsba0 = 0;
wsba1 = 0;
wsba2 = 0;
wsba3 = 0;
wsm0 = 0;
wsm1 = 0;
wsm2 = 0;
wsm3 = 0;
tba0 = 0;
tba1 = 0;
tba2 = 0;
tba3 = 0;
}
Fault
TsunamiPChip::read(MemReqPtr req, uint8_t *data)
{
DPRINTF(Tsunami, "read va=%#x size=%d\n",
req->vaddr, req->size);
Addr daddr = (req->paddr & addr_mask) >> 6;
// ExecContext *xc = req->xc;
// int cpuid = xc->cpu_id;
switch (req->size) {
case sizeof(uint64_t):
switch(daddr) {
case TSDEV_PC_WSBA0:
*(uint64_t*)data = wsba0;
return No_Fault;
case TSDEV_PC_WSBA1:
*(uint64_t*)data = wsba1;
return No_Fault;
case TSDEV_PC_WSBA2:
*(uint64_t*)data = wsba2;
return No_Fault;
case TSDEV_PC_WSBA3:
*(uint64_t*)data = wsba3;
return No_Fault;
case TSDEV_PC_WSM0:
*(uint64_t*)data = wsm0;
return No_Fault;
case TSDEV_PC_WSM1:
*(uint64_t*)data = wsm1;
return No_Fault;
case TSDEV_PC_WSM2:
*(uint64_t*)data = wsm2;
return No_Fault;
case TSDEV_PC_WSM3:
*(uint64_t*)data = wsm3;
return No_Fault;
case TSDEV_PC_TBA0:
*(uint64_t*)data = tba0;
return No_Fault;
case TSDEV_PC_TBA1:
*(uint64_t*)data = tba1;
return No_Fault;
case TSDEV_PC_TBA2:
*(uint64_t*)data = tba2;
return No_Fault;
case TSDEV_PC_TBA3:
*(uint64_t*)data = tba3;
return No_Fault;
case TSDEV_PC_PCTL:
// might want to change the clock??
*(uint64_t*)data = 0x00; // try this
return No_Fault;
case TSDEV_PC_PLAT:
panic("PC_PLAT not implemented\n");
case TSDEV_PC_RES:
panic("PC_RES not implemented\n");
case TSDEV_PC_PERROR:
panic("PC_PERROR not implemented\n");
case TSDEV_PC_PERRMASK:
panic("PC_PERRMASK not implemented\n");
case TSDEV_PC_PERRSET:
panic("PC_PERRSET not implemented\n");
case TSDEV_PC_TLBIV:
panic("PC_TLBIV not implemented\n");
case TSDEV_PC_TLBIA:
*(uint64_t*)data = 0x00; // shouldn't be readable, but linux
return No_Fault;
case TSDEV_PC_PMONCTL:
panic("PC_PMONCTL not implemented\n");
case TSDEV_PC_PMONCNT:
panic("PC_PMONCTN not implemented\n");
default:
panic("Default in PChip Read reached reading 0x%x\n", daddr);
} // uint64_t
break;
case sizeof(uint32_t):
case sizeof(uint16_t):
case sizeof(uint8_t):
default:
panic("invalid access size(?) for tsunami register!\n\n");
}
DPRINTFN("Tsunami PChip ERROR: read daddr=%#x size=%d\n", daddr, req->size);
return No_Fault;
}
Fault
TsunamiPChip::write(MemReqPtr req, const uint8_t *data)
{
DPRINTF(Tsunami, "write - va=%#x size=%d \n",
req->vaddr, req->size);
Addr daddr = (req->paddr & addr_mask) >> 6;
switch (req->size) {
case sizeof(uint64_t):
switch(daddr) {
case TSDEV_PC_WSBA0:
wsba0 = *(uint64_t*)data;
return No_Fault;
case TSDEV_PC_WSBA1:
wsba1 = *(uint64_t*)data;
return No_Fault;
case TSDEV_PC_WSBA2:
wsba2 = *(uint64_t*)data;
return No_Fault;
case TSDEV_PC_WSBA3:
wsba3 = *(uint64_t*)data;
return No_Fault;
case TSDEV_PC_WSM0:
wsm0 = *(uint64_t*)data;
return No_Fault;
case TSDEV_PC_WSM1:
wsm1 = *(uint64_t*)data;
return No_Fault;
case TSDEV_PC_WSM2:
wsm2 = *(uint64_t*)data;
return No_Fault;
case TSDEV_PC_WSM3:
wsm3 = *(uint64_t*)data;
return No_Fault;
case TSDEV_PC_TBA0:
tba0 = *(uint64_t*)data;
return No_Fault;
case TSDEV_PC_TBA1:
tba1 = *(uint64_t*)data;
return No_Fault;
case TSDEV_PC_TBA2:
tba2 = *(uint64_t*)data;
return No_Fault;
case TSDEV_PC_TBA3:
tba3 = *(uint64_t*)data;
return No_Fault;
case TSDEV_PC_PCTL:
// might want to change the clock??
//*(uint64_t*)data; // try this
return No_Fault;
case TSDEV_PC_PLAT:
panic("PC_PLAT not implemented\n");
case TSDEV_PC_RES:
panic("PC_RES not implemented\n");
case TSDEV_PC_PERROR:
panic("PC_PERROR not implemented\n");
case TSDEV_PC_PERRMASK:
panic("PC_PERRMASK not implemented\n");
case TSDEV_PC_PERRSET:
panic("PC_PERRSET not implemented\n");
case TSDEV_PC_TLBIV:
panic("PC_TLBIV not implemented\n");
case TSDEV_PC_TLBIA:
return No_Fault; // value ignored, supposted to invalidate SG TLB
case TSDEV_PC_PMONCTL:
panic("PC_PMONCTL not implemented\n");
case TSDEV_PC_PMONCNT:
panic("PC_PMONCTN not implemented\n");
default:
panic("Default in PChip Read reached reading 0x%x\n", daddr);
} // uint64_t
break;
case sizeof(uint32_t):
case sizeof(uint16_t):
case sizeof(uint8_t):
default:
panic("invalid access size(?) for tsunami register!\n\n");
}
DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size);
return No_Fault;
}
void
TsunamiPChip::serialize(std::ostream &os)
{
// code should be written
}
void
TsunamiPChip::unserialize(Checkpoint *cp, const std::string &section)
{
//code should be written
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
/* SimObjectParam<Tsunami *> tsunami;*/
SimObjectParam<MemoryController *> mmu;
Param<Addr> addr;
Param<Addr> mask;
END_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
/*INIT_PARAM(tsunami, "Tsunami"),*/
INIT_PARAM(mmu, "Memory Controller"),
INIT_PARAM(addr, "Device Address"),
INIT_PARAM(mask, "Address Mask")
END_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
CREATE_SIM_OBJECT(TsunamiPChip)
{
return new TsunamiPChip(getInstanceName(), /*tsunami,*/ addr, mask, mmu);
}
REGISTER_SIM_OBJECT("TsunamiPChip", TsunamiPChip)

74
dev/tsunami_pchip.hh Normal file
View file

@ -0,0 +1,74 @@
/*
* Copyright (c) 2003 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* @file
* Tsunami PChip
*/
#ifndef __TSUNAMI_PCHIP_HH__
#define __TSUNAMI_PCHIP_HH__
#include "mem/functional_mem/mmap_device.hh"
#include "dev/tsunami.hh"
/*
* Tsunami PChip
*/
class TsunamiPChip : public MmapDevice
{
public:
protected:
Tsunami *tsunami;
uint64_t wsba0;
uint64_t wsba1;
uint64_t wsba2;
uint64_t wsba3;
uint64_t wsm0;
uint64_t wsm1;
uint64_t wsm2;
uint64_t wsm3;
uint64_t tba0;
uint64_t tba1;
uint64_t tba2;
uint64_t tba3;
public:
TsunamiPChip(const std::string &name, /*Tsunami *t,*/
Addr addr, Addr mask, MemoryController *mmu);
virtual Fault read(MemReqPtr req, uint8_t *data);
virtual Fault write(MemReqPtr req, const uint8_t *data);
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string &section);
};
#endif // __TSUNAMI_PCHIP_HH__

35
dev/tsunamireg.h
View file

@ -2,6 +2,7 @@
#ifndef __TSUNAMIREG_H__
#define __TSUNAMIREG_H__
// CChip Registers
#define TSDEV_CC_CSR 0x00
#define TSDEV_CC_MTR 0x01
#define TSDEV_CC_MISC 0x02
@ -30,4 +31,38 @@
#define TSDEV_CC_IIC2 0x1C
#define TSDEV_CC_IIC3 0x1D
// PChip Registers
#define TSDEV_PC_WSBA0 0x00
#define TSDEV_PC_WSBA1 0x01
#define TSDEV_PC_WSBA2 0x02
#define TSDEV_PC_WSBA3 0x03
#define TSDEV_PC_WSM0 0x04
#define TSDEV_PC_WSM1 0x05
#define TSDEV_PC_WSM2 0x06
#define TSDEV_PC_WSM3 0x07
#define TSDEV_PC_TBA0 0x08
#define TSDEV_PC_TBA1 0x09
#define TSDEV_PC_TBA2 0x0A
#define TSDEV_PC_TBA3 0x0B
#define TSDEV_PC_PCTL 0x0C
#define TSDEV_PC_PLAT 0x0D
#define TSDEV_PC_RES 0x0E
#define TSDEV_PC_PERROR 0x0F
#define TSDEV_PC_PERRMASK 0x10
#define TSDEV_PC_PERRSET 0x11
#define TSDEV_PC_TLBIV 0x12
#define TSDEV_PC_TLBIA 0x13
#define TSDEV_PC_PMONCTL 0x14
#define TSDEV_PC_PMONCNT 0x15
#define TSDEV_PC_SPST 0x20
// DChip Registers
#define TSDEV_DC_DSC 0x20
#define TSDEV_DC_STR 0x21
#define TSDEV_DC_DREV 0x22
#define TSDEV_DC_DSC2 0x23
#endif // __TSUNAMIREG_H__