0e805e1ff3
dev/alpha_access.h:
removed my attempted hack to get console compling in linux
dev/tsunami.cc:
dev/tsunami.hh:
added pchip pointer to tsunami
dev/tsunami_cchip.cc:
made printing better
dev/tsunami_cchip.hh:
commented out back pointer for now, since the parser has issues with it
dev/tsunamireg.h:
added pchip registers
--HG--
extra : convert_revision : b4fceb7d08e757d9aaf37df8eb1bcd5ae29ce0da
240 lines
7.2 KiB
C++
240 lines
7.2 KiB
C++
/* $Id$ */
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/* @file
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* Tsunami CChip (processor, memory, or IO)
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*/
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#include <deque>
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#include <string>
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#include <vector>
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#include "base/trace.hh"
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#include "cpu/exec_context.hh"
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#include "dev/console.hh"
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#include "dev/etherdev.hh"
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#include "dev/scsi_ctrl.hh"
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#include "dev/tlaser_clock.hh"
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#include "dev/tsunami_cchip.hh"
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#include "dev/tsunamireg.h"
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#include "dev/tsunami.hh"
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#include "mem/functional_mem/memory_control.hh"
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#include "sim/builder.hh"
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#include "sim/system.hh"
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using namespace std;
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TsunamiCChip::TsunamiCChip(const string &name, /*Tsunami *t,*/
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Addr addr, Addr mask, MemoryController *mmu)
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: MmapDevice(name, addr, mask, mmu)/*, tsunami(t) */
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{
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for(int i=0; i < Tsunami::Max_CPUs; i++) {
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dim[i] = 0;
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dir[i] = 0;
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}
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drir = 0;
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}
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Fault
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TsunamiCChip::read(MemReqPtr req, uint8_t *data)
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{
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DPRINTF(Tsunami, "read va=%#x size=%d\n",
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req->vaddr, req->size);
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Addr daddr = (req->paddr & addr_mask) >> 6;
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// ExecContext *xc = req->xc;
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// int cpuid = xc->cpu_id;
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switch (req->size) {
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case sizeof(uint64_t):
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switch(daddr) {
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case TSDEV_CC_CSR:
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*(uint64_t*)data = 0x0;
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return No_Fault;
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case TSDEV_CC_MTR:
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panic("TSDEV_CC_MTR not implemeted\n");
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return No_Fault;
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case TSDEV_CC_MISC:
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panic("TSDEV_CC_MISC not implemented\n");
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return No_Fault;
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case TSDEV_CC_AAR0:
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case TSDEV_CC_AAR1:
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case TSDEV_CC_AAR2:
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case TSDEV_CC_AAR3:
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panic("TSDEV_CC_AARx not implemeted\n");
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return No_Fault;
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case TSDEV_CC_DIM0:
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*(uint64_t*)data = dim[0];
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return No_Fault;
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case TSDEV_CC_DIM1:
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*(uint64_t*)data = dim[1];
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return No_Fault;
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case TSDEV_CC_DIM2:
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*(uint64_t*)data = dim[2];
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return No_Fault;
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case TSDEV_CC_DIM3:
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*(uint64_t*)data = dim[3];
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return No_Fault;
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case TSDEV_CC_DIR0:
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*(uint64_t*)data = dir[0];
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return No_Fault;
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case TSDEV_CC_DIR1:
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*(uint64_t*)data = dir[1];
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return No_Fault;
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case TSDEV_CC_DIR2:
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*(uint64_t*)data = dir[2];
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return No_Fault;
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case TSDEV_CC_DIR3:
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*(uint64_t*)data = dir[3];
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return No_Fault;
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case TSDEV_CC_DRIR:
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*(uint64_t*)data = drir;
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return No_Fault;
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case TSDEV_CC_PRBEN:
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panic("TSDEV_CC_PRBEN not implemented\n");
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return No_Fault;
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case TSDEV_CC_IIC0:
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case TSDEV_CC_IIC1:
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case TSDEV_CC_IIC2:
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case TSDEV_CC_IIC3:
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panic("TSDEV_CC_IICx not implemented\n");
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return No_Fault;
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case TSDEV_CC_MPR0:
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case TSDEV_CC_MPR1:
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case TSDEV_CC_MPR2:
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case TSDEV_CC_MPR3:
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panic("TSDEV_CC_MPRx not implemented\n");
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return No_Fault;
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default:
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panic("default in cchip read reached, accessing 0x%x\n");
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} // uint64_t
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break;
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case sizeof(uint32_t):
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case sizeof(uint16_t):
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case sizeof(uint8_t):
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default:
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panic("invalid access size(?) for tsunami register!\n");
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}
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DPRINTFN("Tsunami CChip ERROR: read daddr=%#x size=%d\n", daddr, req->size);
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return No_Fault;
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}
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Fault
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TsunamiCChip::write(MemReqPtr req, const uint8_t *data)
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{
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DPRINTF(Tsunami, "write - va=%#x size=%d \n",
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req->vaddr, req->size);
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Addr daddr = (req->paddr & addr_mask) >> 6;
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switch (req->size) {
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case sizeof(uint64_t):
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switch(daddr) {
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case TSDEV_CC_CSR:
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panic("TSDEV_CC_CSR write\n");
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return No_Fault;
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case TSDEV_CC_MTR:
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panic("TSDEV_CC_MTR write not implemented\n");
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return No_Fault;
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case TSDEV_CC_MISC:
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panic("TSDEV_CC_MISC write not implemented\n");
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return No_Fault;
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case TSDEV_CC_AAR0:
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case TSDEV_CC_AAR1:
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case TSDEV_CC_AAR2:
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case TSDEV_CC_AAR3:
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panic("TSDEV_CC_AARx write not implemeted\n");
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return No_Fault;
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case TSDEV_CC_DIM0:
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dim[0] = *(uint64_t*)data;
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return No_Fault;
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case TSDEV_CC_DIM1:
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dim[1] = *(uint64_t*)data;
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return No_Fault;
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case TSDEV_CC_DIM2:
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dim[2] = *(uint64_t*)data;
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return No_Fault;
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case TSDEV_CC_DIM3:
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dim[3] = *(uint64_t*)data;
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return No_Fault;
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case TSDEV_CC_DIR0:
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case TSDEV_CC_DIR1:
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case TSDEV_CC_DIR2:
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case TSDEV_CC_DIR3:
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panic("TSDEV_CC_DIR write not implemented\n");
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return No_Fault;
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case TSDEV_CC_DRIR:
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panic("TSDEV_CC_DRIR write not implemented\n");
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return No_Fault;
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case TSDEV_CC_PRBEN:
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panic("TSDEV_CC_PRBEN write not implemented\n");
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return No_Fault;
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case TSDEV_CC_IIC0:
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case TSDEV_CC_IIC1:
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case TSDEV_CC_IIC2:
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case TSDEV_CC_IIC3:
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panic("TSDEV_CC_IICx write not implemented\n");
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return No_Fault;
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case TSDEV_CC_MPR0:
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case TSDEV_CC_MPR1:
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case TSDEV_CC_MPR2:
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case TSDEV_CC_MPR3:
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panic("TSDEV_CC_MPRx write not implemented\n");
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return No_Fault;
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default:
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panic("default in cchip read reached, accessing 0x%x\n");
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}
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break;
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case sizeof(uint32_t):
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case sizeof(uint16_t):
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case sizeof(uint8_t):
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default:
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panic("invalid access size(?) for tsunami register!\n");
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}
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DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size);
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return No_Fault;
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}
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void
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TsunamiCChip::serialize(std::ostream &os)
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{
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// code should be written
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}
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void
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TsunamiCChip::unserialize(Checkpoint *cp, const std::string §ion)
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{
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//code should be written
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}
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
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// SimObjectParam<Tsunami *> tsunami;
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SimObjectParam<MemoryController *> mmu;
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Param<Addr> addr;
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Param<Addr> mask;
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END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
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BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
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// INIT_PARAM(tsunami, "Tsunami"),
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INIT_PARAM(mmu, "Memory Controller"),
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INIT_PARAM(addr, "Device Address"),
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INIT_PARAM(mask, "Address Mask")
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END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
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CREATE_SIM_OBJECT(TsunamiCChip)
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{
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return new TsunamiCChip(getInstanceName(), /*tsunami,*/ addr, mask, mmu);
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}
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REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip)
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