CPU: Trim unnecessary includes from some common files.
This reduces the scope of those includes and makes it less likely for there to be a dependency loop. This also moves the hashing functions associated with ExtMachInst objects to be with the ExtMachInst definitions and out of utility.hh.
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8f3fbd2d13
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14 changed files with 54 additions and 49 deletions
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@ -33,6 +33,7 @@
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#include "arch/alpha/isa.hh"
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#include "base/misc.hh"
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#include "cpu/thread_context.hh"
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#include "sim/serialize.hh"
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namespace AlphaISA
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{
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@ -44,6 +44,7 @@
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#define __ARCH_ARM_TYPES_HH__
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#include "base/bitunion.hh"
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#include "base/hashmap.hh"
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#include "base/types.hh"
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namespace ArmISA
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@ -269,4 +270,13 @@ namespace ArmISA
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} // namespace ArmISA
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namespace __hash_namespace {
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template<>
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struct hash<ArmISA::ExtMachInst> : public hash<uint32_t> {
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size_t operator()(const ArmISA::ExtMachInst &emi) const {
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return hash<uint32_t>::operator()((uint32_t)emi);
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};
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};
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}
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#endif
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@ -47,21 +47,11 @@
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#include "arch/arm/miscregs.hh"
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#include "arch/arm/types.hh"
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#include "base/hashmap.hh"
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#include "base/misc.hh"
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#include "base/trace.hh"
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#include "base/types.hh"
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#include "cpu/thread_context.hh"
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namespace __hash_namespace {
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template<>
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struct hash<ArmISA::ExtMachInst> : public hash<uint32_t> {
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size_t operator()(const ArmISA::ExtMachInst &emi) const {
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return hash<uint32_t>::operator()((uint32_t)emi);
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};
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};
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}
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namespace ArmISA {
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inline bool
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@ -30,6 +30,7 @@
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#include "arch/power/insts/branch.hh"
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#include "base/loader/symtab.hh"
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#include "cpu/thread_context.hh"
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using namespace PowerISA;
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@ -32,6 +32,7 @@
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#define __ARCH_POWER_TYPES_HH__
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#include "base/bitunion.hh"
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#include "base/hashmap.hh"
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#include "base/types.hh"
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namespace PowerISA
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@ -88,4 +89,15 @@ struct CoreSpecific {
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} // PowerISA namspace
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namespace __hash_namespace {
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template<>
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struct hash<PowerISA::ExtMachInst> : public hash<uint32_t> {
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size_t operator()(const PowerISA::ExtMachInst &emi) const {
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return hash<uint32_t>::operator()((uint32_t)emi);
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};
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};
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} // __hash_namespace namespace
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#endif // __ARCH_POWER_TYPES_HH__
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@ -35,23 +35,9 @@
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#ifndef __ARCH_POWER_UTILITY_HH__
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#define __ARCH_POWER_UTILITY_HH__
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#include "arch/power/miscregs.hh"
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#include "arch/power/types.hh"
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#include "base/hashmap.hh"
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#include "base/types.hh"
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#include "cpu/thread_context.hh"
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namespace __hash_namespace {
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template<>
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struct hash<PowerISA::ExtMachInst> : public hash<uint32_t> {
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size_t operator()(const PowerISA::ExtMachInst &emi) const {
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return hash<uint32_t>::operator()((uint32_t)emi);
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};
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};
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} // __hash_namespace namespace
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namespace PowerISA {
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/**
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@ -44,6 +44,7 @@
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#include "base/bitunion.hh"
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#include "base/cprintf.hh"
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#include "base/hashmap.hh"
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#include "base/types.hh"
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#include "sim/serialize.hh"
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@ -225,6 +226,26 @@ namespace X86ISA
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};
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};
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namespace __hash_namespace {
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template<>
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struct hash<X86ISA::ExtMachInst> {
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size_t operator()(const X86ISA::ExtMachInst &emi) const {
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return (((uint64_t)emi.legacy << 56) |
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((uint64_t)emi.rex << 48) |
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((uint64_t)emi.modRM << 40) |
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((uint64_t)emi.sib << 32) |
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((uint64_t)emi.opcode.num << 24) |
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((uint64_t)emi.opcode.prefixA << 16) |
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((uint64_t)emi.opcode.prefixB << 8) |
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((uint64_t)emi.opcode.op)) ^
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emi.immediate ^ emi.displacement ^
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emi.mode ^
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emi.opSize ^ emi.addrSize ^
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emi.stackSize ^ emi.dispSize;
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};
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};
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}
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// These two functions allow ExtMachInst to be used with SERIALIZE_SCALAR
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// and UNSERIALIZE_SCALAR.
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template <>
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@ -50,26 +50,6 @@
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class ThreadContext;
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namespace __hash_namespace {
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template<>
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struct hash<X86ISA::ExtMachInst> {
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size_t operator()(const X86ISA::ExtMachInst &emi) const {
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return (((uint64_t)emi.legacy << 56) |
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((uint64_t)emi.rex << 48) |
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((uint64_t)emi.modRM << 40) |
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((uint64_t)emi.sib << 32) |
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((uint64_t)emi.opcode.num << 24) |
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((uint64_t)emi.opcode.prefixA << 16) |
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((uint64_t)emi.opcode.prefixB << 8) |
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((uint64_t)emi.opcode.op)) ^
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emi.immediate ^ emi.displacement ^
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emi.mode ^
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emi.opSize ^ emi.addrSize ^
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emi.stackSize ^ emi.dispSize;
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};
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};
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}
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namespace X86ISA
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{
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uint64_t getArgument(ThreadContext *tc, int number, bool fp);
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@ -34,6 +34,7 @@
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#include <iomanip>
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#include "arch/isa_traits.hh"
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#include "arch/utility.hh"
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#include "base/loader/symtab.hh"
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#include "cpu/base.hh"
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#include "cpu/exetrace.hh"
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@ -35,12 +35,12 @@
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#include "base/trace.hh"
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#include "base/types.hh"
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#include "cpu/static_inst.hh"
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#include "cpu/thread_context.hh"
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#include "params/ExeTracer.hh"
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#include "sim/insttracer.hh"
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class ThreadContext;
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namespace Trace {
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class ExeTracerRecord : public InstRecord
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@ -34,6 +34,7 @@
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#include <string>
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#include "arch/isa_traits.hh"
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#include "arch/utility.hh"
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#include "config/the_isa.hh"
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#include "cpu/base.hh"
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#include "cpu/simple_thread.hh"
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@ -35,9 +35,8 @@
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#include <string>
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#include "arch/isa_traits.hh"
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#include "arch/utility.hh"
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#include "arch/registers.hh"
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#include "config/the_isa.hh"
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#include "base/bitfield.hh"
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#include "base/hashmap.hh"
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#include "base/misc.hh"
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#include "base/refcnt.hh"
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@ -31,12 +31,14 @@
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#ifndef __CPU_THREAD_CONTEXT_HH__
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#define __CPU_THREAD_CONTEXT_HH__
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#include <string>
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#include <iostream>
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#include "arch/registers.hh"
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#include "arch/types.hh"
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#include "base/types.hh"
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#include "config/full_system.hh"
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#include "config/the_isa.hh"
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#include "sim/serialize.hh"
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// @todo: Figure out a more architecture independent way to obtain the ITB and
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// DTB pointers.
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@ -45,8 +47,8 @@ namespace TheISA
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class TLB;
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}
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class BaseCPU;
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class Checkpoint;
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class EndQuiesceEvent;
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class Event;
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class TranslatingPort;
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class FunctionalPort;
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class VirtualPort;
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@ -36,6 +36,7 @@
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#include <iostream>
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#include <string>
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#include "arch/utility.hh"
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#include "sim/syscall_emul.hh"
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#include "base/chunk_generator.hh"
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#include "base/trace.hh"
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