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tests: update regression tests for changes in stats output and changes in ruby.

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This commit is contained in:
Nathan Binkert 2009-07-06 15:49:48 -07:00
parent da704f52e5
commit 0c1a69e768
55 changed files with 3303 additions and 6629 deletions
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5
tests/quick/00.hello/ref/alpha/linux/simple-atomic-ruby/config.ini
View file

@ -81,10 +81,9 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=RubyMemory
clock=1
config_file=
config_options=
config_file=build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic-ruby/ruby.config
debug=false
debug_file=
debug_file=ruby.debug
file=
latency=30000
latency_var=0

819
tests/quick/00.hello/ref/alpha/linux/simple-atomic-ruby/ruby.stats
View file

@ -1,258 +1,81 @@
================ Begin RubySystem Configuration Print ================
Ruby Configuration
------------------
protocol: MOSI_SMP_bcast
compiled_at: 22:51:11, May 4 2009
RUBY_DEBUG: false
hostname: piton
g_RANDOM_SEED: 1
g_DEADLOCK_THRESHOLD: 500000
RANDOMIZATION: false
g_SYNTHETIC_DRIVER: false
g_DETERMINISTIC_DRIVER: false
g_FILTERING_ENABLED: false
g_DISTRIBUTED_PERSISTENT_ENABLED: true
g_DYNAMIC_TIMEOUT_ENABLED: true
g_RETRY_THRESHOLD: 1
g_FIXED_TIMEOUT_LATENCY: 300
g_trace_warmup_length: 1000000
g_bash_bandwidth_adaptive_threshold: 0.75
g_tester_length: 0
g_synthetic_locks: 2048
g_deterministic_addrs: 1
g_SpecifiedGenerator: DetermInvGenerator
g_callback_counter: 0
g_NUM_COMPLETIONS_BEFORE_PASS: 0
g_NUM_SMT_THREADS: 1
g_think_time: 5
g_hold_time: 5
g_wait_time: 5
PROTOCOL_DEBUG_TRACE: true
DEBUG_FILTER_STRING: none
DEBUG_VERBOSITY_STRING: none
DEBUG_START_TIME: 0
DEBUG_OUTPUT_FILENAME: none
SIMICS_RUBY_MULTIPLIER: 4
OPAL_RUBY_MULTIPLIER: 1
TRANSACTION_TRACE_ENABLED: false
USER_MODE_DATA_ONLY: false
PROFILE_HOT_LINES: false
PROFILE_ALL_INSTRUCTIONS: false
PRINT_INSTRUCTION_TRACE: false
g_DEBUG_CYCLE: 0
BLOCK_STC: false
PERFECT_MEMORY_SYSTEM: false
PERFECT_MEMORY_SYSTEM_LATENCY: 0
DATA_BLOCK: false
REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH: false
L1_CACHE_ASSOC: 4
L1_CACHE_NUM_SETS_BITS: 8
L2_CACHE_ASSOC: 4
L2_CACHE_NUM_SETS_BITS: 16
g_MEMORY_SIZE_BYTES: 4294967296
g_DATA_BLOCK_BYTES: 64
g_PAGE_SIZE_BYTES: 4096
g_REPLACEMENT_POLICY: PSEDUO_LRU
g_NUM_PROCESSORS: 1
g_NUM_L2_BANKS: 1
g_NUM_MEMORIES: 1
g_PROCS_PER_CHIP: 1
g_NUM_CHIPS: 1
g_NUM_CHIP_BITS: 0
g_MEMORY_SIZE_BITS: 32
g_DATA_BLOCK_BITS: 6
g_PAGE_SIZE_BITS: 12
g_NUM_PROCESSORS_BITS: 0
g_PROCS_PER_CHIP_BITS: 0
g_NUM_L2_BANKS_BITS: 0
g_NUM_L2_BANKS_PER_CHIP_BITS: 0
g_NUM_L2_BANKS_PER_CHIP: 1
g_NUM_MEMORIES_BITS: 0
g_NUM_MEMORIES_PER_CHIP: 1
g_MEMORY_MODULE_BITS: 26
g_MEMORY_MODULE_BLOCKS: 67108864
MAP_L2BANKS_TO_LOWEST_BITS: false
DIRECTORY_CACHE_LATENCY: 6
NULL_LATENCY: 1
ISSUE_LATENCY: 2
CACHE_RESPONSE_LATENCY: 12
L2_RESPONSE_LATENCY: 6
L2_TAG_LATENCY: 6
L1_RESPONSE_LATENCY: 3
MEMORY_RESPONSE_LATENCY_MINUS_2: 158
DIRECTORY_LATENCY: 80
NETWORK_LINK_LATENCY: 1
COPY_HEAD_LATENCY: 4
ON_CHIP_LINK_LATENCY: 1
RECYCLE_LATENCY: 10
L2_RECYCLE_LATENCY: 5
TIMER_LATENCY: 10000
TBE_RESPONSE_LATENCY: 1
PERIODIC_TIMER_WAKEUPS: true
PROFILE_EXCEPTIONS: false
PROFILE_XACT: true
PROFILE_NONXACT: false
XACT_DEBUG: true
XACT_DEBUG_LEVEL: 1
XACT_MEMORY: false
XACT_ENABLE_TOURMALINE: false
XACT_NUM_CURRENT: 0
XACT_LAST_UPDATE: 0
XACT_ISOLATION_CHECK: false
PERFECT_FILTER: true
READ_WRITE_FILTER: Perfect_
PERFECT_VIRTUAL_FILTER: true
VIRTUAL_READ_WRITE_FILTER: Perfect_
PERFECT_SUMMARY_FILTER: true
SUMMARY_READ_WRITE_FILTER: Perfect_
XACT_EAGER_CD: true
XACT_LAZY_VM: false
XACT_CONFLICT_RES: BASE
XACT_VISUALIZER: false
XACT_COMMIT_TOKEN_LATENCY: 0
XACT_NO_BACKOFF: false
XACT_LOG_BUFFER_SIZE: 0
XACT_STORE_PREDICTOR_HISTORY: 256
XACT_STORE_PREDICTOR_ENTRIES: 256
XACT_STORE_PREDICTOR_THRESHOLD: 4
XACT_FIRST_ACCESS_COST: 0
XACT_FIRST_PAGE_ACCESS_COST: 0
ENABLE_MAGIC_WAITING: false
ENABLE_WATCHPOINT: false
XACT_ENABLE_VIRTUALIZATION_LOGTM_SE: false
ATMTP_ENABLED: false
ATMTP_ABORT_ON_NON_XACT_INST: false
ATMTP_ALLOW_SAVE_RESTORE_IN_XACT: false
ATMTP_XACT_MAX_STORES: 32
ATMTP_DEBUG_LEVEL: 0
L1_REQUEST_LATENCY: 2
L2_REQUEST_LATENCY: 4
SINGLE_ACCESS_L2_BANKS: true
SEQUENCER_TO_CONTROLLER_LATENCY: 4
L1CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
L2CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
DIRECTORY_TRANSITIONS_PER_RUBY_CYCLE: 32
g_SEQUENCER_OUTSTANDING_REQUESTS: 16
NUMBER_OF_TBES: 128
NUMBER_OF_L1_TBES: 32
NUMBER_OF_L2_TBES: 32
FINITE_BUFFERING: false
FINITE_BUFFER_SIZE: 3
PROCESSOR_BUFFER_SIZE: 10
PROTOCOL_BUFFER_SIZE: 32
TSO: false
g_NETWORK_TOPOLOGY: HIERARCHICAL_SWITCH
g_CACHE_DESIGN: NUCA
g_endpoint_bandwidth: 10000
g_adaptive_routing: true
NUMBER_OF_VIRTUAL_NETWORKS: 4
FAN_OUT_DEGREE: 4
g_PRINT_TOPOLOGY: true
XACT_LENGTH: 0
XACT_SIZE: 0
ABORT_RETRY_TIME: 0
g_GARNET_NETWORK: false
g_DETAIL_NETWORK: false
g_NETWORK_TESTING: false
g_FLIT_SIZE: 16
g_NUM_PIPE_STAGES: 4
g_VCS_PER_CLASS: 4
g_BUFFER_SIZE: 4
MEM_BUS_CYCLE_MULTIPLIER: 10
BANKS_PER_RANK: 8
RANKS_PER_DIMM: 2
DIMMS_PER_CHANNEL: 2
BANK_BIT_0: 8
RANK_BIT_0: 11
DIMM_BIT_0: 12
BANK_QUEUE_SIZE: 12
BANK_BUSY_TIME: 11
RANK_RANK_DELAY: 1
READ_WRITE_DELAY: 2
BASIC_BUS_BUSY_TIME: 2
MEM_CTL_LATENCY: 12
REFRESH_PERIOD: 1560
TFAW: 0
MEM_RANDOM_ARBITRATE: 0
MEM_FIXED_DELAY: 0
Chip Config
-----------
Total_Chips: 1
L1Cache_TBEs numberPerChip: 1
TBEs_per_TBETable: 128
L1Cache_L1IcacheMemory numberPerChip: 1
Cache config: L1Cache_0_L1I
cache_associativity: 4
num_cache_sets_bits: 8
num_cache_sets: 256
cache_set_size_bytes: 16384
cache_set_size_Kbytes: 16
cache_set_size_Mbytes: 0.015625
cache_size_bytes: 65536
cache_size_Kbytes: 64
cache_size_Mbytes: 0.0625
L1Cache_L1DcacheMemory numberPerChip: 1
Cache config: L1Cache_0_L1D
cache_associativity: 4
num_cache_sets_bits: 8
num_cache_sets: 256
cache_set_size_bytes: 16384
cache_set_size_Kbytes: 16
cache_set_size_Mbytes: 0.015625
cache_size_bytes: 65536
cache_size_Kbytes: 64
cache_size_Mbytes: 0.0625
L1Cache_L2cacheMemory numberPerChip: 1
Cache config: L1Cache_0_L2
cache_associativity: 4
num_cache_sets_bits: 16
num_cache_sets: 65536
cache_set_size_bytes: 4194304
cache_set_size_Kbytes: 4096
cache_set_size_Mbytes: 4
cache_size_bytes: 16777216
cache_size_Kbytes: 16384
cache_size_Mbytes: 16
L1Cache_mandatoryQueue numberPerChip: 1
L1Cache_sequencer numberPerChip: 1
sequencer: Sequencer - SC
RubySystem config:
random_seed: 952703
randomization: 0
tech_nm: 45
freq_mhz: 3000
block_size_bytes: 64
block_size_bits: 6
memory_size_bytes: 1073741824
memory_size_bits: 30
DMA_Controller config: DMAController_0
version: 0
buffer_size: 32
dma_sequencer: DMASequencer_0
number_of_TBEs: 128
transitions_per_cycle: 32
Directory_Controller config: DirectoryController_0
version: 0
buffer_size: 32
directory_latency: 6
directory_name: DirectoryMemory_0
memory_controller_name: MemoryControl_0
memory_latency: 158
number_of_TBEs: 128
recycle_latency: 10
to_mem_ctrl_latency: 1
transitions_per_cycle: 32
L1Cache_Controller config: L1CacheController_0
version: 0
buffer_size: 32
cache: l1u_0
cache_response_latency: 12
issue_latency: 2
number_of_TBEs: 128
sequencer: Sequencer_0
transitions_per_cycle: 32
Cache config: l1u_0
controller: L1CacheController_0
cache_associativity: 8
num_cache_sets_bits: 2
num_cache_sets: 4
cache_set_size_bytes: 256
cache_set_size_Kbytes: 0.25
cache_set_size_Mbytes: 0.000244141
cache_size_bytes: 2048
cache_size_Kbytes: 2
cache_size_Mbytes: 0.00195312
DirectoryMemory Global Config:
number of directory memories: 1
total memory size bytes: 1073741824
total memory size bits: 30
DirectoryMemory module config: DirectoryMemory_0
controller: DirectoryController_0
version: 0
memory_bits: 30
memory_size_bytes: 1073741824
memory_size_Kbytes: 1.04858e+06
memory_size_Mbytes: 1024
memory_size_Gbytes: 1
Seqeuncer config: Sequencer_0
controller: L1CacheController_0
version: 0
max_outstanding_requests: 16
L1Cache_storeBuffer numberPerChip: 1
Store buffer entries: 128 (Only valid if TSO is enabled)
Directory_directory numberPerChip: 1
Memory config:
memory_bits: 32
memory_size_bytes: 4294967296
memory_size_Kbytes: 4.1943e+06
memory_size_Mbytes: 4096
memory_size_Gbytes: 4
module_bits: 26
module_size_lines: 67108864
module_size_bytes: 4294967296
module_size_Kbytes: 4.1943e+06
module_size_Mbytes: 4096
deadlock_threshold: 500000
Network Configuration
---------------------
network: SIMPLE_NETWORK
topology: HIERARCHICAL_SWITCH
topology: theTopology
virtual_net_0: active, ordered
virtual_net_1: active, unordered
virtual_net_2: inactive
virtual_net_1: active, ordered
virtual_net_2: active, ordered
virtual_net_3: inactive
virtual_net_4: active, ordered
virtual_net_5: active, ordered
--- Begin Topology Print ---
@ -260,10 +83,16 @@ Topology print ONLY indicates the _NETWORK_ latency between two machines
It does NOT include the latency within the machines
L1Cache-0 Network Latencies
L1Cache-0 -> Directory-0 net_lat: 5
L1Cache-0 -> Directory-0 net_lat: 7
L1Cache-0 -> DMA-0 net_lat: 7
Directory-0 Network Latencies
Directory-0 -> L1Cache-0 net_lat: 5
Directory-0 -> L1Cache-0 net_lat: 7
Directory-0 -> DMA-0 net_lat: 7
DMA-0 Network Latencies
DMA-0 -> L1Cache-0 net_lat: 7
DMA-0 -> Directory-0 net_lat: 7
--- End Topology Print ---
@ -274,27 +103,27 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
Real time: May/05/2009 07:34:03
Real time: Jul/06/2009 11:11:07
Profiler Stats
--------------
Elapsed_time_in_seconds: 0
Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
Elapsed_time_in_seconds: 1
Elapsed_time_in_minutes: 0.0166667
Elapsed_time_in_hours: 0.000277778
Elapsed_time_in_days: 1.15741e-05
Virtual_time_in_seconds: 0.15
Virtual_time_in_minutes: 0.0025
Virtual_time_in_hours: 4.16667e-05
Virtual_time_in_days: 4.16667e-05
Virtual_time_in_seconds: 0.2
Virtual_time_in_minutes: 0.00333333
Virtual_time_in_hours: 5.55556e-05
Virtual_time_in_days: 5.55556e-05
Ruby_current_time: 3215001
Ruby_start_time: 1
Ruby_cycles: 3215000
mbytes_resident: 34.6523
mbytes_total: 195.43
resident_ratio: 0.177334
mbytes_resident: 144.742
mbytes_total: 1329.5
resident_ratio: 0.108872
Total_misses: 0
total_misses: 0 [ 0 ]
@ -302,7 +131,7 @@ user_misses: 0 [ 0 ]
supervisor_misses: 0 [ 0 ]
instruction_executed: 1 [ 1 ]
cycles_executed: 1 [ 1 ]
ruby_cycles_executed: 3215001 [ 3215001 ]
cycles_per_instruction: 3.215e+06 [ 3.215e+06 ]
misses_per_thousand_instructions: 0 [ 0 ]
@ -352,6 +181,7 @@ L2_cache cache stats:
Busy Controller Counts:
L1Cache-0:0
Directory-0:0
DMA-0:0
Busy Bank Count:0
@ -390,406 +220,163 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard dev
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Resource Usage
--------------
page_size: 4096
user_time: 0
system_time: 0
page_reclaims: 9071
page_reclaims: 37817
page_faults: 0
swaps: 0
block_inputs: 0
block_outputs: 56
MessageBuffer: [Chip 0 0, L1Cache, mandatoryQueue_in] stats - msgs:0 full:0
block_outputs: 40
Network Stats
-------------
switch_0_inlinks: 1
switch_0_outlinks: 1
switch_0_inlinks: 2
switch_0_outlinks: 2
links_utilized_percent_switch_0: 0
links_utilized_percent_switch_0_link_0: 0 bw: 10000 base_latency: 1
links_utilized_percent_switch_0_link_0: 0 bw: 640000 base_latency: 1
links_utilized_percent_switch_0_link_1: 0 bw: 160000 base_latency: 1
switch_1_inlinks: 1
switch_1_outlinks: 1
switch_1_inlinks: 2
switch_1_outlinks: 2
links_utilized_percent_switch_1: 0
links_utilized_percent_switch_1_link_0: 0 bw: 10000 base_latency: 1
links_utilized_percent_switch_1_link_0: 0 bw: 640000 base_latency: 1
links_utilized_percent_switch_1_link_1: 0 bw: 160000 base_latency: 1
switch_2_inlinks: 2
switch_2_outlinks: 2
links_utilized_percent_switch_2: 0
links_utilized_percent_switch_2_link_0: 0 bw: 10000 base_latency: 1
links_utilized_percent_switch_2_link_1: 0 bw: 10000 base_latency: 1
links_utilized_percent_switch_2_link_0: 0 bw: 640000 base_latency: 1
links_utilized_percent_switch_2_link_1: 0 bw: 160000 base_latency: 1
switch_3_inlinks: 3
switch_3_outlinks: 3
links_utilized_percent_switch_3: 0
links_utilized_percent_switch_3_link_0: 0 bw: 160000 base_latency: 1
links_utilized_percent_switch_3_link_1: 0 bw: 160000 base_latency: 1
links_utilized_percent_switch_3_link_2: 0 bw: 160000 base_latency: 1
Chip Stats
----------
--- DMA ---
- Event Counts -
ReadRequest 0
WriteRequest 0
Data 0
Ack 0
- Transitions -
READY ReadRequest 0 <--
READY WriteRequest 0 <--
BUSY_RD Data 0 <--
BUSY_WR Ack 0 <--
--- Directory ---
- Event Counts -
GETX 0
GETS 0
PUTX 0
PUTX_NotOwner 0
DMA_READ 0
DMA_WRITE 0
Memory_Data 0
Memory_Ack 0
- Transitions -
I GETX 0 <--
I PUTX_NotOwner 0 <--
I DMA_READ 0 <--
I DMA_WRITE 0 <--
M GETX 0 <--
M PUTX 0 <--
M PUTX_NotOwner 0 <--
M DMA_READ 0 <--
M DMA_WRITE 0 <--
M_DRD GETX 0 <--
M_DRD PUTX 0 <--
M_DWR GETX 0 <--
M_DWR PUTX 0 <--
M_DWRI Memory_Ack 0 <--
IM GETX 0 <--
IM GETS 0 <--
IM PUTX 0 <--
IM PUTX_NotOwner 0 <--
IM DMA_READ 0 <--
IM DMA_WRITE 0 <--
IM Memory_Data 0 <--
MI GETX 0 <--
MI GETS 0 <--
MI PUTX 0 <--
MI PUTX_NotOwner 0 <--
MI DMA_READ 0 <--
MI DMA_WRITE 0 <--
MI Memory_Ack 0 <--
ID GETX 0 <--
ID GETS 0 <--
ID PUTX 0 <--
ID PUTX_NotOwner 0 <--
ID DMA_READ 0 <--
ID DMA_WRITE 0 <--
ID Memory_Data 0 <--
ID_W GETX 0 <--
ID_W GETS 0 <--
ID_W PUTX 0 <--
ID_W PUTX_NotOwner 0 <--
ID_W DMA_READ 0 <--
ID_W DMA_WRITE 0 <--
ID_W Memory_Ack 0 <--
--- L1Cache ---
- Event Counts -
Load 0
Ifetch 0
Store 0
L1_to_L2 0
L2_to_L1D 0
L2_to_L1I 0
L2_Replacement 0
Own_GETS 0
Own_GET_INSTR 0
Own_GETX 0
Own_PUTX 0
Other_GETS 0
Other_GET_INSTR 0
Other_GETX 0
Other_PUTX 0
Data 0
Fwd_GETX 0
Inv 0
Replacement 0
Writeback_Ack 0
Writeback_Nack 0
- Transitions -
NP Load 0 <--
NP Ifetch 0 <--
NP Store 0 <--
NP Other_GETS 0 <--
NP Other_GET_INSTR 0 <--
NP Other_GETX 0 <--
NP Other_PUTX 0 <--
I Load 0 <--
I Ifetch 0 <--
I Store 0 <--
I L1_to_L2 0 <--
I L2_to_L1D 0 <--
I L2_to_L1I 0 <--
I L2_Replacement 0 <--
I Other_GETS 0 <--
I Other_GET_INSTR 0 <--
I Other_GETX 0 <--
I Other_PUTX 0 <--
I Inv 0 <--
I Replacement 0 <--
S Load 0 <--
S Ifetch 0 <--
S Store 0 <--
S L1_to_L2 0 <--
S L2_to_L1D 0 <--
S L2_to_L1I 0 <--
S L2_Replacement 0 <--
S Other_GETS 0 <--
S Other_GET_INSTR 0 <--
S Other_GETX 0 <--
S Other_PUTX 0 <--
O Load 0 <--
O Ifetch 0 <--
O Store 0 <--
O L1_to_L2 0 <--
O L2_to_L1D 0 <--
O L2_to_L1I 0 <--
O L2_Replacement 0 <--
O Other_GETS 0 <--
O Other_GET_INSTR 0 <--
O Other_GETX 0 <--
O Other_PUTX 0 <--
II Writeback_Nack 0 <--
M Load 0 <--
M Ifetch 0 <--
M Store 0 <--
M L1_to_L2 0 <--
M L2_to_L1D 0 <--
M L2_to_L1I 0 <--
M L2_Replacement 0 <--
M Other_GETS 0 <--
M Other_GET_INSTR 0 <--
M Other_GETX 0 <--
M Other_PUTX 0 <--
M Fwd_GETX 0 <--
M Inv 0 <--
M Replacement 0 <--
IS_AD Load 0 <--
IS_AD Ifetch 0 <--
IS_AD Store 0 <--
IS_AD L1_to_L2 0 <--
IS_AD L2_to_L1D 0 <--
IS_AD L2_to_L1I 0 <--
IS_AD L2_Replacement 0 <--
IS_AD Own_GETS 0 <--
IS_AD Own_GET_INSTR 0 <--
IS_AD Other_GETS 0 <--
IS_AD Other_GET_INSTR 0 <--
IS_AD Other_GETX 0 <--
IS_AD Other_PUTX 0 <--
IS_AD Data 0 <--
MI Fwd_GETX 0 <--
MI Inv 0 <--
MI Writeback_Ack 0 <--
IM_AD Load 0 <--
IM_AD Ifetch 0 <--
IM_AD Store 0 <--
IM_AD L1_to_L2 0 <--
IM_AD L2_to_L1D 0 <--
IM_AD L2_to_L1I 0 <--
IM_AD L2_Replacement 0 <--
IM_AD Own_GETX 0 <--
IM_AD Other_GETS 0 <--
IM_AD Other_GET_INSTR 0 <--
IM_AD Other_GETX 0 <--
IM_AD Other_PUTX 0 <--
IM_AD Data 0 <--
IS Data 0 <--
SM_AD Load 0 <--
SM_AD Ifetch 0 <--
SM_AD Store 0 <--
SM_AD L1_to_L2 0 <--
SM_AD L2_to_L1D 0 <--
SM_AD L2_to_L1I 0 <--
SM_AD L2_Replacement 0 <--
SM_AD Own_GETX 0 <--
SM_AD Other_GETS 0 <--
SM_AD Other_GET_INSTR 0 <--
SM_AD Other_GETX 0 <--
SM_AD Other_PUTX 0 <--
SM_AD Data 0 <--
OM_A Load 0 <--
OM_A Ifetch 0 <--
OM_A Store 0 <--
OM_A L1_to_L2 0 <--
OM_A L2_to_L1D 0 <--
OM_A L2_to_L1I 0 <--
OM_A L2_Replacement 0 <--
OM_A Own_GETX 0 <--
OM_A Other_GETS 0 <--
OM_A Other_GET_INSTR 0 <--
OM_A Other_GETX 0 <--
OM_A Other_PUTX 0 <--
OM_A Data 0 <--
IS_A Load 0 <--
IS_A Ifetch 0 <--
IS_A Store 0 <--
IS_A L1_to_L2 0 <--
IS_A L2_to_L1D 0 <--
IS_A L2_to_L1I 0 <--
IS_A L2_Replacement 0 <--
IS_A Own_GETS 0 <--
IS_A Own_GET_INSTR 0 <--
IS_A Other_GETS 0 <--
IS_A Other_GET_INSTR 0 <--
IS_A Other_GETX 0 <--
IS_A Other_PUTX 0 <--
IM_A Load 0 <--
IM_A Ifetch 0 <--
IM_A Store 0 <--
IM_A L1_to_L2 0 <--
IM_A L2_to_L1D 0 <--
IM_A L2_to_L1I 0 <--
IM_A L2_Replacement 0 <--
IM_A Own_GETX 0 <--
IM_A Other_GETS 0 <--
IM_A Other_GET_INSTR 0 <--
IM_A Other_GETX 0 <--
IM_A Other_PUTX 0 <--
SM_A Load 0 <--
SM_A Ifetch 0 <--
SM_A Store 0 <--
SM_A L1_to_L2 0 <--
SM_A L2_to_L1D 0 <--
SM_A L2_to_L1I 0 <--
SM_A L2_Replacement 0 <--
SM_A Own_GETX 0 <--
SM_A Other_GETS 0 <--
SM_A Other_GET_INSTR 0 <--
SM_A Other_GETX 0 <--
SM_A Other_PUTX 0 <--
MI_A Load 0 <--
MI_A Ifetch 0 <--
MI_A Store 0 <--
MI_A L1_to_L2 0 <--
MI_A L2_to_L1D 0 <--
MI_A L2_to_L1I 0 <--
MI_A L2_Replacement 0 <--
MI_A Own_PUTX 0 <--
MI_A Other_GETS 0 <--
MI_A Other_GET_INSTR 0 <--
MI_A Other_GETX 0 <--
MI_A Other_PUTX 0 <--
OI_A Load 0 <--
OI_A Ifetch 0 <--
OI_A Store 0 <--
OI_A L1_to_L2 0 <--
OI_A L2_to_L1D 0 <--
OI_A L2_to_L1I 0 <--
OI_A L2_Replacement 0 <--
OI_A Own_PUTX 0 <--
OI_A Other_GETS 0 <--
OI_A Other_GET_INSTR 0 <--
OI_A Other_GETX 0 <--
OI_A Other_PUTX 0 <--
II_A Load 0 <--
II_A Ifetch 0 <--
II_A Store 0 <--
II_A L1_to_L2 0 <--
II_A L2_to_L1D 0 <--
II_A L2_to_L1I 0 <--
II_A L2_Replacement 0 <--
II_A Own_PUTX 0 <--
II_A Other_GETS 0 <--
II_A Other_GET_INSTR 0 <--
II_A Other_GETX 0 <--
II_A Other_PUTX 0 <--
IS_D Load 0 <--
IS_D Ifetch 0 <--
IS_D Store 0 <--
IS_D L1_to_L2 0 <--
IS_D L2_to_L1D 0 <--
IS_D L2_to_L1I 0 <--
IS_D L2_Replacement 0 <--
IS_D Other_GETS 0 <--
IS_D Other_GET_INSTR 0 <--
IS_D Other_GETX 0 <--
IS_D Other_PUTX 0 <--
IS_D Data 0 <--
IS_D_I Load 0 <--
IS_D_I Ifetch 0 <--
IS_D_I Store 0 <--
IS_D_I L1_to_L2 0 <--
IS_D_I L2_to_L1D 0 <--
IS_D_I L2_to_L1I 0 <--
IS_D_I L2_Replacement 0 <--
IS_D_I Other_GETS 0 <--
IS_D_I Other_GET_INSTR 0 <--
IS_D_I Other_GETX 0 <--
IS_D_I Other_PUTX 0 <--
IS_D_I Data 0 <--
IM_D Load 0 <--
IM_D Ifetch 0 <--
IM_D Store 0 <--
IM_D L1_to_L2 0 <--
IM_D L2_to_L1D 0 <--
IM_D L2_to_L1I 0 <--
IM_D L2_Replacement 0 <--
IM_D Other_GETS 0 <--
IM_D Other_GET_INSTR 0 <--
IM_D Other_GETX 0 <--
IM_D Other_PUTX 0 <--
IM_D Data 0 <--
IM_D_O Load 0 <--
IM_D_O Ifetch 0 <--
IM_D_O Store 0 <--
IM_D_O L1_to_L2 0 <--
IM_D_O L2_to_L1D 0 <--
IM_D_O L2_to_L1I 0 <--
IM_D_O L2_Replacement 0 <--
IM_D_O Other_GETS 0 <--
IM_D_O Other_GET_INSTR 0 <--
IM_D_O Other_GETX 0 <--
IM_D_O Other_PUTX 0 <--
IM_D_O Data 0 <--
IM_D_I Load 0 <--
IM_D_I Ifetch 0 <--
IM_D_I Store 0 <--
IM_D_I L1_to_L2 0 <--
IM_D_I L2_to_L1D 0 <--
IM_D_I L2_to_L1I 0 <--
IM_D_I L2_Replacement 0 <--
IM_D_I Other_GETS 0 <--
IM_D_I Other_GET_INSTR 0 <--
IM_D_I Other_GETX 0 <--
IM_D_I Other_PUTX 0 <--
IM_D_I Data 0 <--
IM_D_OI Load 0 <--
IM_D_OI Ifetch 0 <--
IM_D_OI Store 0 <--
IM_D_OI L1_to_L2 0 <--
IM_D_OI L2_to_L1D 0 <--
IM_D_OI L2_to_L1I 0 <--
IM_D_OI L2_Replacement 0 <--
IM_D_OI Other_GETS 0 <--
IM_D_OI Other_GET_INSTR 0 <--
IM_D_OI Other_GETX 0 <--
IM_D_OI Other_PUTX 0 <--
IM_D_OI Data 0 <--
SM_D Load 0 <--
SM_D Ifetch 0 <--
SM_D Store 0 <--
SM_D L1_to_L2 0 <--
SM_D L2_to_L1D 0 <--
SM_D L2_to_L1I 0 <--
SM_D L2_Replacement 0 <--
SM_D Other_GETS 0 <--
SM_D Other_GET_INSTR 0 <--
SM_D Other_GETX 0 <--
SM_D Other_PUTX 0 <--
SM_D Data 0 <--
SM_D_O Load 0 <--
SM_D_O Ifetch 0 <--
SM_D_O Store 0 <--
SM_D_O L1_to_L2 0 <--
SM_D_O L2_to_L1D 0 <--
SM_D_O L2_to_L1I 0 <--
SM_D_O L2_Replacement 0 <--
SM_D_O Other_GETS 0 <--
SM_D_O Other_GET_INSTR 0 <--
SM_D_O Other_GETX 0 <--
SM_D_O Other_PUTX 0 <--
SM_D_O Data 0 <--
--- Directory ---
- Event Counts -
OtherAddress 0
GETS 0
GET_INSTR 0
GETX 0
PUTX_Owner 0
PUTX_NotOwner 0
- Transitions -
C OtherAddress 0 <--
C GETS 0 <--
C GET_INSTR 0 <--
C GETX 0 <--
I GETS 0 <--
I GET_INSTR 0 <--
I GETX 0 <--
I PUTX_NotOwner 0 <--
S GETS 0 <--
S GET_INSTR 0 <--
S GETX 0 <--
S PUTX_NotOwner 0 <--
SS GETS 0 <--
SS GET_INSTR 0 <--
SS GETX 0 <--
SS PUTX_NotOwner 0 <--
OS GETS 0 <--
OS GET_INSTR 0 <--
OS GETX 0 <--
OS PUTX_Owner 0 <--
OS PUTX_NotOwner 0 <--
OSS GETS 0 <--
OSS GET_INSTR 0 <--
OSS GETX 0 <--
OSS PUTX_Owner 0 <--
OSS PUTX_NotOwner 0 <--
M GETS 0 <--
M GET_INSTR 0 <--
M GETX 0 <--
M PUTX_Owner 0 <--
M PUTX_NotOwner 0 <--
IM Data 0 <--

20
tests/quick/00.hello/ref/alpha/linux/simple-atomic-ruby/simerr
View file

@ -1,3 +1,23 @@
["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024"]
print config: 1
Creating new MessageBuffer for 0 0
Creating new MessageBuffer for 0 1
Creating new MessageBuffer for 0 2
Creating new MessageBuffer for 0 3
Creating new MessageBuffer for 0 4
Creating new MessageBuffer for 0 5
Creating new MessageBuffer for 1 0
Creating new MessageBuffer for 1 1
Creating new MessageBuffer for 1 2
Creating new MessageBuffer for 1 3
Creating new MessageBuffer for 1 4
Creating new MessageBuffer for 1 5
Creating new MessageBuffer for 2 0
Creating new MessageBuffer for 2 1
Creating new MessageBuffer for 2 2
Creating new MessageBuffer for 2 3
Creating new MessageBuffer for 2 4
Creating new MessageBuffer for 2 5
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here

18
tests/quick/00.hello/ref/alpha/linux/simple-atomic-ruby/simout
View file

@ -5,19 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 5 2009 07:34:00
M5 revision 8bea207e2193 6172 default qtip tip ruby_tests_refs.diff
M5 started May 5 2009 07:34:03
M5 executing on piton
command line: /n/piton/z/nate/build/xgem5/build/ALPHA_SE/m5.fast -d /n/piton/z/nate/build/xgem5/build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic-ruby -re tests/run.py /n/piton/z/nate/build/xgem5/build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic-ruby
M5 compiled Jul 6 2009 11:03:45
M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
M5 started Jul 6 2009 11:11:06
M5 executing on maize
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic-ruby
Global frequency set at 1000000000000 ticks per second
Ruby Timing Mode
Creating event queue...
Creating event queue done
Creating system...
Processors: 1
Creating system done
Ruby initialization complete
Debug: Adding to filter: 'q' (Queue)
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!

8
tests/quick/00.hello/ref/alpha/linux/simple-atomic-ruby/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 94038 # Simulator instruction rate (inst/s)
host_mem_usage 200124 # Number of bytes of host memory used
host_seconds 0.07 # Real time elapsed on the host
host_tick_rate 47099326 # Simulator tick rate (ticks/s)
host_inst_rate 105206 # Simulator instruction rate (inst/s)
host_mem_usage 1361416 # Number of bytes of host memory used
host_seconds 0.06 # Real time elapsed on the host
host_tick_rate 52654853 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 6404 # Number of instructions simulated
sim_seconds 0.000003 # Number of seconds simulated

5
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
View file

@ -78,10 +78,9 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=RubyMemory
clock=1
config_file=
config_options=
config_file=build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby/ruby.config
debug=false
debug_file=
debug_file=ruby.debug
file=
latency=30000
latency_var=0

954
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
View file

File diff suppressed because it is too large Load diff

20
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simerr
View file

@ -1,3 +1,23 @@
["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024"]
print config: 1
Creating new MessageBuffer for 0 0
Creating new MessageBuffer for 0 1
Creating new MessageBuffer for 0 2
Creating new MessageBuffer for 0 3
Creating new MessageBuffer for 0 4
Creating new MessageBuffer for 0 5
Creating new MessageBuffer for 1 0
Creating new MessageBuffer for 1 1
Creating new MessageBuffer for 1 2
Creating new MessageBuffer for 1 3
Creating new MessageBuffer for 1 4
Creating new MessageBuffer for 1 5
Creating new MessageBuffer for 2 0
Creating new MessageBuffer for 2 1
Creating new MessageBuffer for 2 2
Creating new MessageBuffer for 2 3
Creating new MessageBuffer for 2 4
Creating new MessageBuffer for 2 5
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here

18
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout
View file

@ -5,19 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 5 2009 07:34:00
M5 revision 8bea207e2193 6172 default qtip tip ruby_tests_refs.diff
M5 started May 5 2009 07:34:03
M5 executing on piton
command line: /n/piton/z/nate/build/xgem5/build/ALPHA_SE/m5.fast -d /n/piton/z/nate/build/xgem5/build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py /n/piton/z/nate/build/xgem5/build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby
M5 compiled Jul 6 2009 11:03:45
M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
M5 started Jul 6 2009 11:11:07
M5 executing on maize
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby
Global frequency set at 1000000000000 ticks per second
Ruby Timing Mode
Creating event queue...
Creating event queue done
Creating system...
Processors: 1
Creating system done
Ruby initialization complete
Debug: Adding to filter: 'q' (Queue)
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!

8
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 9868 # Simulator instruction rate (inst/s)
host_mem_usage 200140 # Number of bytes of host memory used
host_seconds 0.65 # Real time elapsed on the host
host_tick_rate 39112264 # Simulator tick rate (ticks/s)
host_inst_rate 8064 # Simulator instruction rate (inst/s)
host_mem_usage 1361592 # Number of bytes of host memory used
host_seconds 0.79 # Real time elapsed on the host
host_tick_rate 31966299 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 6404 # Number of instructions simulated
sim_seconds 0.000025 # Number of seconds simulated

5
tests/quick/00.hello/ref/alpha/tru64/simple-atomic-ruby/config.ini
View file

@ -81,10 +81,9 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=RubyMemory
clock=1
config_file=
config_options=
config_file=build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic-ruby/ruby.config
debug=false
debug_file=
debug_file=ruby.debug
file=
latency=30000
latency_var=0

813
tests/quick/00.hello/ref/alpha/tru64/simple-atomic-ruby/ruby.stats
View file

@ -1,258 +1,81 @@
================ Begin RubySystem Configuration Print ================
Ruby Configuration
------------------
protocol: MOSI_SMP_bcast
compiled_at: 22:51:11, May 4 2009
RUBY_DEBUG: false
hostname: piton
g_RANDOM_SEED: 1
g_DEADLOCK_THRESHOLD: 500000
RANDOMIZATION: false
g_SYNTHETIC_DRIVER: false
g_DETERMINISTIC_DRIVER: false
g_FILTERING_ENABLED: false
g_DISTRIBUTED_PERSISTENT_ENABLED: true
g_DYNAMIC_TIMEOUT_ENABLED: true
g_RETRY_THRESHOLD: 1
g_FIXED_TIMEOUT_LATENCY: 300
g_trace_warmup_length: 1000000
g_bash_bandwidth_adaptive_threshold: 0.75
g_tester_length: 0
g_synthetic_locks: 2048
g_deterministic_addrs: 1
g_SpecifiedGenerator: DetermInvGenerator
g_callback_counter: 0
g_NUM_COMPLETIONS_BEFORE_PASS: 0
g_NUM_SMT_THREADS: 1
g_think_time: 5
g_hold_time: 5
g_wait_time: 5
PROTOCOL_DEBUG_TRACE: true
DEBUG_FILTER_STRING: none
DEBUG_VERBOSITY_STRING: none
DEBUG_START_TIME: 0
DEBUG_OUTPUT_FILENAME: none
SIMICS_RUBY_MULTIPLIER: 4
OPAL_RUBY_MULTIPLIER: 1
TRANSACTION_TRACE_ENABLED: false
USER_MODE_DATA_ONLY: false
PROFILE_HOT_LINES: false
PROFILE_ALL_INSTRUCTIONS: false
PRINT_INSTRUCTION_TRACE: false
g_DEBUG_CYCLE: 0
BLOCK_STC: false
PERFECT_MEMORY_SYSTEM: false
PERFECT_MEMORY_SYSTEM_LATENCY: 0
DATA_BLOCK: false
REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH: false
L1_CACHE_ASSOC: 4
L1_CACHE_NUM_SETS_BITS: 8
L2_CACHE_ASSOC: 4
L2_CACHE_NUM_SETS_BITS: 16
g_MEMORY_SIZE_BYTES: 4294967296
g_DATA_BLOCK_BYTES: 64
g_PAGE_SIZE_BYTES: 4096
g_REPLACEMENT_POLICY: PSEDUO_LRU
g_NUM_PROCESSORS: 1
g_NUM_L2_BANKS: 1
g_NUM_MEMORIES: 1
g_PROCS_PER_CHIP: 1
g_NUM_CHIPS: 1
g_NUM_CHIP_BITS: 0
g_MEMORY_SIZE_BITS: 32
g_DATA_BLOCK_BITS: 6
g_PAGE_SIZE_BITS: 12
g_NUM_PROCESSORS_BITS: 0
g_PROCS_PER_CHIP_BITS: 0
g_NUM_L2_BANKS_BITS: 0
g_NUM_L2_BANKS_PER_CHIP_BITS: 0
g_NUM_L2_BANKS_PER_CHIP: 1
g_NUM_MEMORIES_BITS: 0
g_NUM_MEMORIES_PER_CHIP: 1
g_MEMORY_MODULE_BITS: 26
g_MEMORY_MODULE_BLOCKS: 67108864
MAP_L2BANKS_TO_LOWEST_BITS: false
DIRECTORY_CACHE_LATENCY: 6
NULL_LATENCY: 1
ISSUE_LATENCY: 2
CACHE_RESPONSE_LATENCY: 12
L2_RESPONSE_LATENCY: 6
L2_TAG_LATENCY: 6
L1_RESPONSE_LATENCY: 3
MEMORY_RESPONSE_LATENCY_MINUS_2: 158
DIRECTORY_LATENCY: 80
NETWORK_LINK_LATENCY: 1
COPY_HEAD_LATENCY: 4
ON_CHIP_LINK_LATENCY: 1
RECYCLE_LATENCY: 10
L2_RECYCLE_LATENCY: 5
TIMER_LATENCY: 10000
TBE_RESPONSE_LATENCY: 1
PERIODIC_TIMER_WAKEUPS: true
PROFILE_EXCEPTIONS: false
PROFILE_XACT: true
PROFILE_NONXACT: false
XACT_DEBUG: true
XACT_DEBUG_LEVEL: 1
XACT_MEMORY: false
XACT_ENABLE_TOURMALINE: false
XACT_NUM_CURRENT: 0
XACT_LAST_UPDATE: 0
XACT_ISOLATION_CHECK: false
PERFECT_FILTER: true
READ_WRITE_FILTER: Perfect_
PERFECT_VIRTUAL_FILTER: true
VIRTUAL_READ_WRITE_FILTER: Perfect_
PERFECT_SUMMARY_FILTER: true
SUMMARY_READ_WRITE_FILTER: Perfect_
XACT_EAGER_CD: true
XACT_LAZY_VM: false
XACT_CONFLICT_RES: BASE
XACT_VISUALIZER: false
XACT_COMMIT_TOKEN_LATENCY: 0
XACT_NO_BACKOFF: false
XACT_LOG_BUFFER_SIZE: 0
XACT_STORE_PREDICTOR_HISTORY: 256
XACT_STORE_PREDICTOR_ENTRIES: 256
XACT_STORE_PREDICTOR_THRESHOLD: 4
XACT_FIRST_ACCESS_COST: 0
XACT_FIRST_PAGE_ACCESS_COST: 0
ENABLE_MAGIC_WAITING: false
ENABLE_WATCHPOINT: false
XACT_ENABLE_VIRTUALIZATION_LOGTM_SE: false
ATMTP_ENABLED: false
ATMTP_ABORT_ON_NON_XACT_INST: false
ATMTP_ALLOW_SAVE_RESTORE_IN_XACT: false
ATMTP_XACT_MAX_STORES: 32
ATMTP_DEBUG_LEVEL: 0
L1_REQUEST_LATENCY: 2
L2_REQUEST_LATENCY: 4
SINGLE_ACCESS_L2_BANKS: true
SEQUENCER_TO_CONTROLLER_LATENCY: 4
L1CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
L2CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
DIRECTORY_TRANSITIONS_PER_RUBY_CYCLE: 32
g_SEQUENCER_OUTSTANDING_REQUESTS: 16
NUMBER_OF_TBES: 128
NUMBER_OF_L1_TBES: 32
NUMBER_OF_L2_TBES: 32
FINITE_BUFFERING: false
FINITE_BUFFER_SIZE: 3
PROCESSOR_BUFFER_SIZE: 10
PROTOCOL_BUFFER_SIZE: 32
TSO: false
g_NETWORK_TOPOLOGY: HIERARCHICAL_SWITCH
g_CACHE_DESIGN: NUCA
g_endpoint_bandwidth: 10000
g_adaptive_routing: true
NUMBER_OF_VIRTUAL_NETWORKS: 4
FAN_OUT_DEGREE: 4
g_PRINT_TOPOLOGY: true
XACT_LENGTH: 0
XACT_SIZE: 0
ABORT_RETRY_TIME: 0
g_GARNET_NETWORK: false
g_DETAIL_NETWORK: false
g_NETWORK_TESTING: false
g_FLIT_SIZE: 16
g_NUM_PIPE_STAGES: 4
g_VCS_PER_CLASS: 4
g_BUFFER_SIZE: 4
MEM_BUS_CYCLE_MULTIPLIER: 10
BANKS_PER_RANK: 8
RANKS_PER_DIMM: 2
DIMMS_PER_CHANNEL: 2
BANK_BIT_0: 8
RANK_BIT_0: 11
DIMM_BIT_0: 12
BANK_QUEUE_SIZE: 12
BANK_BUSY_TIME: 11
RANK_RANK_DELAY: 1
READ_WRITE_DELAY: 2
BASIC_BUS_BUSY_TIME: 2
MEM_CTL_LATENCY: 12
REFRESH_PERIOD: 1560
TFAW: 0
MEM_RANDOM_ARBITRATE: 0
MEM_FIXED_DELAY: 0
Chip Config
-----------
Total_Chips: 1
L1Cache_TBEs numberPerChip: 1
TBEs_per_TBETable: 128
L1Cache_L1IcacheMemory numberPerChip: 1
Cache config: L1Cache_0_L1I
cache_associativity: 4
num_cache_sets_bits: 8
num_cache_sets: 256
cache_set_size_bytes: 16384
cache_set_size_Kbytes: 16
cache_set_size_Mbytes: 0.015625
cache_size_bytes: 65536
cache_size_Kbytes: 64
cache_size_Mbytes: 0.0625
L1Cache_L1DcacheMemory numberPerChip: 1
Cache config: L1Cache_0_L1D
cache_associativity: 4
num_cache_sets_bits: 8
num_cache_sets: 256
cache_set_size_bytes: 16384
cache_set_size_Kbytes: 16
cache_set_size_Mbytes: 0.015625
cache_size_bytes: 65536
cache_size_Kbytes: 64
cache_size_Mbytes: 0.0625
L1Cache_L2cacheMemory numberPerChip: 1
Cache config: L1Cache_0_L2
cache_associativity: 4
num_cache_sets_bits: 16
num_cache_sets: 65536
cache_set_size_bytes: 4194304
cache_set_size_Kbytes: 4096
cache_set_size_Mbytes: 4
cache_size_bytes: 16777216
cache_size_Kbytes: 16384
cache_size_Mbytes: 16
L1Cache_mandatoryQueue numberPerChip: 1
L1Cache_sequencer numberPerChip: 1
sequencer: Sequencer - SC
RubySystem config:
random_seed: 613394
randomization: 0
tech_nm: 45
freq_mhz: 3000
block_size_bytes: 64
block_size_bits: 6
memory_size_bytes: 1073741824
memory_size_bits: 30
DMA_Controller config: DMAController_0
version: 0
buffer_size: 32
dma_sequencer: DMASequencer_0
number_of_TBEs: 128
transitions_per_cycle: 32
Directory_Controller config: DirectoryController_0
version: 0
buffer_size: 32
directory_latency: 6
directory_name: DirectoryMemory_0
memory_controller_name: MemoryControl_0
memory_latency: 158
number_of_TBEs: 128
recycle_latency: 10
to_mem_ctrl_latency: 1
transitions_per_cycle: 32
L1Cache_Controller config: L1CacheController_0
version: 0
buffer_size: 32
cache: l1u_0
cache_response_latency: 12
issue_latency: 2
number_of_TBEs: 128
sequencer: Sequencer_0
transitions_per_cycle: 32
Cache config: l1u_0
controller: L1CacheController_0
cache_associativity: 8
num_cache_sets_bits: 2
num_cache_sets: 4
cache_set_size_bytes: 256
cache_set_size_Kbytes: 0.25
cache_set_size_Mbytes: 0.000244141
cache_size_bytes: 2048
cache_size_Kbytes: 2
cache_size_Mbytes: 0.00195312
DirectoryMemory Global Config:
number of directory memories: 1
total memory size bytes: 1073741824
total memory size bits: 30
DirectoryMemory module config: DirectoryMemory_0
controller: DirectoryController_0
version: 0
memory_bits: 30
memory_size_bytes: 1073741824
memory_size_Kbytes: 1.04858e+06
memory_size_Mbytes: 1024
memory_size_Gbytes: 1
Seqeuncer config: Sequencer_0
controller: L1CacheController_0
version: 0
max_outstanding_requests: 16
L1Cache_storeBuffer numberPerChip: 1
Store buffer entries: 128 (Only valid if TSO is enabled)
Directory_directory numberPerChip: 1
Memory config:
memory_bits: 32
memory_size_bytes: 4294967296
memory_size_Kbytes: 4.1943e+06
memory_size_Mbytes: 4096
memory_size_Gbytes: 4
module_bits: 26
module_size_lines: 67108864
module_size_bytes: 4294967296
module_size_Kbytes: 4.1943e+06
module_size_Mbytes: 4096
deadlock_threshold: 500000
Network Configuration
---------------------
network: SIMPLE_NETWORK
topology: HIERARCHICAL_SWITCH
topology: theTopology
virtual_net_0: active, ordered
virtual_net_1: active, unordered
virtual_net_2: inactive
virtual_net_1: active, ordered
virtual_net_2: active, ordered
virtual_net_3: inactive
virtual_net_4: active, ordered
virtual_net_5: active, ordered
--- Begin Topology Print ---
@ -260,10 +83,16 @@ Topology print ONLY indicates the _NETWORK_ latency between two machines
It does NOT include the latency within the machines
L1Cache-0 Network Latencies
L1Cache-0 -> Directory-0 net_lat: 5
L1Cache-0 -> Directory-0 net_lat: 7
L1Cache-0 -> DMA-0 net_lat: 7
Directory-0 Network Latencies
Directory-0 -> L1Cache-0 net_lat: 5
Directory-0 -> L1Cache-0 net_lat: 7
Directory-0 -> DMA-0 net_lat: 7
DMA-0 Network Latencies
DMA-0 -> L1Cache-0 net_lat: 7
DMA-0 -> Directory-0 net_lat: 7
--- End Topology Print ---
@ -274,7 +103,7 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
Real time: May/05/2009 07:34:03
Real time: Jul/06/2009 11:11:05
Profiler Stats
--------------
@ -283,18 +112,18 @@ Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
Virtual_time_in_seconds: 0.13
Virtual_time_in_minutes: 0.00216667
Virtual_time_in_hours: 3.61111e-05
Virtual_time_in_days: 3.61111e-05
Virtual_time_in_seconds: 0.21
Virtual_time_in_minutes: 0.0035
Virtual_time_in_hours: 5.83333e-05
Virtual_time_in_days: 5.83333e-05
Ruby_current_time: 1297501
Ruby_start_time: 1
Ruby_cycles: 1297500
mbytes_resident: 33.3828
mbytes_total: 194.5
resident_ratio: 0.171654
mbytes_resident: 143.516
mbytes_total: 1328.64
resident_ratio: 0.10802
Total_misses: 0
total_misses: 0 [ 0 ]
@ -302,7 +131,7 @@ user_misses: 0 [ 0 ]
supervisor_misses: 0 [ 0 ]
instruction_executed: 1 [ 1 ]
cycles_executed: 1 [ 1 ]
ruby_cycles_executed: 1297501 [ 1297501 ]
cycles_per_instruction: 1.2975e+06 [ 1.2975e+06 ]
misses_per_thousand_instructions: 0 [ 0 ]
@ -352,6 +181,7 @@ L2_cache cache stats:
Busy Controller Counts:
L1Cache-0:0
Directory-0:0
DMA-0:0
Busy Bank Count:0
@ -390,406 +220,163 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard dev
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Resource Usage
--------------
page_size: 4096
user_time: 0
system_time: 0
page_reclaims: 8746
page_reclaims: 37503
page_faults: 0
swaps: 0
block_inputs: 0
block_outputs: 56
MessageBuffer: [Chip 0 0, L1Cache, mandatoryQueue_in] stats - msgs:0 full:0
block_inputs: 24
block_outputs: 48
Network Stats
-------------
switch_0_inlinks: 1
switch_0_outlinks: 1
switch_0_inlinks: 2
switch_0_outlinks: 2
links_utilized_percent_switch_0: 0
links_utilized_percent_switch_0_link_0: 0 bw: 10000 base_latency: 1
links_utilized_percent_switch_0_link_0: 0 bw: 640000 base_latency: 1
links_utilized_percent_switch_0_link_1: 0 bw: 160000 base_latency: 1
switch_1_inlinks: 1
switch_1_outlinks: 1
switch_1_inlinks: 2
switch_1_outlinks: 2
links_utilized_percent_switch_1: 0
links_utilized_percent_switch_1_link_0: 0 bw: 10000 base_latency: 1
links_utilized_percent_switch_1_link_0: 0 bw: 640000 base_latency: 1
links_utilized_percent_switch_1_link_1: 0 bw: 160000 base_latency: 1
switch_2_inlinks: 2
switch_2_outlinks: 2
links_utilized_percent_switch_2: 0
links_utilized_percent_switch_2_link_0: 0 bw: 10000 base_latency: 1
links_utilized_percent_switch_2_link_1: 0 bw: 10000 base_latency: 1
links_utilized_percent_switch_2_link_0: 0 bw: 640000 base_latency: 1
links_utilized_percent_switch_2_link_1: 0 bw: 160000 base_latency: 1
switch_3_inlinks: 3
switch_3_outlinks: 3
links_utilized_percent_switch_3: 0
links_utilized_percent_switch_3_link_0: 0 bw: 160000 base_latency: 1
links_utilized_percent_switch_3_link_1: 0 bw: 160000 base_latency: 1
links_utilized_percent_switch_3_link_2: 0 bw: 160000 base_latency: 1
Chip Stats
----------
--- DMA ---
- Event Counts -
ReadRequest 0
WriteRequest 0
Data 0
Ack 0
- Transitions -
READY ReadRequest 0 <--
READY WriteRequest 0 <--
BUSY_RD Data 0 <--
BUSY_WR Ack 0 <--
--- Directory ---
- Event Counts -
GETX 0
GETS 0
PUTX 0
PUTX_NotOwner 0
DMA_READ 0
DMA_WRITE 0
Memory_Data 0
Memory_Ack 0
- Transitions -
I GETX 0 <--
I PUTX_NotOwner 0 <--
I DMA_READ 0 <--
I DMA_WRITE 0 <--
M GETX 0 <--
M PUTX 0 <--
M PUTX_NotOwner 0 <--
M DMA_READ 0 <--
M DMA_WRITE 0 <--
M_DRD GETX 0 <--
M_DRD PUTX 0 <--
M_DWR GETX 0 <--
M_DWR PUTX 0 <--
M_DWRI Memory_Ack 0 <--
IM GETX 0 <--
IM GETS 0 <--
IM PUTX 0 <--
IM PUTX_NotOwner 0 <--
IM DMA_READ 0 <--
IM DMA_WRITE 0 <--
IM Memory_Data 0 <--
MI GETX 0 <--
MI GETS 0 <--
MI PUTX 0 <--
MI PUTX_NotOwner 0 <--
MI DMA_READ 0 <--
MI DMA_WRITE 0 <--
MI Memory_Ack 0 <--
ID GETX 0 <--
ID GETS 0 <--
ID PUTX 0 <--
ID PUTX_NotOwner 0 <--
ID DMA_READ 0 <--
ID DMA_WRITE 0 <--
ID Memory_Data 0 <--
ID_W GETX 0 <--
ID_W GETS 0 <--
ID_W PUTX 0 <--
ID_W PUTX_NotOwner 0 <--
ID_W DMA_READ 0 <--
ID_W DMA_WRITE 0 <--
ID_W Memory_Ack 0 <--
--- L1Cache ---
- Event Counts -
Load 0
Ifetch 0
Store 0
L1_to_L2 0
L2_to_L1D 0
L2_to_L1I 0
L2_Replacement 0
Own_GETS 0
Own_GET_INSTR 0
Own_GETX 0
Own_PUTX 0
Other_GETS 0
Other_GET_INSTR 0
Other_GETX 0
Other_PUTX 0
Data 0
Fwd_GETX 0
Inv 0
Replacement 0
Writeback_Ack 0
Writeback_Nack 0
- Transitions -
NP Load 0 <--
NP Ifetch 0 <--
NP Store 0 <--
NP Other_GETS 0 <--
NP Other_GET_INSTR 0 <--
NP Other_GETX 0 <--
NP Other_PUTX 0 <--
I Load 0 <--
I Ifetch 0 <--
I Store 0 <--
I L1_to_L2 0 <--
I L2_to_L1D 0 <--
I L2_to_L1I 0 <--
I L2_Replacement 0 <--
I Other_GETS 0 <--
I Other_GET_INSTR 0 <--
I Other_GETX 0 <--
I Other_PUTX 0 <--
I Inv 0 <--
I Replacement 0 <--
S Load 0 <--
S Ifetch 0 <--
S Store 0 <--
S L1_to_L2 0 <--
S L2_to_L1D 0 <--
S L2_to_L1I 0 <--
S L2_Replacement 0 <--
S Other_GETS 0 <--
S Other_GET_INSTR 0 <--
S Other_GETX 0 <--
S Other_PUTX 0 <--
O Load 0 <--
O Ifetch 0 <--
O Store 0 <--
O L1_to_L2 0 <--
O L2_to_L1D 0 <--
O L2_to_L1I 0 <--
O L2_Replacement 0 <--
O Other_GETS 0 <--
O Other_GET_INSTR 0 <--
O Other_GETX 0 <--
O Other_PUTX 0 <--
II Writeback_Nack 0 <--
M Load 0 <--
M Ifetch 0 <--
M Store 0 <--
M L1_to_L2 0 <--
M L2_to_L1D 0 <--
M L2_to_L1I 0 <--
M L2_Replacement 0 <--
M Other_GETS 0 <--
M Other_GET_INSTR 0 <--
M Other_GETX 0 <--
M Other_PUTX 0 <--
M Fwd_GETX 0 <--
M Inv 0 <--
M Replacement 0 <--
IS_AD Load 0 <--
IS_AD Ifetch 0 <--
IS_AD Store 0 <--
IS_AD L1_to_L2 0 <--
IS_AD L2_to_L1D 0 <--
IS_AD L2_to_L1I 0 <--
IS_AD L2_Replacement 0 <--
IS_AD Own_GETS 0 <--
IS_AD Own_GET_INSTR 0 <--
IS_AD Other_GETS 0 <--
IS_AD Other_GET_INSTR 0 <--
IS_AD Other_GETX 0 <--
IS_AD Other_PUTX 0 <--
IS_AD Data 0 <--
MI Fwd_GETX 0 <--
MI Inv 0 <--
MI Writeback_Ack 0 <--
IM_AD Load 0 <--
IM_AD Ifetch 0 <--
IM_AD Store 0 <--
IM_AD L1_to_L2 0 <--
IM_AD L2_to_L1D 0 <--
IM_AD L2_to_L1I 0 <--
IM_AD L2_Replacement 0 <--
IM_AD Own_GETX 0 <--
IM_AD Other_GETS 0 <--
IM_AD Other_GET_INSTR 0 <--
IM_AD Other_GETX 0 <--
IM_AD Other_PUTX 0 <--
IM_AD Data 0 <--
IS Data 0 <--
SM_AD Load 0 <--
SM_AD Ifetch 0 <--
SM_AD Store 0 <--
SM_AD L1_to_L2 0 <--
SM_AD L2_to_L1D 0 <--
SM_AD L2_to_L1I 0 <--
SM_AD L2_Replacement 0 <--
SM_AD Own_GETX 0 <--
SM_AD Other_GETS 0 <--
SM_AD Other_GET_INSTR 0 <--
SM_AD Other_GETX 0 <--
SM_AD Other_PUTX 0 <--
SM_AD Data 0 <--
OM_A Load 0 <--
OM_A Ifetch 0 <--
OM_A Store 0 <--
OM_A L1_to_L2 0 <--
OM_A L2_to_L1D 0 <--
OM_A L2_to_L1I 0 <--
OM_A L2_Replacement 0 <--
OM_A Own_GETX 0 <--
OM_A Other_GETS 0 <--
OM_A Other_GET_INSTR 0 <--
OM_A Other_GETX 0 <--
OM_A Other_PUTX 0 <--
OM_A Data 0 <--
IS_A Load 0 <--
IS_A Ifetch 0 <--
IS_A Store 0 <--
IS_A L1_to_L2 0 <--
IS_A L2_to_L1D 0 <--
IS_A L2_to_L1I 0 <--
IS_A L2_Replacement 0 <--
IS_A Own_GETS 0 <--
IS_A Own_GET_INSTR 0 <--
IS_A Other_GETS 0 <--
IS_A Other_GET_INSTR 0 <--
IS_A Other_GETX 0 <--
IS_A Other_PUTX 0 <--
IM_A Load 0 <--
IM_A Ifetch 0 <--
IM_A Store 0 <--
IM_A L1_to_L2 0 <--
IM_A L2_to_L1D 0 <--
IM_A L2_to_L1I 0 <--
IM_A L2_Replacement 0 <--
IM_A Own_GETX 0 <--
IM_A Other_GETS 0 <--
IM_A Other_GET_INSTR 0 <--
IM_A Other_GETX 0 <--
IM_A Other_PUTX 0 <--
SM_A Load 0 <--
SM_A Ifetch 0 <--
SM_A Store 0 <--
SM_A L1_to_L2 0 <--
SM_A L2_to_L1D 0 <--
SM_A L2_to_L1I 0 <--
SM_A L2_Replacement 0 <--
SM_A Own_GETX 0 <--
SM_A Other_GETS 0 <--
SM_A Other_GET_INSTR 0 <--
SM_A Other_GETX 0 <--
SM_A Other_PUTX 0 <--
MI_A Load 0 <--
MI_A Ifetch 0 <--
MI_A Store 0 <--
MI_A L1_to_L2 0 <--
MI_A L2_to_L1D 0 <--
MI_A L2_to_L1I 0 <--
MI_A L2_Replacement 0 <--
MI_A Own_PUTX 0 <--
MI_A Other_GETS 0 <--
MI_A Other_GET_INSTR 0 <--
MI_A Other_GETX 0 <--
MI_A Other_PUTX 0 <--
OI_A Load 0 <--
OI_A Ifetch 0 <--
OI_A Store 0 <--
OI_A L1_to_L2 0 <--
OI_A L2_to_L1D 0 <--
OI_A L2_to_L1I 0 <--
OI_A L2_Replacement 0 <--
OI_A Own_PUTX 0 <--
OI_A Other_GETS 0 <--
OI_A Other_GET_INSTR 0 <--
OI_A Other_GETX 0 <--
OI_A Other_PUTX 0 <--
II_A Load 0 <--
II_A Ifetch 0 <--
II_A Store 0 <--
II_A L1_to_L2 0 <--
II_A L2_to_L1D 0 <--
II_A L2_to_L1I 0 <--
II_A L2_Replacement 0 <--
II_A Own_PUTX 0 <--
II_A Other_GETS 0 <--
II_A Other_GET_INSTR 0 <--
II_A Other_GETX 0 <--
II_A Other_PUTX 0 <--
IS_D Load 0 <--
IS_D Ifetch 0 <--
IS_D Store 0 <--
IS_D L1_to_L2 0 <--
IS_D L2_to_L1D 0 <--
IS_D L2_to_L1I 0 <--
IS_D L2_Replacement 0 <--
IS_D Other_GETS 0 <--
IS_D Other_GET_INSTR 0 <--
IS_D Other_GETX 0 <--
IS_D Other_PUTX 0 <--
IS_D Data 0 <--
IS_D_I Load 0 <--
IS_D_I Ifetch 0 <--
IS_D_I Store 0 <--
IS_D_I L1_to_L2 0 <--
IS_D_I L2_to_L1D 0 <--
IS_D_I L2_to_L1I 0 <--
IS_D_I L2_Replacement 0 <--
IS_D_I Other_GETS 0 <--
IS_D_I Other_GET_INSTR 0 <--
IS_D_I Other_GETX 0 <--
IS_D_I Other_PUTX 0 <--
IS_D_I Data 0 <--
IM_D Load 0 <--
IM_D Ifetch 0 <--
IM_D Store 0 <--
IM_D L1_to_L2 0 <--
IM_D L2_to_L1D 0 <--
IM_D L2_to_L1I 0 <--
IM_D L2_Replacement 0 <--
IM_D Other_GETS 0 <--
IM_D Other_GET_INSTR 0 <--
IM_D Other_GETX 0 <--
IM_D Other_PUTX 0 <--
IM_D Data 0 <--
IM_D_O Load 0 <--
IM_D_O Ifetch 0 <--
IM_D_O Store 0 <--
IM_D_O L1_to_L2 0 <--
IM_D_O L2_to_L1D 0 <--
IM_D_O L2_to_L1I 0 <--
IM_D_O L2_Replacement 0 <--
IM_D_O Other_GETS 0 <--
IM_D_O Other_GET_INSTR 0 <--
IM_D_O Other_GETX 0 <--
IM_D_O Other_PUTX 0 <--
IM_D_O Data 0 <--
IM_D_I Load 0 <--
IM_D_I Ifetch 0 <--
IM_D_I Store 0 <--
IM_D_I L1_to_L2 0 <--
IM_D_I L2_to_L1D 0 <--
IM_D_I L2_to_L1I 0 <--
IM_D_I L2_Replacement 0 <--
IM_D_I Other_GETS 0 <--
IM_D_I Other_GET_INSTR 0 <--
IM_D_I Other_GETX 0 <--
IM_D_I Other_PUTX 0 <--
IM_D_I Data 0 <--
IM_D_OI Load 0 <--
IM_D_OI Ifetch 0 <--
IM_D_OI Store 0 <--
IM_D_OI L1_to_L2 0 <--
IM_D_OI L2_to_L1D 0 <--
IM_D_OI L2_to_L1I 0 <--
IM_D_OI L2_Replacement 0 <--
IM_D_OI Other_GETS 0 <--
IM_D_OI Other_GET_INSTR 0 <--
IM_D_OI Other_GETX 0 <--
IM_D_OI Other_PUTX 0 <--
IM_D_OI Data 0 <--
SM_D Load 0 <--
SM_D Ifetch 0 <--
SM_D Store 0 <--
SM_D L1_to_L2 0 <--
SM_D L2_to_L1D 0 <--
SM_D L2_to_L1I 0 <--
SM_D L2_Replacement 0 <--
SM_D Other_GETS 0 <--
SM_D Other_GET_INSTR 0 <--
SM_D Other_GETX 0 <--
SM_D Other_PUTX 0 <--
SM_D Data 0 <--
SM_D_O Load 0 <--
SM_D_O Ifetch 0 <--
SM_D_O Store 0 <--
SM_D_O L1_to_L2 0 <--
SM_D_O L2_to_L1D 0 <--
SM_D_O L2_to_L1I 0 <--
SM_D_O L2_Replacement 0 <--
SM_D_O Other_GETS 0 <--
SM_D_O Other_GET_INSTR 0 <--
SM_D_O Other_GETX 0 <--
SM_D_O Other_PUTX 0 <--
SM_D_O Data 0 <--
--- Directory ---
- Event Counts -
OtherAddress 0
GETS 0
GET_INSTR 0
GETX 0
PUTX_Owner 0
PUTX_NotOwner 0
- Transitions -
C OtherAddress 0 <--
C GETS 0 <--
C GET_INSTR 0 <--
C GETX 0 <--
I GETS 0 <--
I GET_INSTR 0 <--
I GETX 0 <--
I PUTX_NotOwner 0 <--
S GETS 0 <--
S GET_INSTR 0 <--
S GETX 0 <--
S PUTX_NotOwner 0 <--
SS GETS 0 <--
SS GET_INSTR 0 <--
SS GETX 0 <--
SS PUTX_NotOwner 0 <--
OS GETS 0 <--
OS GET_INSTR 0 <--
OS GETX 0 <--
OS PUTX_Owner 0 <--
OS PUTX_NotOwner 0 <--
OSS GETS 0 <--
OSS GET_INSTR 0 <--
OSS GETX 0 <--
OSS PUTX_Owner 0 <--
OSS PUTX_NotOwner 0 <--
M GETS 0 <--
M GET_INSTR 0 <--
M GETX 0 <--
M PUTX_Owner 0 <--
M PUTX_NotOwner 0 <--
IM Data 0 <--

20
tests/quick/00.hello/ref/alpha/tru64/simple-atomic-ruby/simerr
View file

@ -1,3 +1,23 @@
["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024"]
print config: 1
Creating new MessageBuffer for 0 0
Creating new MessageBuffer for 0 1
Creating new MessageBuffer for 0 2
Creating new MessageBuffer for 0 3
Creating new MessageBuffer for 0 4
Creating new MessageBuffer for 0 5
Creating new MessageBuffer for 1 0
Creating new MessageBuffer for 1 1
Creating new MessageBuffer for 1 2
Creating new MessageBuffer for 1 3
Creating new MessageBuffer for 1 4
Creating new MessageBuffer for 1 5
Creating new MessageBuffer for 2 0
Creating new MessageBuffer for 2 1
Creating new MessageBuffer for 2 2
Creating new MessageBuffer for 2 3
Creating new MessageBuffer for 2 4
Creating new MessageBuffer for 2 5
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...)

18
tests/quick/00.hello/ref/alpha/tru64/simple-atomic-ruby/simout
View file

@ -5,19 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 5 2009 07:34:00
M5 revision 8bea207e2193 6172 default qtip tip ruby_tests_refs.diff
M5 started May 5 2009 07:34:03
M5 executing on piton
command line: /n/piton/z/nate/build/xgem5/build/ALPHA_SE/m5.fast -d /n/piton/z/nate/build/xgem5/build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic-ruby -re tests/run.py /n/piton/z/nate/build/xgem5/build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic-ruby
M5 compiled Jul 6 2009 11:03:45
M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
M5 started Jul 6 2009 11:11:05
M5 executing on maize
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic-ruby
Global frequency set at 1000000000000 ticks per second
Ruby Timing Mode
Creating event queue...
Creating event queue done
Creating system...
Processors: 1
Creating system done
Ruby initialization complete
Debug: Adding to filter: 'q' (Queue)
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!

8
tests/quick/00.hello/ref/alpha/tru64/simple-atomic-ruby/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 44606 # Simulator instruction rate (inst/s)
host_mem_usage 199172 # Number of bytes of host memory used
host_seconds 0.06 # Real time elapsed on the host
host_tick_rate 22395015 # Simulator tick rate (ticks/s)
host_inst_rate 10832 # Simulator instruction rate (inst/s)
host_mem_usage 1360528 # Number of bytes of host memory used
host_seconds 0.24 # Real time elapsed on the host
host_tick_rate 5450330 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2577 # Number of instructions simulated
sim_seconds 0.000001 # Number of seconds simulated

5
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
View file

@ -78,10 +78,9 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=RubyMemory
clock=1
config_file=
config_options=
config_file=build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby/ruby.config
debug=false
debug_file=
debug_file=ruby.debug
file=
latency=30000
latency_var=0

956
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
View file

File diff suppressed because it is too large Load diff

20
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
View file

@ -1,3 +1,23 @@
["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024"]
print config: 1
Creating new MessageBuffer for 0 0
Creating new MessageBuffer for 0 1
Creating new MessageBuffer for 0 2
Creating new MessageBuffer for 0 3
Creating new MessageBuffer for 0 4
Creating new MessageBuffer for 0 5
Creating new MessageBuffer for 1 0
Creating new MessageBuffer for 1 1
Creating new MessageBuffer for 1 2
Creating new MessageBuffer for 1 3
Creating new MessageBuffer for 1 4
Creating new MessageBuffer for 1 5
Creating new MessageBuffer for 2 0
Creating new MessageBuffer for 2 1
Creating new MessageBuffer for 2 2
Creating new MessageBuffer for 2 3
Creating new MessageBuffer for 2 4
Creating new MessageBuffer for 2 5
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...)

18
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
View file

@ -5,19 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 5 2009 07:34:00
M5 revision 8bea207e2193 6172 default qtip tip ruby_tests_refs.diff
M5 started May 5 2009 07:34:03
M5 executing on piton
command line: /n/piton/z/nate/build/xgem5/build/ALPHA_SE/m5.fast -d /n/piton/z/nate/build/xgem5/build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py /n/piton/z/nate/build/xgem5/build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby
M5 compiled Jul 6 2009 11:03:45
M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
M5 started Jul 6 2009 11:11:06
M5 executing on maize
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby
Global frequency set at 1000000000000 ticks per second
Ruby Timing Mode
Creating event queue...
Creating event queue done
Creating system...
Processors: 1
Creating system done
Ruby initialization complete
Debug: Adding to filter: 'q' (Queue)
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!

8
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 6475 # Simulator instruction rate (inst/s)
host_mem_usage 199236 # Number of bytes of host memory used
host_seconds 0.40 # Real time elapsed on the host
host_tick_rate 24815516 # Simulator tick rate (ticks/s)
host_inst_rate 7760 # Simulator instruction rate (inst/s)
host_mem_usage 1360644 # Number of bytes of host memory used
host_seconds 0.33 # Real time elapsed on the host
host_tick_rate 29737002 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2577 # Number of instructions simulated
sim_seconds 0.000010 # Number of seconds simulated

5
tests/quick/00.hello/ref/mips/linux/simple-atomic-ruby/config.ini
View file

@ -135,10 +135,9 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=RubyMemory
clock=1
config_file=
config_options=
config_file=build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic-ruby/ruby.config
debug=false
debug_file=
debug_file=ruby.debug
file=
latency=30000
latency_var=0

20
tests/quick/00.hello/ref/mips/linux/simple-atomic-ruby/simerr
View file

@ -1,3 +1,23 @@
["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024"]
print config: 1
Creating new MessageBuffer for 0 0
Creating new MessageBuffer for 0 1
Creating new MessageBuffer for 0 2
Creating new MessageBuffer for 0 3
Creating new MessageBuffer for 0 4
Creating new MessageBuffer for 0 5
Creating new MessageBuffer for 1 0
Creating new MessageBuffer for 1 1
Creating new MessageBuffer for 1 2
Creating new MessageBuffer for 1 3
Creating new MessageBuffer for 1 4
Creating new MessageBuffer for 1 5
Creating new MessageBuffer for 2 0
Creating new MessageBuffer for 2 1
Creating new MessageBuffer for 2 2
Creating new MessageBuffer for 2 3
Creating new MessageBuffer for 2 4
Creating new MessageBuffer for 2 5
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here

18
tests/quick/00.hello/ref/mips/linux/simple-atomic-ruby/simout
View file

@ -5,19 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 5 2009 07:34:00
M5 revision 8bea207e2193 6172 default qtip tip ruby_tests_refs.diff
M5 started May 5 2009 07:34:02
M5 executing on piton
command line: /n/piton/z/nate/build/xgem5/build/MIPS_SE/m5.fast -d /n/piton/z/nate/build/xgem5/build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic-ruby -re tests/run.py /n/piton/z/nate/build/xgem5/build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic-ruby
M5 compiled Jul 6 2009 11:05:29
M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
M5 started Jul 6 2009 11:11:09
M5 executing on maize
command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic-ruby -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic-ruby
Global frequency set at 1000000000000 ticks per second
Ruby Timing Mode
Creating event queue...
Creating event queue done
Creating system...
Processors: 1
Creating system done
Ruby initialization complete
Debug: Adding to filter: 'q' (Queue)
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello World!

8
tests/quick/00.hello/ref/mips/linux/simple-atomic-ruby/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 15454 # Simulator instruction rate (inst/s)
host_mem_usage 201224 # Number of bytes of host memory used
host_seconds 0.37 # Real time elapsed on the host
host_tick_rate 7721818 # Simulator tick rate (ticks/s)
host_inst_rate 47334 # Simulator instruction rate (inst/s)
host_mem_usage 1362452 # Number of bytes of host memory used
host_seconds 0.12 # Real time elapsed on the host
host_tick_rate 23634419 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5656 # Number of instructions simulated
sim_seconds 0.000003 # Number of seconds simulated

5
tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
View file

@ -132,10 +132,9 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=RubyMemory
clock=1
config_file=
config_options=
config_file=build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby/ruby.config
debug=false
debug_file=
debug_file=ruby.debug
file=
latency=30000
latency_var=0

20
tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simerr
View file

@ -1,3 +1,23 @@
["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024"]
print config: 1
Creating new MessageBuffer for 0 0
Creating new MessageBuffer for 0 1
Creating new MessageBuffer for 0 2
Creating new MessageBuffer for 0 3
Creating new MessageBuffer for 0 4
Creating new MessageBuffer for 0 5
Creating new MessageBuffer for 1 0
Creating new MessageBuffer for 1 1
Creating new MessageBuffer for 1 2
Creating new MessageBuffer for 1 3
Creating new MessageBuffer for 1 4
Creating new MessageBuffer for 1 5
Creating new MessageBuffer for 2 0
Creating new MessageBuffer for 2 1
Creating new MessageBuffer for 2 2
Creating new MessageBuffer for 2 3
Creating new MessageBuffer for 2 4
Creating new MessageBuffer for 2 5
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here

18
tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout
View file

@ -5,19 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 5 2009 07:34:00
M5 revision 8bea207e2193 6172 default qtip tip ruby_tests_refs.diff
M5 started May 5 2009 07:34:02
M5 executing on piton
command line: /n/piton/z/nate/build/xgem5/build/MIPS_SE/m5.fast -d /n/piton/z/nate/build/xgem5/build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby -re tests/run.py /n/piton/z/nate/build/xgem5/build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby
M5 compiled Jul 6 2009 11:05:29
M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
M5 started Jul 6 2009 11:11:09
M5 executing on maize
command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby
Global frequency set at 1000000000000 ticks per second
Ruby Timing Mode
Creating event queue...
Creating event queue done
Creating system...
Processors: 1
Creating system done
Ruby initialization complete
Debug: Adding to filter: 'q' (Queue)
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello World!

8
tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 10877 # Simulator instruction rate (inst/s)
host_mem_usage 201300 # Number of bytes of host memory used
host_seconds 0.52 # Real time elapsed on the host
host_tick_rate 44468411 # Simulator tick rate (ticks/s)
host_inst_rate 8081 # Simulator instruction rate (inst/s)
host_mem_usage 1362552 # Number of bytes of host memory used
host_seconds 0.70 # Real time elapsed on the host
host_tick_rate 33041595 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5656 # Number of instructions simulated
sim_seconds 0.000023 # Number of seconds simulated

5
tests/quick/00.hello/ref/sparc/linux/simple-atomic-ruby/config.ini
View file

@ -81,10 +81,9 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=RubyMemory
clock=1
config_file=
config_options=
config_file=build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic-ruby/ruby.config
debug=false
debug_file=
debug_file=ruby.debug
file=
latency=30000
latency_var=0

819
tests/quick/00.hello/ref/sparc/linux/simple-atomic-ruby/ruby.stats
View file

@ -1,258 +1,81 @@
================ Begin RubySystem Configuration Print ================
Ruby Configuration
------------------
protocol: MOSI_SMP_bcast
compiled_at: 22:54:24, May 4 2009
RUBY_DEBUG: false
hostname: piton
g_RANDOM_SEED: 1
g_DEADLOCK_THRESHOLD: 500000
RANDOMIZATION: false
g_SYNTHETIC_DRIVER: false
g_DETERMINISTIC_DRIVER: false
g_FILTERING_ENABLED: false
g_DISTRIBUTED_PERSISTENT_ENABLED: true
g_DYNAMIC_TIMEOUT_ENABLED: true
g_RETRY_THRESHOLD: 1
g_FIXED_TIMEOUT_LATENCY: 300
g_trace_warmup_length: 1000000
g_bash_bandwidth_adaptive_threshold: 0.75
g_tester_length: 0
g_synthetic_locks: 2048
g_deterministic_addrs: 1
g_SpecifiedGenerator: DetermInvGenerator
g_callback_counter: 0
g_NUM_COMPLETIONS_BEFORE_PASS: 0
g_NUM_SMT_THREADS: 1
g_think_time: 5
g_hold_time: 5
g_wait_time: 5
PROTOCOL_DEBUG_TRACE: true
DEBUG_FILTER_STRING: none
DEBUG_VERBOSITY_STRING: none
DEBUG_START_TIME: 0
DEBUG_OUTPUT_FILENAME: none
SIMICS_RUBY_MULTIPLIER: 4
OPAL_RUBY_MULTIPLIER: 1
TRANSACTION_TRACE_ENABLED: false
USER_MODE_DATA_ONLY: false
PROFILE_HOT_LINES: false
PROFILE_ALL_INSTRUCTIONS: false
PRINT_INSTRUCTION_TRACE: false
g_DEBUG_CYCLE: 0
BLOCK_STC: false
PERFECT_MEMORY_SYSTEM: false
PERFECT_MEMORY_SYSTEM_LATENCY: 0
DATA_BLOCK: false
REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH: false
L1_CACHE_ASSOC: 4
L1_CACHE_NUM_SETS_BITS: 8
L2_CACHE_ASSOC: 4
L2_CACHE_NUM_SETS_BITS: 16
g_MEMORY_SIZE_BYTES: 4294967296
g_DATA_BLOCK_BYTES: 64
g_PAGE_SIZE_BYTES: 4096
g_REPLACEMENT_POLICY: PSEDUO_LRU
g_NUM_PROCESSORS: 1
g_NUM_L2_BANKS: 1
g_NUM_MEMORIES: 1
g_PROCS_PER_CHIP: 1
g_NUM_CHIPS: 1
g_NUM_CHIP_BITS: 0
g_MEMORY_SIZE_BITS: 32
g_DATA_BLOCK_BITS: 6
g_PAGE_SIZE_BITS: 12
g_NUM_PROCESSORS_BITS: 0
g_PROCS_PER_CHIP_BITS: 0
g_NUM_L2_BANKS_BITS: 0
g_NUM_L2_BANKS_PER_CHIP_BITS: 0
g_NUM_L2_BANKS_PER_CHIP: 1
g_NUM_MEMORIES_BITS: 0
g_NUM_MEMORIES_PER_CHIP: 1
g_MEMORY_MODULE_BITS: 26
g_MEMORY_MODULE_BLOCKS: 67108864
MAP_L2BANKS_TO_LOWEST_BITS: false
DIRECTORY_CACHE_LATENCY: 6
NULL_LATENCY: 1
ISSUE_LATENCY: 2
CACHE_RESPONSE_LATENCY: 12
L2_RESPONSE_LATENCY: 6
L2_TAG_LATENCY: 6
L1_RESPONSE_LATENCY: 3
MEMORY_RESPONSE_LATENCY_MINUS_2: 158
DIRECTORY_LATENCY: 80
NETWORK_LINK_LATENCY: 1
COPY_HEAD_LATENCY: 4
ON_CHIP_LINK_LATENCY: 1
RECYCLE_LATENCY: 10
L2_RECYCLE_LATENCY: 5
TIMER_LATENCY: 10000
TBE_RESPONSE_LATENCY: 1
PERIODIC_TIMER_WAKEUPS: true
PROFILE_EXCEPTIONS: false
PROFILE_XACT: true
PROFILE_NONXACT: false
XACT_DEBUG: true
XACT_DEBUG_LEVEL: 1
XACT_MEMORY: false
XACT_ENABLE_TOURMALINE: false
XACT_NUM_CURRENT: 0
XACT_LAST_UPDATE: 0
XACT_ISOLATION_CHECK: false
PERFECT_FILTER: true
READ_WRITE_FILTER: Perfect_
PERFECT_VIRTUAL_FILTER: true
VIRTUAL_READ_WRITE_FILTER: Perfect_
PERFECT_SUMMARY_FILTER: true
SUMMARY_READ_WRITE_FILTER: Perfect_
XACT_EAGER_CD: true
XACT_LAZY_VM: false
XACT_CONFLICT_RES: BASE
XACT_VISUALIZER: false
XACT_COMMIT_TOKEN_LATENCY: 0
XACT_NO_BACKOFF: false
XACT_LOG_BUFFER_SIZE: 0
XACT_STORE_PREDICTOR_HISTORY: 256
XACT_STORE_PREDICTOR_ENTRIES: 256
XACT_STORE_PREDICTOR_THRESHOLD: 4
XACT_FIRST_ACCESS_COST: 0
XACT_FIRST_PAGE_ACCESS_COST: 0
ENABLE_MAGIC_WAITING: false
ENABLE_WATCHPOINT: false
XACT_ENABLE_VIRTUALIZATION_LOGTM_SE: false
ATMTP_ENABLED: false
ATMTP_ABORT_ON_NON_XACT_INST: false
ATMTP_ALLOW_SAVE_RESTORE_IN_XACT: false
ATMTP_XACT_MAX_STORES: 32
ATMTP_DEBUG_LEVEL: 0
L1_REQUEST_LATENCY: 2
L2_REQUEST_LATENCY: 4
SINGLE_ACCESS_L2_BANKS: true
SEQUENCER_TO_CONTROLLER_LATENCY: 4
L1CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
L2CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
DIRECTORY_TRANSITIONS_PER_RUBY_CYCLE: 32
g_SEQUENCER_OUTSTANDING_REQUESTS: 16
NUMBER_OF_TBES: 128
NUMBER_OF_L1_TBES: 32
NUMBER_OF_L2_TBES: 32
FINITE_BUFFERING: false
FINITE_BUFFER_SIZE: 3
PROCESSOR_BUFFER_SIZE: 10
PROTOCOL_BUFFER_SIZE: 32
TSO: false
g_NETWORK_TOPOLOGY: HIERARCHICAL_SWITCH
g_CACHE_DESIGN: NUCA
g_endpoint_bandwidth: 10000
g_adaptive_routing: true
NUMBER_OF_VIRTUAL_NETWORKS: 4
FAN_OUT_DEGREE: 4
g_PRINT_TOPOLOGY: true
XACT_LENGTH: 0
XACT_SIZE: 0
ABORT_RETRY_TIME: 0
g_GARNET_NETWORK: false
g_DETAIL_NETWORK: false
g_NETWORK_TESTING: false
g_FLIT_SIZE: 16
g_NUM_PIPE_STAGES: 4
g_VCS_PER_CLASS: 4
g_BUFFER_SIZE: 4
MEM_BUS_CYCLE_MULTIPLIER: 10
BANKS_PER_RANK: 8
RANKS_PER_DIMM: 2
DIMMS_PER_CHANNEL: 2
BANK_BIT_0: 8
RANK_BIT_0: 11
DIMM_BIT_0: 12
BANK_QUEUE_SIZE: 12
BANK_BUSY_TIME: 11
RANK_RANK_DELAY: 1
READ_WRITE_DELAY: 2
BASIC_BUS_BUSY_TIME: 2
MEM_CTL_LATENCY: 12
REFRESH_PERIOD: 1560
TFAW: 0
MEM_RANDOM_ARBITRATE: 0
MEM_FIXED_DELAY: 0
Chip Config
-----------
Total_Chips: 1
L1Cache_TBEs numberPerChip: 1
TBEs_per_TBETable: 128
L1Cache_L1IcacheMemory numberPerChip: 1
Cache config: L1Cache_0_L1I
cache_associativity: 4
num_cache_sets_bits: 8
num_cache_sets: 256
cache_set_size_bytes: 16384
cache_set_size_Kbytes: 16
cache_set_size_Mbytes: 0.015625
cache_size_bytes: 65536
cache_size_Kbytes: 64
cache_size_Mbytes: 0.0625
L1Cache_L1DcacheMemory numberPerChip: 1
Cache config: L1Cache_0_L1D
cache_associativity: 4
num_cache_sets_bits: 8
num_cache_sets: 256
cache_set_size_bytes: 16384
cache_set_size_Kbytes: 16
cache_set_size_Mbytes: 0.015625
cache_size_bytes: 65536
cache_size_Kbytes: 64
cache_size_Mbytes: 0.0625
L1Cache_L2cacheMemory numberPerChip: 1
Cache config: L1Cache_0_L2
cache_associativity: 4
num_cache_sets_bits: 16
num_cache_sets: 65536
cache_set_size_bytes: 4194304
cache_set_size_Kbytes: 4096
cache_set_size_Mbytes: 4
cache_size_bytes: 16777216
cache_size_Kbytes: 16384
cache_size_Mbytes: 16
L1Cache_mandatoryQueue numberPerChip: 1
L1Cache_sequencer numberPerChip: 1
sequencer: Sequencer - SC
RubySystem config:
random_seed: 539659
randomization: 0
tech_nm: 45
freq_mhz: 3000
block_size_bytes: 64
block_size_bits: 6
memory_size_bytes: 1073741824
memory_size_bits: 30
DMA_Controller config: DMAController_0
version: 0
buffer_size: 32
dma_sequencer: DMASequencer_0
number_of_TBEs: 128
transitions_per_cycle: 32
Directory_Controller config: DirectoryController_0
version: 0
buffer_size: 32
directory_latency: 6
directory_name: DirectoryMemory_0
memory_controller_name: MemoryControl_0
memory_latency: 158
number_of_TBEs: 128
recycle_latency: 10
to_mem_ctrl_latency: 1
transitions_per_cycle: 32
L1Cache_Controller config: L1CacheController_0
version: 0
buffer_size: 32
cache: l1u_0
cache_response_latency: 12
issue_latency: 2
number_of_TBEs: 128
sequencer: Sequencer_0
transitions_per_cycle: 32
Cache config: l1u_0
controller: L1CacheController_0
cache_associativity: 8
num_cache_sets_bits: 2
num_cache_sets: 4
cache_set_size_bytes: 256
cache_set_size_Kbytes: 0.25
cache_set_size_Mbytes: 0.000244141
cache_size_bytes: 2048
cache_size_Kbytes: 2
cache_size_Mbytes: 0.00195312
DirectoryMemory Global Config:
number of directory memories: 1
total memory size bytes: 1073741824
total memory size bits: 30
DirectoryMemory module config: DirectoryMemory_0
controller: DirectoryController_0
version: 0
memory_bits: 30
memory_size_bytes: 1073741824
memory_size_Kbytes: 1.04858e+06
memory_size_Mbytes: 1024
memory_size_Gbytes: 1
Seqeuncer config: Sequencer_0
controller: L1CacheController_0
version: 0
max_outstanding_requests: 16
L1Cache_storeBuffer numberPerChip: 1
Store buffer entries: 128 (Only valid if TSO is enabled)
Directory_directory numberPerChip: 1
Memory config:
memory_bits: 32
memory_size_bytes: 4294967296
memory_size_Kbytes: 4.1943e+06
memory_size_Mbytes: 4096
memory_size_Gbytes: 4
module_bits: 26
module_size_lines: 67108864
module_size_bytes: 4294967296
module_size_Kbytes: 4.1943e+06
module_size_Mbytes: 4096
deadlock_threshold: 500000
Network Configuration
---------------------
network: SIMPLE_NETWORK
topology: HIERARCHICAL_SWITCH
topology: theTopology
virtual_net_0: active, ordered
virtual_net_1: active, unordered
virtual_net_2: inactive
virtual_net_1: active, ordered
virtual_net_2: active, ordered
virtual_net_3: inactive
virtual_net_4: active, ordered
virtual_net_5: active, ordered
--- Begin Topology Print ---
@ -260,10 +83,16 @@ Topology print ONLY indicates the _NETWORK_ latency between two machines
It does NOT include the latency within the machines
L1Cache-0 Network Latencies
L1Cache-0 -> Directory-0 net_lat: 5
L1Cache-0 -> Directory-0 net_lat: 7
L1Cache-0 -> DMA-0 net_lat: 7
Directory-0 Network Latencies
Directory-0 -> L1Cache-0 net_lat: 5
Directory-0 -> L1Cache-0 net_lat: 7
Directory-0 -> DMA-0 net_lat: 7
DMA-0 Network Latencies
DMA-0 -> L1Cache-0 net_lat: 7
DMA-0 -> Directory-0 net_lat: 7
--- End Topology Print ---
@ -274,27 +103,27 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
Real time: May/05/2009 07:34:03
Real time: Jul/06/2009 11:11:24
Profiler Stats
--------------
Elapsed_time_in_seconds: 1
Elapsed_time_in_minutes: 0.0166667
Elapsed_time_in_hours: 0.000277778
Elapsed_time_in_days: 1.15741e-05
Elapsed_time_in_seconds: 0
Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
Virtual_time_in_seconds: 0.17
Virtual_time_in_minutes: 0.00283333
Virtual_time_in_hours: 4.72222e-05
Virtual_time_in_days: 4.72222e-05
Virtual_time_in_seconds: 0.23
Virtual_time_in_minutes: 0.00383333
Virtual_time_in_hours: 6.38889e-05
Virtual_time_in_days: 6.38889e-05
Ruby_current_time: 2701001
Ruby_start_time: 1
Ruby_cycles: 2701000
mbytes_resident: 34.9023
mbytes_total: 196.324
resident_ratio: 0.177799
mbytes_resident: 144.91
mbytes_total: 1330.19
resident_ratio: 0.108942
Total_misses: 0
total_misses: 0 [ 0 ]
@ -302,7 +131,7 @@ user_misses: 0 [ 0 ]
supervisor_misses: 0 [ 0 ]
instruction_executed: 1 [ 1 ]
cycles_executed: 1 [ 1 ]
ruby_cycles_executed: 2701001 [ 2701001 ]
cycles_per_instruction: 2.701e+06 [ 2.701e+06 ]
misses_per_thousand_instructions: 0 [ 0 ]
@ -352,6 +181,7 @@ L2_cache cache stats:
Busy Controller Counts:
L1Cache-0:0
Directory-0:0
DMA-0:0
Busy Bank Count:0
@ -390,406 +220,163 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard dev
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Resource Usage
--------------
page_size: 4096
user_time: 0
system_time: 0
page_reclaims: 9143
page_reclaims: 37843
page_faults: 0
swaps: 0
block_inputs: 0
block_outputs: 56
MessageBuffer: [Chip 0 0, L1Cache, mandatoryQueue_in] stats - msgs:0 full:0
block_outputs: 40
Network Stats
-------------
switch_0_inlinks: 1
switch_0_outlinks: 1
switch_0_inlinks: 2
switch_0_outlinks: 2
links_utilized_percent_switch_0: 0
links_utilized_percent_switch_0_link_0: 0 bw: 10000 base_latency: 1
links_utilized_percent_switch_0_link_0: 0 bw: 640000 base_latency: 1
links_utilized_percent_switch_0_link_1: 0 bw: 160000 base_latency: 1
switch_1_inlinks: 1
switch_1_outlinks: 1
switch_1_inlinks: 2
switch_1_outlinks: 2
links_utilized_percent_switch_1: 0
links_utilized_percent_switch_1_link_0: 0 bw: 10000 base_latency: 1
links_utilized_percent_switch_1_link_0: 0 bw: 640000 base_latency: 1
links_utilized_percent_switch_1_link_1: 0 bw: 160000 base_latency: 1
switch_2_inlinks: 2
switch_2_outlinks: 2
links_utilized_percent_switch_2: 0
links_utilized_percent_switch_2_link_0: 0 bw: 10000 base_latency: 1
links_utilized_percent_switch_2_link_1: 0 bw: 10000 base_latency: 1
links_utilized_percent_switch_2_link_0: 0 bw: 640000 base_latency: 1
links_utilized_percent_switch_2_link_1: 0 bw: 160000 base_latency: 1
switch_3_inlinks: 3
switch_3_outlinks: 3
links_utilized_percent_switch_3: 0
links_utilized_percent_switch_3_link_0: 0 bw: 160000 base_latency: 1
links_utilized_percent_switch_3_link_1: 0 bw: 160000 base_latency: 1
links_utilized_percent_switch_3_link_2: 0 bw: 160000 base_latency: 1
Chip Stats
----------
--- DMA ---
- Event Counts -
ReadRequest 0
WriteRequest 0
Data 0
Ack 0
- Transitions -
READY ReadRequest 0 <--
READY WriteRequest 0 <--
BUSY_RD Data 0 <--
BUSY_WR Ack 0 <--
--- Directory ---
- Event Counts -
GETX 0
GETS 0
PUTX 0
PUTX_NotOwner 0
DMA_READ 0
DMA_WRITE 0
Memory_Data 0
Memory_Ack 0
- Transitions -
I GETX 0 <--
I PUTX_NotOwner 0 <--
I DMA_READ 0 <--
I DMA_WRITE 0 <--
M GETX 0 <--
M PUTX 0 <--
M PUTX_NotOwner 0 <--
M DMA_READ 0 <--
M DMA_WRITE 0 <--
M_DRD GETX 0 <--
M_DRD PUTX 0 <--
M_DWR GETX 0 <--
M_DWR PUTX 0 <--
M_DWRI Memory_Ack 0 <--
IM GETX 0 <--
IM GETS 0 <--
IM PUTX 0 <--
IM PUTX_NotOwner 0 <--
IM DMA_READ 0 <--
IM DMA_WRITE 0 <--
IM Memory_Data 0 <--
MI GETX 0 <--
MI GETS 0 <--
MI PUTX 0 <--
MI PUTX_NotOwner 0 <--
MI DMA_READ 0 <--
MI DMA_WRITE 0 <--
MI Memory_Ack 0 <--
ID GETX 0 <--
ID GETS 0 <--
ID PUTX 0 <--
ID PUTX_NotOwner 0 <--
ID DMA_READ 0 <--
ID DMA_WRITE 0 <--
ID Memory_Data 0 <--
ID_W GETX 0 <--
ID_W GETS 0 <--
ID_W PUTX 0 <--
ID_W PUTX_NotOwner 0 <--
ID_W DMA_READ 0 <--
ID_W DMA_WRITE 0 <--
ID_W Memory_Ack 0 <--
--- L1Cache ---
- Event Counts -
Load 0
Ifetch 0
Store 0
L1_to_L2 0
L2_to_L1D 0
L2_to_L1I 0
L2_Replacement 0
Own_GETS 0
Own_GET_INSTR 0
Own_GETX 0
Own_PUTX 0
Other_GETS 0
Other_GET_INSTR 0
Other_GETX 0
Other_PUTX 0
Data 0
Fwd_GETX 0
Inv 0
Replacement 0
Writeback_Ack 0
Writeback_Nack 0
- Transitions -
NP Load 0 <--
NP Ifetch 0 <--
NP Store 0 <--
NP Other_GETS 0 <--
NP Other_GET_INSTR 0 <--
NP Other_GETX 0 <--
NP Other_PUTX 0 <--
I Load 0 <--
I Ifetch 0 <--
I Store 0 <--
I L1_to_L2 0 <--
I L2_to_L1D 0 <--
I L2_to_L1I 0 <--
I L2_Replacement 0 <--
I Other_GETS 0 <--
I Other_GET_INSTR 0 <--
I Other_GETX 0 <--
I Other_PUTX 0 <--
I Inv 0 <--
I Replacement 0 <--
S Load 0 <--
S Ifetch 0 <--
S Store 0 <--
S L1_to_L2 0 <--
S L2_to_L1D 0 <--
S L2_to_L1I 0 <--
S L2_Replacement 0 <--
S Other_GETS 0 <--
S Other_GET_INSTR 0 <--
S Other_GETX 0 <--
S Other_PUTX 0 <--
O Load 0 <--
O Ifetch 0 <--
O Store 0 <--
O L1_to_L2 0 <--
O L2_to_L1D 0 <--
O L2_to_L1I 0 <--
O L2_Replacement 0 <--
O Other_GETS 0 <--
O Other_GET_INSTR 0 <--
O Other_GETX 0 <--
O Other_PUTX 0 <--
II Writeback_Nack 0 <--
M Load 0 <--
M Ifetch 0 <--
M Store 0 <--
M L1_to_L2 0 <--
M L2_to_L1D 0 <--
M L2_to_L1I 0 <--
M L2_Replacement 0 <--
M Other_GETS 0 <--
M Other_GET_INSTR 0 <--
M Other_GETX 0 <--
M Other_PUTX 0 <--
M Fwd_GETX 0 <--
M Inv 0 <--
M Replacement 0 <--
IS_AD Load 0 <--
IS_AD Ifetch 0 <--
IS_AD Store 0 <--
IS_AD L1_to_L2 0 <--
IS_AD L2_to_L1D 0 <--
IS_AD L2_to_L1I 0 <--
IS_AD L2_Replacement 0 <--
IS_AD Own_GETS 0 <--
IS_AD Own_GET_INSTR 0 <--
IS_AD Other_GETS 0 <--
IS_AD Other_GET_INSTR 0 <--
IS_AD Other_GETX 0 <--
IS_AD Other_PUTX 0 <--
IS_AD Data 0 <--
MI Fwd_GETX 0 <--
MI Inv 0 <--
MI Writeback_Ack 0 <--
IM_AD Load 0 <--
IM_AD Ifetch 0 <--
IM_AD Store 0 <--
IM_AD L1_to_L2 0 <--
IM_AD L2_to_L1D 0 <--
IM_AD L2_to_L1I 0 <--
IM_AD L2_Replacement 0 <--
IM_AD Own_GETX 0 <--
IM_AD Other_GETS 0 <--
IM_AD Other_GET_INSTR 0 <--
IM_AD Other_GETX 0 <--
IM_AD Other_PUTX 0 <--
IM_AD Data 0 <--
IS Data 0 <--
SM_AD Load 0 <--
SM_AD Ifetch 0 <--
SM_AD Store 0 <--
SM_AD L1_to_L2 0 <--
SM_AD L2_to_L1D 0 <--
SM_AD L2_to_L1I 0 <--
SM_AD L2_Replacement 0 <--
SM_AD Own_GETX 0 <--
SM_AD Other_GETS 0 <--
SM_AD Other_GET_INSTR 0 <--
SM_AD Other_GETX 0 <--
SM_AD Other_PUTX 0 <--
SM_AD Data 0 <--
OM_A Load 0 <--
OM_A Ifetch 0 <--
OM_A Store 0 <--
OM_A L1_to_L2 0 <--
OM_A L2_to_L1D 0 <--
OM_A L2_to_L1I 0 <--
OM_A L2_Replacement 0 <--
OM_A Own_GETX 0 <--
OM_A Other_GETS 0 <--
OM_A Other_GET_INSTR 0 <--
OM_A Other_GETX 0 <--
OM_A Other_PUTX 0 <--
OM_A Data 0 <--
IS_A Load 0 <--
IS_A Ifetch 0 <--
IS_A Store 0 <--
IS_A L1_to_L2 0 <--
IS_A L2_to_L1D 0 <--
IS_A L2_to_L1I 0 <--
IS_A L2_Replacement 0 <--
IS_A Own_GETS 0 <--
IS_A Own_GET_INSTR 0 <--
IS_A Other_GETS 0 <--
IS_A Other_GET_INSTR 0 <--
IS_A Other_GETX 0 <--
IS_A Other_PUTX 0 <--
IM_A Load 0 <--
IM_A Ifetch 0 <--
IM_A Store 0 <--
IM_A L1_to_L2 0 <--
IM_A L2_to_L1D 0 <--
IM_A L2_to_L1I 0 <--
IM_A L2_Replacement 0 <--
IM_A Own_GETX 0 <--
IM_A Other_GETS 0 <--
IM_A Other_GET_INSTR 0 <--
IM_A Other_GETX 0 <--
IM_A Other_PUTX 0 <--
SM_A Load 0 <--
SM_A Ifetch 0 <--
SM_A Store 0 <--
SM_A L1_to_L2 0 <--
SM_A L2_to_L1D 0 <--
SM_A L2_to_L1I 0 <--
SM_A L2_Replacement 0 <--
SM_A Own_GETX 0 <--
SM_A Other_GETS 0 <--
SM_A Other_GET_INSTR 0 <--
SM_A Other_GETX 0 <--
SM_A Other_PUTX 0 <--
MI_A Load 0 <--
MI_A Ifetch 0 <--
MI_A Store 0 <--
MI_A L1_to_L2 0 <--
MI_A L2_to_L1D 0 <--
MI_A L2_to_L1I 0 <--
MI_A L2_Replacement 0 <--
MI_A Own_PUTX 0 <--
MI_A Other_GETS 0 <--
MI_A Other_GET_INSTR 0 <--
MI_A Other_GETX 0 <--
MI_A Other_PUTX 0 <--
OI_A Load 0 <--
OI_A Ifetch 0 <--
OI_A Store 0 <--
OI_A L1_to_L2 0 <--
OI_A L2_to_L1D 0 <--
OI_A L2_to_L1I 0 <--
OI_A L2_Replacement 0 <--
OI_A Own_PUTX 0 <--
OI_A Other_GETS 0 <--
OI_A Other_GET_INSTR 0 <--
OI_A Other_GETX 0 <--
OI_A Other_PUTX 0 <--
II_A Load 0 <--
II_A Ifetch 0 <--
II_A Store 0 <--
II_A L1_to_L2 0 <--
II_A L2_to_L1D 0 <--
II_A L2_to_L1I 0 <--
II_A L2_Replacement 0 <--
II_A Own_PUTX 0 <--
II_A Other_GETS 0 <--
II_A Other_GET_INSTR 0 <--
II_A Other_GETX 0 <--
II_A Other_PUTX 0 <--
IS_D Load 0 <--
IS_D Ifetch 0 <--
IS_D Store 0 <--
IS_D L1_to_L2 0 <--
IS_D L2_to_L1D 0 <--
IS_D L2_to_L1I 0 <--
IS_D L2_Replacement 0 <--
IS_D Other_GETS 0 <--
IS_D Other_GET_INSTR 0 <--
IS_D Other_GETX 0 <--
IS_D Other_PUTX 0 <--
IS_D Data 0 <--
IS_D_I Load 0 <--
IS_D_I Ifetch 0 <--
IS_D_I Store 0 <--
IS_D_I L1_to_L2 0 <--
IS_D_I L2_to_L1D 0 <--
IS_D_I L2_to_L1I 0 <--
IS_D_I L2_Replacement 0 <--
IS_D_I Other_GETS 0 <--
IS_D_I Other_GET_INSTR 0 <--
IS_D_I Other_GETX 0 <--
IS_D_I Other_PUTX 0 <--
IS_D_I Data 0 <--
IM_D Load 0 <--
IM_D Ifetch 0 <--
IM_D Store 0 <--
IM_D L1_to_L2 0 <--
IM_D L2_to_L1D 0 <--
IM_D L2_to_L1I 0 <--
IM_D L2_Replacement 0 <--
IM_D Other_GETS 0 <--
IM_D Other_GET_INSTR 0 <--
IM_D Other_GETX 0 <--
IM_D Other_PUTX 0 <--
IM_D Data 0 <--
IM_D_O Load 0 <--
IM_D_O Ifetch 0 <--
IM_D_O Store 0 <--
IM_D_O L1_to_L2 0 <--
IM_D_O L2_to_L1D 0 <--
IM_D_O L2_to_L1I 0 <--
IM_D_O L2_Replacement 0 <--
IM_D_O Other_GETS 0 <--
IM_D_O Other_GET_INSTR 0 <--
IM_D_O Other_GETX 0 <--
IM_D_O Other_PUTX 0 <--
IM_D_O Data 0 <--
IM_D_I Load 0 <--
IM_D_I Ifetch 0 <--
IM_D_I Store 0 <--
IM_D_I L1_to_L2 0 <--
IM_D_I L2_to_L1D 0 <--
IM_D_I L2_to_L1I 0 <--
IM_D_I L2_Replacement 0 <--
IM_D_I Other_GETS 0 <--
IM_D_I Other_GET_INSTR 0 <--
IM_D_I Other_GETX 0 <--
IM_D_I Other_PUTX 0 <--
IM_D_I Data 0 <--
IM_D_OI Load 0 <--
IM_D_OI Ifetch 0 <--
IM_D_OI Store 0 <--
IM_D_OI L1_to_L2 0 <--
IM_D_OI L2_to_L1D 0 <--
IM_D_OI L2_to_L1I 0 <--
IM_D_OI L2_Replacement 0 <--
IM_D_OI Other_GETS 0 <--
IM_D_OI Other_GET_INSTR 0 <--
IM_D_OI Other_GETX 0 <--
IM_D_OI Other_PUTX 0 <--
IM_D_OI Data 0 <--
SM_D Load 0 <--
SM_D Ifetch 0 <--
SM_D Store 0 <--
SM_D L1_to_L2 0 <--
SM_D L2_to_L1D 0 <--
SM_D L2_to_L1I 0 <--
SM_D L2_Replacement 0 <--
SM_D Other_GETS 0 <--
SM_D Other_GET_INSTR 0 <--
SM_D Other_GETX 0 <--
SM_D Other_PUTX 0 <--
SM_D Data 0 <--
SM_D_O Load 0 <--
SM_D_O Ifetch 0 <--
SM_D_O Store 0 <--
SM_D_O L1_to_L2 0 <--
SM_D_O L2_to_L1D 0 <--
SM_D_O L2_to_L1I 0 <--
SM_D_O L2_Replacement 0 <--
SM_D_O Other_GETS 0 <--
SM_D_O Other_GET_INSTR 0 <--
SM_D_O Other_GETX 0 <--
SM_D_O Other_PUTX 0 <--
SM_D_O Data 0 <--
--- Directory ---
- Event Counts -
OtherAddress 0
GETS 0
GET_INSTR 0
GETX 0
PUTX_Owner 0
PUTX_NotOwner 0
- Transitions -
C OtherAddress 0 <--
C GETS 0 <--
C GET_INSTR 0 <--
C GETX 0 <--
I GETS 0 <--
I GET_INSTR 0 <--
I GETX 0 <--
I PUTX_NotOwner 0 <--
S GETS 0 <--
S GET_INSTR 0 <--
S GETX 0 <--
S PUTX_NotOwner 0 <--
SS GETS 0 <--
SS GET_INSTR 0 <--
SS GETX 0 <--
SS PUTX_NotOwner 0 <--
OS GETS 0 <--
OS GET_INSTR 0 <--
OS GETX 0 <--
OS PUTX_Owner 0 <--
OS PUTX_NotOwner 0 <--
OSS GETS 0 <--
OSS GET_INSTR 0 <--
OSS GETX 0 <--
OSS PUTX_Owner 0 <--
OSS PUTX_NotOwner 0 <--
M GETS 0 <--
M GET_INSTR 0 <--
M GETX 0 <--
M PUTX_Owner 0 <--
M PUTX_NotOwner 0 <--
IM Data 0 <--

20
tests/quick/00.hello/ref/sparc/linux/simple-atomic-ruby/simerr
View file

@ -1,3 +1,23 @@
["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024"]
print config: 1
Creating new MessageBuffer for 0 0
Creating new MessageBuffer for 0 1
Creating new MessageBuffer for 0 2
Creating new MessageBuffer for 0 3
Creating new MessageBuffer for 0 4
Creating new MessageBuffer for 0 5
Creating new MessageBuffer for 1 0
Creating new MessageBuffer for 1 1
Creating new MessageBuffer for 1 2
Creating new MessageBuffer for 1 3
Creating new MessageBuffer for 1 4
Creating new MessageBuffer for 1 5
Creating new MessageBuffer for 2 0
Creating new MessageBuffer for 2 1
Creating new MessageBuffer for 2 2
Creating new MessageBuffer for 2 3
Creating new MessageBuffer for 2 4
Creating new MessageBuffer for 2 5
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here

18
tests/quick/00.hello/ref/sparc/linux/simple-atomic-ruby/simout
View file

@ -5,18 +5,12 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 5 2009 07:34:00
M5 revision 8bea207e2193 6172 default qtip tip ruby_tests_refs.diff
M5 started May 5 2009 07:34:02
M5 executing on piton
command line: /n/piton/z/nate/build/xgem5/build/SPARC_SE/m5.fast -d /n/piton/z/nate/build/xgem5/build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic-ruby -re tests/run.py /n/piton/z/nate/build/xgem5/build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic-ruby
M5 compiled Jul 6 2009 11:07:18
M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
M5 started Jul 6 2009 11:11:24
M5 executing on maize
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic-ruby -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic-ruby
Global frequency set at 1000000000000 ticks per second
Ruby Timing Mode
Creating event queue...
Creating event queue done
Creating system...
Processors: 1
Creating system done
Ruby initialization complete
Debug: Adding to filter: 'q' (Queue)
info: Entering event queue @ 0. Starting simulation...
Hello World!Exiting @ tick 2701000 because target called exit()

5
tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
View file

@ -78,10 +78,9 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=RubyMemory
clock=1
config_file=
config_options=
config_file=build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing-ruby/ruby.config
debug=false
debug_file=
debug_file=ruby.debug
file=
latency=30000
latency_var=0

946
tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats
View file

File diff suppressed because it is too large Load diff

20
tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simerr
View file

@ -1,3 +1,23 @@
["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024"]
print config: 1
Creating new MessageBuffer for 0 0
Creating new MessageBuffer for 0 1
Creating new MessageBuffer for 0 2
Creating new MessageBuffer for 0 3
Creating new MessageBuffer for 0 4
Creating new MessageBuffer for 0 5
Creating new MessageBuffer for 1 0
Creating new MessageBuffer for 1 1
Creating new MessageBuffer for 1 2
Creating new MessageBuffer for 1 3
Creating new MessageBuffer for 1 4
Creating new MessageBuffer for 1 5
Creating new MessageBuffer for 2 0
Creating new MessageBuffer for 2 1
Creating new MessageBuffer for 2 2
Creating new MessageBuffer for 2 3
Creating new MessageBuffer for 2 4
Creating new MessageBuffer for 2 5
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here

18
tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout
View file

@ -5,18 +5,12 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 5 2009 07:34:00
M5 revision 8bea207e2193 6172 default qtip tip ruby_tests_refs.diff
M5 started May 5 2009 07:34:02
M5 executing on piton
command line: /n/piton/z/nate/build/xgem5/build/SPARC_SE/m5.fast -d /n/piton/z/nate/build/xgem5/build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py /n/piton/z/nate/build/xgem5/build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing-ruby
M5 compiled Jul 6 2009 11:07:18
M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
M5 started Jul 6 2009 11:11:35
M5 executing on maize
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing-ruby
Global frequency set at 1000000000000 ticks per second
Ruby Timing Mode
Creating event queue...
Creating event queue done
Creating system...
Processors: 1
Creating system done
Ruby initialization complete
Debug: Adding to filter: 'q' (Queue)
info: Entering event queue @ 0. Starting simulation...
Hello World!Exiting @ tick 20314000 because target called exit()

8
tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 11636 # Simulator instruction rate (inst/s)
host_mem_usage 201180 # Number of bytes of host memory used
host_seconds 0.46 # Real time elapsed on the host
host_tick_rate 44246862 # Simulator tick rate (ticks/s)
host_inst_rate 3344 # Simulator instruction rate (inst/s)
host_mem_usage 1362412 # Number of bytes of host memory used
host_seconds 1.60 # Real time elapsed on the host
host_tick_rate 12720005 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5340 # Number of instructions simulated
sim_seconds 0.000020 # Number of seconds simulated

5
tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/config.ini
View file

@ -81,10 +81,9 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=RubyMemory
clock=1
config_file=
config_options=
config_file=build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic-ruby/ruby.config
debug=false
debug_file=
debug_file=ruby.debug
file=
latency=30000
latency_var=0

819
tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/ruby.stats
View file

@ -1,258 +1,81 @@
================ Begin RubySystem Configuration Print ================
Ruby Configuration
------------------
protocol: MOSI_SMP_bcast
compiled_at: 22:56:05, May 4 2009
RUBY_DEBUG: false
hostname: piton
g_RANDOM_SEED: 1
g_DEADLOCK_THRESHOLD: 500000
RANDOMIZATION: false
g_SYNTHETIC_DRIVER: false
g_DETERMINISTIC_DRIVER: false
g_FILTERING_ENABLED: false
g_DISTRIBUTED_PERSISTENT_ENABLED: true
g_DYNAMIC_TIMEOUT_ENABLED: true
g_RETRY_THRESHOLD: 1
g_FIXED_TIMEOUT_LATENCY: 300
g_trace_warmup_length: 1000000
g_bash_bandwidth_adaptive_threshold: 0.75
g_tester_length: 0
g_synthetic_locks: 2048
g_deterministic_addrs: 1
g_SpecifiedGenerator: DetermInvGenerator
g_callback_counter: 0
g_NUM_COMPLETIONS_BEFORE_PASS: 0
g_NUM_SMT_THREADS: 1
g_think_time: 5
g_hold_time: 5
g_wait_time: 5
PROTOCOL_DEBUG_TRACE: true
DEBUG_FILTER_STRING: none
DEBUG_VERBOSITY_STRING: none
DEBUG_START_TIME: 0
DEBUG_OUTPUT_FILENAME: none
SIMICS_RUBY_MULTIPLIER: 4
OPAL_RUBY_MULTIPLIER: 1
TRANSACTION_TRACE_ENABLED: false
USER_MODE_DATA_ONLY: false
PROFILE_HOT_LINES: false
PROFILE_ALL_INSTRUCTIONS: false
PRINT_INSTRUCTION_TRACE: false
g_DEBUG_CYCLE: 0
BLOCK_STC: false
PERFECT_MEMORY_SYSTEM: false
PERFECT_MEMORY_SYSTEM_LATENCY: 0
DATA_BLOCK: false
REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH: false
L1_CACHE_ASSOC: 4
L1_CACHE_NUM_SETS_BITS: 8
L2_CACHE_ASSOC: 4
L2_CACHE_NUM_SETS_BITS: 16
g_MEMORY_SIZE_BYTES: 4294967296
g_DATA_BLOCK_BYTES: 64
g_PAGE_SIZE_BYTES: 4096
g_REPLACEMENT_POLICY: PSEDUO_LRU
g_NUM_PROCESSORS: 1
g_NUM_L2_BANKS: 1
g_NUM_MEMORIES: 1
g_PROCS_PER_CHIP: 1
g_NUM_CHIPS: 1
g_NUM_CHIP_BITS: 0
g_MEMORY_SIZE_BITS: 32
g_DATA_BLOCK_BITS: 6
g_PAGE_SIZE_BITS: 12
g_NUM_PROCESSORS_BITS: 0
g_PROCS_PER_CHIP_BITS: 0
g_NUM_L2_BANKS_BITS: 0
g_NUM_L2_BANKS_PER_CHIP_BITS: 0
g_NUM_L2_BANKS_PER_CHIP: 1
g_NUM_MEMORIES_BITS: 0
g_NUM_MEMORIES_PER_CHIP: 1
g_MEMORY_MODULE_BITS: 26
g_MEMORY_MODULE_BLOCKS: 67108864
MAP_L2BANKS_TO_LOWEST_BITS: false
DIRECTORY_CACHE_LATENCY: 6
NULL_LATENCY: 1
ISSUE_LATENCY: 2
CACHE_RESPONSE_LATENCY: 12
L2_RESPONSE_LATENCY: 6
L2_TAG_LATENCY: 6
L1_RESPONSE_LATENCY: 3
MEMORY_RESPONSE_LATENCY_MINUS_2: 158
DIRECTORY_LATENCY: 80
NETWORK_LINK_LATENCY: 1
COPY_HEAD_LATENCY: 4
ON_CHIP_LINK_LATENCY: 1
RECYCLE_LATENCY: 10
L2_RECYCLE_LATENCY: 5
TIMER_LATENCY: 10000
TBE_RESPONSE_LATENCY: 1
PERIODIC_TIMER_WAKEUPS: true
PROFILE_EXCEPTIONS: false
PROFILE_XACT: true
PROFILE_NONXACT: false
XACT_DEBUG: true
XACT_DEBUG_LEVEL: 1
XACT_MEMORY: false
XACT_ENABLE_TOURMALINE: false
XACT_NUM_CURRENT: 0
XACT_LAST_UPDATE: 0
XACT_ISOLATION_CHECK: false
PERFECT_FILTER: true
READ_WRITE_FILTER: Perfect_
PERFECT_VIRTUAL_FILTER: true
VIRTUAL_READ_WRITE_FILTER: Perfect_
PERFECT_SUMMARY_FILTER: true
SUMMARY_READ_WRITE_FILTER: Perfect_
XACT_EAGER_CD: true
XACT_LAZY_VM: false
XACT_CONFLICT_RES: BASE
XACT_VISUALIZER: false
XACT_COMMIT_TOKEN_LATENCY: 0
XACT_NO_BACKOFF: false
XACT_LOG_BUFFER_SIZE: 0
XACT_STORE_PREDICTOR_HISTORY: 256
XACT_STORE_PREDICTOR_ENTRIES: 256
XACT_STORE_PREDICTOR_THRESHOLD: 4
XACT_FIRST_ACCESS_COST: 0
XACT_FIRST_PAGE_ACCESS_COST: 0
ENABLE_MAGIC_WAITING: false
ENABLE_WATCHPOINT: false
XACT_ENABLE_VIRTUALIZATION_LOGTM_SE: false
ATMTP_ENABLED: false
ATMTP_ABORT_ON_NON_XACT_INST: false
ATMTP_ALLOW_SAVE_RESTORE_IN_XACT: false
ATMTP_XACT_MAX_STORES: 32
ATMTP_DEBUG_LEVEL: 0
L1_REQUEST_LATENCY: 2
L2_REQUEST_LATENCY: 4
SINGLE_ACCESS_L2_BANKS: true
SEQUENCER_TO_CONTROLLER_LATENCY: 4
L1CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
L2CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
DIRECTORY_TRANSITIONS_PER_RUBY_CYCLE: 32
g_SEQUENCER_OUTSTANDING_REQUESTS: 16
NUMBER_OF_TBES: 128
NUMBER_OF_L1_TBES: 32
NUMBER_OF_L2_TBES: 32
FINITE_BUFFERING: false
FINITE_BUFFER_SIZE: 3
PROCESSOR_BUFFER_SIZE: 10
PROTOCOL_BUFFER_SIZE: 32
TSO: false
g_NETWORK_TOPOLOGY: HIERARCHICAL_SWITCH
g_CACHE_DESIGN: NUCA
g_endpoint_bandwidth: 10000
g_adaptive_routing: true
NUMBER_OF_VIRTUAL_NETWORKS: 4
FAN_OUT_DEGREE: 4
g_PRINT_TOPOLOGY: true
XACT_LENGTH: 0
XACT_SIZE: 0
ABORT_RETRY_TIME: 0
g_GARNET_NETWORK: false
g_DETAIL_NETWORK: false
g_NETWORK_TESTING: false
g_FLIT_SIZE: 16
g_NUM_PIPE_STAGES: 4
g_VCS_PER_CLASS: 4
g_BUFFER_SIZE: 4
MEM_BUS_CYCLE_MULTIPLIER: 10
BANKS_PER_RANK: 8
RANKS_PER_DIMM: 2
DIMMS_PER_CHANNEL: 2
BANK_BIT_0: 8
RANK_BIT_0: 11
DIMM_BIT_0: 12
BANK_QUEUE_SIZE: 12
BANK_BUSY_TIME: 11
RANK_RANK_DELAY: 1
READ_WRITE_DELAY: 2
BASIC_BUS_BUSY_TIME: 2
MEM_CTL_LATENCY: 12
REFRESH_PERIOD: 1560
TFAW: 0
MEM_RANDOM_ARBITRATE: 0
MEM_FIXED_DELAY: 0
Chip Config
-----------
Total_Chips: 1
L1Cache_TBEs numberPerChip: 1
TBEs_per_TBETable: 128
L1Cache_L1IcacheMemory numberPerChip: 1
Cache config: L1Cache_0_L1I
cache_associativity: 4
num_cache_sets_bits: 8
num_cache_sets: 256
cache_set_size_bytes: 16384
cache_set_size_Kbytes: 16
cache_set_size_Mbytes: 0.015625
cache_size_bytes: 65536
cache_size_Kbytes: 64
cache_size_Mbytes: 0.0625
L1Cache_L1DcacheMemory numberPerChip: 1
Cache config: L1Cache_0_L1D
cache_associativity: 4
num_cache_sets_bits: 8
num_cache_sets: 256
cache_set_size_bytes: 16384
cache_set_size_Kbytes: 16
cache_set_size_Mbytes: 0.015625
cache_size_bytes: 65536
cache_size_Kbytes: 64
cache_size_Mbytes: 0.0625
L1Cache_L2cacheMemory numberPerChip: 1
Cache config: L1Cache_0_L2
cache_associativity: 4
num_cache_sets_bits: 16
num_cache_sets: 65536
cache_set_size_bytes: 4194304
cache_set_size_Kbytes: 4096
cache_set_size_Mbytes: 4
cache_size_bytes: 16777216
cache_size_Kbytes: 16384
cache_size_Mbytes: 16
L1Cache_mandatoryQueue numberPerChip: 1
L1Cache_sequencer numberPerChip: 1
sequencer: Sequencer - SC
RubySystem config:
random_seed: 30545
randomization: 0
tech_nm: 45
freq_mhz: 3000
block_size_bytes: 64
block_size_bits: 6
memory_size_bytes: 1073741824
memory_size_bits: 30
DMA_Controller config: DMAController_0
version: 0
buffer_size: 32
dma_sequencer: DMASequencer_0
number_of_TBEs: 128
transitions_per_cycle: 32
Directory_Controller config: DirectoryController_0
version: 0
buffer_size: 32
directory_latency: 6
directory_name: DirectoryMemory_0
memory_controller_name: MemoryControl_0
memory_latency: 158
number_of_TBEs: 128
recycle_latency: 10
to_mem_ctrl_latency: 1
transitions_per_cycle: 32
L1Cache_Controller config: L1CacheController_0
version: 0
buffer_size: 32
cache: l1u_0
cache_response_latency: 12
issue_latency: 2
number_of_TBEs: 128
sequencer: Sequencer_0
transitions_per_cycle: 32
Cache config: l1u_0
controller: L1CacheController_0
cache_associativity: 8
num_cache_sets_bits: 2
num_cache_sets: 4
cache_set_size_bytes: 256
cache_set_size_Kbytes: 0.25
cache_set_size_Mbytes: 0.000244141
cache_size_bytes: 2048
cache_size_Kbytes: 2
cache_size_Mbytes: 0.00195312
DirectoryMemory Global Config:
number of directory memories: 1
total memory size bytes: 1073741824
total memory size bits: 30
DirectoryMemory module config: DirectoryMemory_0
controller: DirectoryController_0
version: 0
memory_bits: 30
memory_size_bytes: 1073741824
memory_size_Kbytes: 1.04858e+06
memory_size_Mbytes: 1024
memory_size_Gbytes: 1
Seqeuncer config: Sequencer_0
controller: L1CacheController_0
version: 0
max_outstanding_requests: 16
L1Cache_storeBuffer numberPerChip: 1
Store buffer entries: 128 (Only valid if TSO is enabled)
Directory_directory numberPerChip: 1
Memory config:
memory_bits: 32
memory_size_bytes: 4294967296
memory_size_Kbytes: 4.1943e+06
memory_size_Mbytes: 4096
memory_size_Gbytes: 4
module_bits: 26
module_size_lines: 67108864
module_size_bytes: 4294967296
module_size_Kbytes: 4.1943e+06
module_size_Mbytes: 4096
deadlock_threshold: 500000
Network Configuration
---------------------
network: SIMPLE_NETWORK
topology: HIERARCHICAL_SWITCH
topology: theTopology
virtual_net_0: active, ordered
virtual_net_1: active, unordered
virtual_net_2: inactive
virtual_net_1: active, ordered
virtual_net_2: active, ordered
virtual_net_3: inactive
virtual_net_4: active, ordered
virtual_net_5: active, ordered
--- Begin Topology Print ---
@ -260,10 +83,16 @@ Topology print ONLY indicates the _NETWORK_ latency between two machines
It does NOT include the latency within the machines
L1Cache-0 Network Latencies
L1Cache-0 -> Directory-0 net_lat: 5
L1Cache-0 -> Directory-0 net_lat: 7
L1Cache-0 -> DMA-0 net_lat: 7
Directory-0 Network Latencies
Directory-0 -> L1Cache-0 net_lat: 5
Directory-0 -> L1Cache-0 net_lat: 7
Directory-0 -> DMA-0 net_lat: 7
DMA-0 Network Latencies
DMA-0 -> L1Cache-0 net_lat: 7
DMA-0 -> Directory-0 net_lat: 7
--- End Topology Print ---
@ -274,27 +103,27 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
Real time: May/05/2009 07:34:04
Real time: Jul/06/2009 11:11:42
Profiler Stats
--------------
Elapsed_time_in_seconds: 1
Elapsed_time_in_minutes: 0.0166667
Elapsed_time_in_hours: 0.000277778
Elapsed_time_in_days: 1.15741e-05
Elapsed_time_in_seconds: 0
Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
Virtual_time_in_seconds: 0.24
Virtual_time_in_minutes: 0.004
Virtual_time_in_hours: 6.66667e-05
Virtual_time_in_days: 6.66667e-05
Virtual_time_in_seconds: 0.28
Virtual_time_in_minutes: 0.00466667
Virtual_time_in_hours: 7.77778e-05
Virtual_time_in_days: 7.77778e-05
Ruby_current_time: 5491501
Ruby_start_time: 1
Ruby_cycles: 5491500
mbytes_resident: 34.8438
mbytes_total: 196.57
resident_ratio: 0.177278
mbytes_resident: 144.855
mbytes_total: 1330.54
resident_ratio: 0.108873
Total_misses: 0
total_misses: 0 [ 0 ]
@ -302,7 +131,7 @@ user_misses: 0 [ 0 ]
supervisor_misses: 0 [ 0 ]
instruction_executed: 1 [ 1 ]
cycles_executed: 1 [ 1 ]
ruby_cycles_executed: 5491501 [ 5491501 ]
cycles_per_instruction: 5.4915e+06 [ 5.4915e+06 ]
misses_per_thousand_instructions: 0 [ 0 ]
@ -352,6 +181,7 @@ L2_cache cache stats:
Busy Controller Counts:
L1Cache-0:0
Directory-0:0
DMA-0:0
Busy Bank Count:0
@ -390,406 +220,163 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard dev
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Resource Usage
--------------
page_size: 4096
user_time: 0
system_time: 0
page_reclaims: 9117
page_reclaims: 37781
page_faults: 0
swaps: 0
block_inputs: 0
block_outputs: 56
MessageBuffer: [Chip 0 0, L1Cache, mandatoryQueue_in] stats - msgs:0 full:0
block_outputs: 40
Network Stats
-------------
switch_0_inlinks: 1
switch_0_outlinks: 1
switch_0_inlinks: 2
switch_0_outlinks: 2
links_utilized_percent_switch_0: 0
links_utilized_percent_switch_0_link_0: 0 bw: 10000 base_latency: 1
links_utilized_percent_switch_0_link_0: 0 bw: 640000 base_latency: 1
links_utilized_percent_switch_0_link_1: 0 bw: 160000 base_latency: 1
switch_1_inlinks: 1
switch_1_outlinks: 1
switch_1_inlinks: 2
switch_1_outlinks: 2
links_utilized_percent_switch_1: 0
links_utilized_percent_switch_1_link_0: 0 bw: 10000 base_latency: 1
links_utilized_percent_switch_1_link_0: 0 bw: 640000 base_latency: 1
links_utilized_percent_switch_1_link_1: 0 bw: 160000 base_latency: 1
switch_2_inlinks: 2
switch_2_outlinks: 2
links_utilized_percent_switch_2: 0
links_utilized_percent_switch_2_link_0: 0 bw: 10000 base_latency: 1
links_utilized_percent_switch_2_link_1: 0 bw: 10000 base_latency: 1
links_utilized_percent_switch_2_link_0: 0 bw: 640000 base_latency: 1
links_utilized_percent_switch_2_link_1: 0 bw: 160000 base_latency: 1
switch_3_inlinks: 3
switch_3_outlinks: 3
links_utilized_percent_switch_3: 0
links_utilized_percent_switch_3_link_0: 0 bw: 160000 base_latency: 1
links_utilized_percent_switch_3_link_1: 0 bw: 160000 base_latency: 1
links_utilized_percent_switch_3_link_2: 0 bw: 160000 base_latency: 1
Chip Stats
----------
--- DMA ---
- Event Counts -
ReadRequest 0
WriteRequest 0
Data 0
Ack 0
- Transitions -
READY ReadRequest 0 <--
READY WriteRequest 0 <--
BUSY_RD Data 0 <--
BUSY_WR Ack 0 <--
--- Directory ---
- Event Counts -
GETX 0
GETS 0
PUTX 0
PUTX_NotOwner 0
DMA_READ 0
DMA_WRITE 0
Memory_Data 0
Memory_Ack 0
- Transitions -
I GETX 0 <--
I PUTX_NotOwner 0 <--
I DMA_READ 0 <--
I DMA_WRITE 0 <--
M GETX 0 <--
M PUTX 0 <--
M PUTX_NotOwner 0 <--
M DMA_READ 0 <--
M DMA_WRITE 0 <--
M_DRD GETX 0 <--
M_DRD PUTX 0 <--
M_DWR GETX 0 <--
M_DWR PUTX 0 <--
M_DWRI Memory_Ack 0 <--
IM GETX 0 <--
IM GETS 0 <--
IM PUTX 0 <--
IM PUTX_NotOwner 0 <--
IM DMA_READ 0 <--
IM DMA_WRITE 0 <--
IM Memory_Data 0 <--
MI GETX 0 <--
MI GETS 0 <--
MI PUTX 0 <--
MI PUTX_NotOwner 0 <--
MI DMA_READ 0 <--
MI DMA_WRITE 0 <--
MI Memory_Ack 0 <--
ID GETX 0 <--
ID GETS 0 <--
ID PUTX 0 <--
ID PUTX_NotOwner 0 <--
ID DMA_READ 0 <--
ID DMA_WRITE 0 <--
ID Memory_Data 0 <--
ID_W GETX 0 <--
ID_W GETS 0 <--
ID_W PUTX 0 <--
ID_W PUTX_NotOwner 0 <--
ID_W DMA_READ 0 <--
ID_W DMA_WRITE 0 <--
ID_W Memory_Ack 0 <--
--- L1Cache ---
- Event Counts -
Load 0
Ifetch 0
Store 0
L1_to_L2 0
L2_to_L1D 0
L2_to_L1I 0
L2_Replacement 0
Own_GETS 0
Own_GET_INSTR 0
Own_GETX 0
Own_PUTX 0
Other_GETS 0
Other_GET_INSTR 0
Other_GETX 0
Other_PUTX 0
Data 0
Fwd_GETX 0
Inv 0
Replacement 0
Writeback_Ack 0
Writeback_Nack 0
- Transitions -
NP Load 0 <--
NP Ifetch 0 <--
NP Store 0 <--
NP Other_GETS 0 <--
NP Other_GET_INSTR 0 <--
NP Other_GETX 0 <--
NP Other_PUTX 0 <--
I Load 0 <--
I Ifetch 0 <--
I Store 0 <--
I L1_to_L2 0 <--
I L2_to_L1D 0 <--
I L2_to_L1I 0 <--
I L2_Replacement 0 <--
I Other_GETS 0 <--
I Other_GET_INSTR 0 <--
I Other_GETX 0 <--
I Other_PUTX 0 <--
I Inv 0 <--
I Replacement 0 <--
S Load 0 <--
S Ifetch 0 <--
S Store 0 <--
S L1_to_L2 0 <--
S L2_to_L1D 0 <--
S L2_to_L1I 0 <--
S L2_Replacement 0 <--
S Other_GETS 0 <--
S Other_GET_INSTR 0 <--
S Other_GETX 0 <--
S Other_PUTX 0 <--
O Load 0 <--
O Ifetch 0 <--
O Store 0 <--
O L1_to_L2 0 <--
O L2_to_L1D 0 <--
O L2_to_L1I 0 <--
O L2_Replacement 0 <--
O Other_GETS 0 <--
O Other_GET_INSTR 0 <--
O Other_GETX 0 <--
O Other_PUTX 0 <--
II Writeback_Nack 0 <--
M Load 0 <--
M Ifetch 0 <--
M Store 0 <--
M L1_to_L2 0 <--
M L2_to_L1D 0 <--
M L2_to_L1I 0 <--
M L2_Replacement 0 <--
M Other_GETS 0 <--
M Other_GET_INSTR 0 <--
M Other_GETX 0 <--
M Other_PUTX 0 <--
M Fwd_GETX 0 <--
M Inv 0 <--
M Replacement 0 <--
IS_AD Load 0 <--
IS_AD Ifetch 0 <--
IS_AD Store 0 <--
IS_AD L1_to_L2 0 <--
IS_AD L2_to_L1D 0 <--
IS_AD L2_to_L1I 0 <--
IS_AD L2_Replacement 0 <--
IS_AD Own_GETS 0 <--
IS_AD Own_GET_INSTR 0 <--
IS_AD Other_GETS 0 <--
IS_AD Other_GET_INSTR 0 <--
IS_AD Other_GETX 0 <--
IS_AD Other_PUTX 0 <--
IS_AD Data 0 <--
MI Fwd_GETX 0 <--
MI Inv 0 <--
MI Writeback_Ack 0 <--
IM_AD Load 0 <--
IM_AD Ifetch 0 <--
IM_AD Store 0 <--
IM_AD L1_to_L2 0 <--
IM_AD L2_to_L1D 0 <--
IM_AD L2_to_L1I 0 <--
IM_AD L2_Replacement 0 <--
IM_AD Own_GETX 0 <--
IM_AD Other_GETS 0 <--
IM_AD Other_GET_INSTR 0 <--
IM_AD Other_GETX 0 <--
IM_AD Other_PUTX 0 <--
IM_AD Data 0 <--
IS Data 0 <--
SM_AD Load 0 <--
SM_AD Ifetch 0 <--
SM_AD Store 0 <--
SM_AD L1_to_L2 0 <--
SM_AD L2_to_L1D 0 <--
SM_AD L2_to_L1I 0 <--
SM_AD L2_Replacement 0 <--
SM_AD Own_GETX 0 <--
SM_AD Other_GETS 0 <--
SM_AD Other_GET_INSTR 0 <--
SM_AD Other_GETX 0 <--
SM_AD Other_PUTX 0 <--
SM_AD Data 0 <--
OM_A Load 0 <--
OM_A Ifetch 0 <--
OM_A Store 0 <--
OM_A L1_to_L2 0 <--
OM_A L2_to_L1D 0 <--
OM_A L2_to_L1I 0 <--
OM_A L2_Replacement 0 <--
OM_A Own_GETX 0 <--
OM_A Other_GETS 0 <--
OM_A Other_GET_INSTR 0 <--
OM_A Other_GETX 0 <--
OM_A Other_PUTX 0 <--
OM_A Data 0 <--
IS_A Load 0 <--
IS_A Ifetch 0 <--
IS_A Store 0 <--
IS_A L1_to_L2 0 <--
IS_A L2_to_L1D 0 <--
IS_A L2_to_L1I 0 <--
IS_A L2_Replacement 0 <--
IS_A Own_GETS 0 <--
IS_A Own_GET_INSTR 0 <--
IS_A Other_GETS 0 <--
IS_A Other_GET_INSTR 0 <--
IS_A Other_GETX 0 <--
IS_A Other_PUTX 0 <--
IM_A Load 0 <--
IM_A Ifetch 0 <--
IM_A Store 0 <--
IM_A L1_to_L2 0 <--
IM_A L2_to_L1D 0 <--
IM_A L2_to_L1I 0 <--
IM_A L2_Replacement 0 <--
IM_A Own_GETX 0 <--
IM_A Other_GETS 0 <--
IM_A Other_GET_INSTR 0 <--
IM_A Other_GETX 0 <--
IM_A Other_PUTX 0 <--
SM_A Load 0 <--
SM_A Ifetch 0 <--
SM_A Store 0 <--
SM_A L1_to_L2 0 <--
SM_A L2_to_L1D 0 <--
SM_A L2_to_L1I 0 <--
SM_A L2_Replacement 0 <--
SM_A Own_GETX 0 <--
SM_A Other_GETS 0 <--
SM_A Other_GET_INSTR 0 <--
SM_A Other_GETX 0 <--
SM_A Other_PUTX 0 <--
MI_A Load 0 <--
MI_A Ifetch 0 <--
MI_A Store 0 <--
MI_A L1_to_L2 0 <--
MI_A L2_to_L1D 0 <--
MI_A L2_to_L1I 0 <--
MI_A L2_Replacement 0 <--
MI_A Own_PUTX 0 <--
MI_A Other_GETS 0 <--
MI_A Other_GET_INSTR 0 <--
MI_A Other_GETX 0 <--
MI_A Other_PUTX 0 <--
OI_A Load 0 <--
OI_A Ifetch 0 <--
OI_A Store 0 <--
OI_A L1_to_L2 0 <--
OI_A L2_to_L1D 0 <--
OI_A L2_to_L1I 0 <--
OI_A L2_Replacement 0 <--
OI_A Own_PUTX 0 <--
OI_A Other_GETS 0 <--
OI_A Other_GET_INSTR 0 <--
OI_A Other_GETX 0 <--
OI_A Other_PUTX 0 <--
II_A Load 0 <--
II_A Ifetch 0 <--
II_A Store 0 <--
II_A L1_to_L2 0 <--
II_A L2_to_L1D 0 <--
II_A L2_to_L1I 0 <--
II_A L2_Replacement 0 <--
II_A Own_PUTX 0 <--
II_A Other_GETS 0 <--
II_A Other_GET_INSTR 0 <--
II_A Other_GETX 0 <--
II_A Other_PUTX 0 <--
IS_D Load 0 <--
IS_D Ifetch 0 <--
IS_D Store 0 <--
IS_D L1_to_L2 0 <--
IS_D L2_to_L1D 0 <--
IS_D L2_to_L1I 0 <--
IS_D L2_Replacement 0 <--
IS_D Other_GETS 0 <--
IS_D Other_GET_INSTR 0 <--
IS_D Other_GETX 0 <--
IS_D Other_PUTX 0 <--
IS_D Data 0 <--
IS_D_I Load 0 <--
IS_D_I Ifetch 0 <--
IS_D_I Store 0 <--
IS_D_I L1_to_L2 0 <--
IS_D_I L2_to_L1D 0 <--
IS_D_I L2_to_L1I 0 <--
IS_D_I L2_Replacement 0 <--
IS_D_I Other_GETS 0 <--
IS_D_I Other_GET_INSTR 0 <--
IS_D_I Other_GETX 0 <--
IS_D_I Other_PUTX 0 <--
IS_D_I Data 0 <--
IM_D Load 0 <--
IM_D Ifetch 0 <--
IM_D Store 0 <--
IM_D L1_to_L2 0 <--
IM_D L2_to_L1D 0 <--
IM_D L2_to_L1I 0 <--
IM_D L2_Replacement 0 <--
IM_D Other_GETS 0 <--
IM_D Other_GET_INSTR 0 <--
IM_D Other_GETX 0 <--
IM_D Other_PUTX 0 <--
IM_D Data 0 <--
IM_D_O Load 0 <--
IM_D_O Ifetch 0 <--
IM_D_O Store 0 <--
IM_D_O L1_to_L2 0 <--
IM_D_O L2_to_L1D 0 <--
IM_D_O L2_to_L1I 0 <--
IM_D_O L2_Replacement 0 <--
IM_D_O Other_GETS 0 <--
IM_D_O Other_GET_INSTR 0 <--
IM_D_O Other_GETX 0 <--
IM_D_O Other_PUTX 0 <--
IM_D_O Data 0 <--
IM_D_I Load 0 <--
IM_D_I Ifetch 0 <--
IM_D_I Store 0 <--
IM_D_I L1_to_L2 0 <--
IM_D_I L2_to_L1D 0 <--
IM_D_I L2_to_L1I 0 <--
IM_D_I L2_Replacement 0 <--
IM_D_I Other_GETS 0 <--
IM_D_I Other_GET_INSTR 0 <--
IM_D_I Other_GETX 0 <--
IM_D_I Other_PUTX 0 <--
IM_D_I Data 0 <--
IM_D_OI Load 0 <--
IM_D_OI Ifetch 0 <--
IM_D_OI Store 0 <--
IM_D_OI L1_to_L2 0 <--
IM_D_OI L2_to_L1D 0 <--
IM_D_OI L2_to_L1I 0 <--
IM_D_OI L2_Replacement 0 <--
IM_D_OI Other_GETS 0 <--
IM_D_OI Other_GET_INSTR 0 <--
IM_D_OI Other_GETX 0 <--
IM_D_OI Other_PUTX 0 <--
IM_D_OI Data 0 <--
SM_D Load 0 <--
SM_D Ifetch 0 <--
SM_D Store 0 <--
SM_D L1_to_L2 0 <--
SM_D L2_to_L1D 0 <--
SM_D L2_to_L1I 0 <--
SM_D L2_Replacement 0 <--
SM_D Other_GETS 0 <--
SM_D Other_GET_INSTR 0 <--
SM_D Other_GETX 0 <--
SM_D Other_PUTX 0 <--
SM_D Data 0 <--
SM_D_O Load 0 <--
SM_D_O Ifetch 0 <--
SM_D_O Store 0 <--
SM_D_O L1_to_L2 0 <--
SM_D_O L2_to_L1D 0 <--
SM_D_O L2_to_L1I 0 <--
SM_D_O L2_Replacement 0 <--
SM_D_O Other_GETS 0 <--
SM_D_O Other_GET_INSTR 0 <--
SM_D_O Other_GETX 0 <--
SM_D_O Other_PUTX 0 <--
SM_D_O Data 0 <--
--- Directory ---
- Event Counts -
OtherAddress 0
GETS 0
GET_INSTR 0
GETX 0
PUTX_Owner 0
PUTX_NotOwner 0
- Transitions -
C OtherAddress 0 <--
C GETS 0 <--
C GET_INSTR 0 <--
C GETX 0 <--
I GETS 0 <--
I GET_INSTR 0 <--
I GETX 0 <--
I PUTX_NotOwner 0 <--
S GETS 0 <--
S GET_INSTR 0 <--
S GETX 0 <--
S PUTX_NotOwner 0 <--
SS GETS 0 <--
SS GET_INSTR 0 <--
SS GETX 0 <--
SS PUTX_NotOwner 0 <--
OS GETS 0 <--
OS GET_INSTR 0 <--
OS GETX 0 <--
OS PUTX_Owner 0 <--
OS PUTX_NotOwner 0 <--
OSS GETS 0 <--
OSS GET_INSTR 0 <--
OSS GETX 0 <--
OSS PUTX_Owner 0 <--
OSS PUTX_NotOwner 0 <--
M GETS 0 <--
M GET_INSTR 0 <--
M GETX 0 <--
M PUTX_Owner 0 <--
M PUTX_NotOwner 0 <--
IM Data 0 <--

20
tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/simerr
View file

@ -1,3 +1,23 @@
["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024"]
print config: 1
Creating new MessageBuffer for 0 0
Creating new MessageBuffer for 0 1
Creating new MessageBuffer for 0 2
Creating new MessageBuffer for 0 3
Creating new MessageBuffer for 0 4
Creating new MessageBuffer for 0 5
Creating new MessageBuffer for 1 0
Creating new MessageBuffer for 1 1
Creating new MessageBuffer for 1 2
Creating new MessageBuffer for 1 3
Creating new MessageBuffer for 1 4
Creating new MessageBuffer for 1 5
Creating new MessageBuffer for 2 0
Creating new MessageBuffer for 2 1
Creating new MessageBuffer for 2 2
Creating new MessageBuffer for 2 3
Creating new MessageBuffer for 2 4
Creating new MessageBuffer for 2 5
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
warn: instruction 'fnstcw_Mw' unimplemented

18
tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/simout
View file

@ -5,19 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 5 2009 07:34:01
M5 revision 8bea207e2193 6172 default qtip tip ruby_tests_refs.diff
M5 started May 5 2009 07:34:03
M5 executing on piton
command line: /n/piton/z/nate/build/xgem5/build/X86_SE/m5.fast -d /n/piton/z/nate/build/xgem5/build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic-ruby -re tests/run.py /n/piton/z/nate/build/xgem5/build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic-ruby
M5 compiled Jul 6 2009 11:09:41
M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
M5 started Jul 6 2009 11:11:41
M5 executing on maize
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic-ruby -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic-ruby
Global frequency set at 1000000000000 ticks per second
Ruby Timing Mode
Creating event queue...
Creating event queue done
Creating system...
Processors: 1
Creating system done
Ruby initialization complete
Debug: Adding to filter: 'q' (Queue)
info: Entering event queue @ 0. Starting simulation...
Hello world!
Exiting @ tick 5491500 because target called exit()

6
tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 67050 # Simulator instruction rate (inst/s)
host_mem_usage 201292 # Number of bytes of host memory used
host_inst_rate 70231 # Simulator instruction rate (inst/s)
host_mem_usage 1362472 # Number of bytes of host memory used
host_seconds 0.14 # Real time elapsed on the host
host_tick_rate 38741287 # Simulator tick rate (ticks/s)
host_tick_rate 40570791 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 9494 # Number of instructions simulated
sim_seconds 0.000005 # Number of seconds simulated

5
tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
View file

@ -78,10 +78,9 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=RubyMemory
clock=1
config_file=
config_options=
config_file=build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby/ruby.config
debug=false
debug_file=
debug_file=ruby.debug
file=
latency=30000
latency_var=0

946
tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
View file

File diff suppressed because it is too large Load diff

20
tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simerr
View file

@ -1,3 +1,23 @@
["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024"]
print config: 1
Creating new MessageBuffer for 0 0
Creating new MessageBuffer for 0 1
Creating new MessageBuffer for 0 2
Creating new MessageBuffer for 0 3
Creating new MessageBuffer for 0 4
Creating new MessageBuffer for 0 5
Creating new MessageBuffer for 1 0
Creating new MessageBuffer for 1 1
Creating new MessageBuffer for 1 2
Creating new MessageBuffer for 1 3
Creating new MessageBuffer for 1 4
Creating new MessageBuffer for 1 5
Creating new MessageBuffer for 2 0
Creating new MessageBuffer for 2 1
Creating new MessageBuffer for 2 2
Creating new MessageBuffer for 2 3
Creating new MessageBuffer for 2 4
Creating new MessageBuffer for 2 5
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
warn: instruction 'fnstcw_Mw' unimplemented

18
tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout
View file

@ -5,19 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 5 2009 07:34:01
M5 revision 8bea207e2193 6172 default qtip tip ruby_tests_refs.diff
M5 started May 5 2009 07:34:03
M5 executing on piton
command line: /n/piton/z/nate/build/xgem5/build/X86_SE/m5.fast -d /n/piton/z/nate/build/xgem5/build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py /n/piton/z/nate/build/xgem5/build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby
M5 compiled Jul 6 2009 11:09:41
M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
M5 started Jul 6 2009 11:11:43
M5 executing on maize
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby
Global frequency set at 1000000000000 ticks per second
Ruby Timing Mode
Creating event queue...
Creating event queue done
Creating system...
Processors: 1
Creating system done
Ruby initialization complete
Debug: Adding to filter: 'q' (Queue)
info: Entering event queue @ 0. Starting simulation...
Hello world!
Exiting @ tick 26617000 because target called exit()

8
tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 19555 # Simulator instruction rate (inst/s)
host_mem_usage 201376 # Number of bytes of host memory used
host_seconds 0.49 # Real time elapsed on the host
host_tick_rate 54805154 # Simulator tick rate (ticks/s)
host_inst_rate 12919 # Simulator instruction rate (inst/s)
host_mem_usage 1362572 # Number of bytes of host memory used
host_seconds 0.74 # Real time elapsed on the host
host_tick_rate 36211191 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 9494 # Number of instructions simulated
sim_seconds 0.000027 # Number of seconds simulated

38
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp-ruby/simerr
View file

@ -1,3 +1,41 @@
["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "4", "-m", "1", "-s", "1024"]
print config: 1
Creating new MessageBuffer for 0 0
Creating new MessageBuffer for 0 1
Creating new MessageBuffer for 0 2
Creating new MessageBuffer for 0 3
Creating new MessageBuffer for 0 4
Creating new MessageBuffer for 0 5
Creating new MessageBuffer for 1 0
Creating new MessageBuffer for 1 1
Creating new MessageBuffer for 1 2
Creating new MessageBuffer for 1 3
Creating new MessageBuffer for 1 4
Creating new MessageBuffer for 1 5
Creating new MessageBuffer for 2 0
Creating new MessageBuffer for 2 1
Creating new MessageBuffer for 2 2
Creating new MessageBuffer for 2 3
Creating new MessageBuffer for 2 4
Creating new MessageBuffer for 2 5
Creating new MessageBuffer for 3 0
Creating new MessageBuffer for 3 1
Creating new MessageBuffer for 3 2
Creating new MessageBuffer for 3 3
Creating new MessageBuffer for 3 4
Creating new MessageBuffer for 3 5
Creating new MessageBuffer for 4 0
Creating new MessageBuffer for 4 1
Creating new MessageBuffer for 4 2
Creating new MessageBuffer for 4 3
Creating new MessageBuffer for 4 4
Creating new MessageBuffer for 4 5
Creating new MessageBuffer for 5 0
Creating new MessageBuffer for 5 1
Creating new MessageBuffer for 5 2
Creating new MessageBuffer for 5 3
Creating new MessageBuffer for 5 4
Creating new MessageBuffer for 5 5
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here

18
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp-ruby/simout
View file

@ -5,19 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 5 2009 07:34:00
M5 revision 8bea207e2193 6172 default qtip tip ruby_tests_refs.diff
M5 started May 5 2009 07:34:02
M5 executing on piton
command line: /n/piton/z/nate/build/xgem5/build/SPARC_SE/m5.fast -d /n/piton/z/nate/build/xgem5/build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp-ruby -re tests/run.py /n/piton/z/nate/build/xgem5/build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp-ruby
M5 compiled Jul 6 2009 11:07:18
M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
M5 started Jul 6 2009 11:11:25
M5 executing on maize
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp-ruby -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp-ruby
Global frequency set at 1000000000000 ticks per second
Ruby Timing Mode
Creating event queue...
Creating event queue done
Creating system...
Processors: 4
Creating system done
Ruby initialization complete
Debug: Adding to filter: 'q' (Queue)
info: Entering event queue @ 0. Starting simulation...
Init done
[Iteration 1, Thread 1] Got lock

8
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp-ruby/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 286405 # Simulator instruction rate (inst/s)
host_mem_usage 257880 # Number of bytes of host memory used
host_seconds 2.37 # Real time elapsed on the host
host_tick_rate 37086106 # Simulator tick rate (ticks/s)
host_inst_rate 38506 # Simulator instruction rate (inst/s)
host_mem_usage 1363292 # Number of bytes of host memory used
host_seconds 17.59 # Real time elapsed on the host
host_tick_rate 4986293 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 677340 # Number of instructions simulated
sim_seconds 0.000088 # Number of seconds simulated

5
tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
View file

@ -152,10 +152,9 @@ port=system.cpu0.test system.cpu1.test system.cpu2.test system.cpu3.test system.
[system.physmem]
type=RubyMemory
clock=1
config_file=
config_options=
config_file=build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby/ruby.config
debug=false
debug_file=
debug_file=ruby.debug
file=
latency=30000
latency_var=0

2023
tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats
View file

File diff suppressed because it is too large Load diff

208
tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr
View file

@ -1,74 +1,136 @@
system.cpu7: completed 10000 read accesses @483405
system.cpu1: completed 10000 read accesses @489648
system.cpu2: completed 10000 read accesses @489706
system.cpu5: completed 10000 read accesses @490354
system.cpu0: completed 10000 read accesses @492776
system.cpu4: completed 10000 read accesses @495396
system.cpu6: completed 10000 read accesses @497104
system.cpu3: completed 10000 read accesses @497952
system.cpu7: completed 20000 read accesses @923382
system.cpu5: completed 20000 read accesses @926026
system.cpu1: completed 20000 read accesses @927265
system.cpu2: completed 20000 read accesses @930725
system.cpu3: completed 20000 read accesses @933398
system.cpu6: completed 20000 read accesses @936538
system.cpu0: completed 20000 read accesses @938376
system.cpu4: completed 20000 read accesses @941944
system.cpu5: completed 30000 read accesses @1362075
system.cpu1: completed 30000 read accesses @1364620
system.cpu7: completed 30000 read accesses @1365206
system.cpu2: completed 30000 read accesses @1372346
system.cpu3: completed 30000 read accesses @1372730
system.cpu6: completed 30000 read accesses @1377457
system.cpu0: completed 30000 read accesses @1377608
system.cpu4: completed 30000 read accesses @1384598
system.cpu7: completed 40000 read accesses @1798226
system.cpu1: completed 40000 read accesses @1802550
system.cpu5: completed 40000 read accesses @1803508
system.cpu2: completed 40000 read accesses @1813044
system.cpu0: completed 40000 read accesses @1813249
system.cpu6: completed 40000 read accesses @1814460
system.cpu3: completed 40000 read accesses @1816124
system.cpu4: completed 40000 read accesses @1829214
system.cpu7: completed 50000 read accesses @2240501
system.cpu0: completed 50000 read accesses @2243543
system.cpu1: completed 50000 read accesses @2245806
system.cpu5: completed 50000 read accesses @2246126
system.cpu2: completed 50000 read accesses @2254021
system.cpu3: completed 50000 read accesses @2256564
system.cpu6: completed 50000 read accesses @2258894
system.cpu4: completed 50000 read accesses @2271354
system.cpu7: completed 60000 read accesses @2684820
system.cpu5: completed 60000 read accesses @2685946
system.cpu0: completed 60000 read accesses @2687254
system.cpu1: completed 60000 read accesses @2688183
system.cpu6: completed 60000 read accesses @2690040
system.cpu2: completed 60000 read accesses @2690996
system.cpu3: completed 60000 read accesses @2703034
system.cpu4: completed 60000 read accesses @2716020
system.cpu7: completed 70000 read accesses @3125991
system.cpu0: completed 70000 read accesses @3129042
system.cpu1: completed 70000 read accesses @3129110
system.cpu6: completed 70000 read accesses @3130362
system.cpu5: completed 70000 read accesses @3131396
system.cpu2: completed 70000 read accesses @3139286
system.cpu3: completed 70000 read accesses @3141858
system.cpu4: completed 70000 read accesses @3162690
system.cpu0: completed 80000 read accesses @3563564
system.cpu1: completed 80000 read accesses @3566188
system.cpu7: completed 80000 read accesses @3566291
system.cpu6: completed 80000 read accesses @3571624
system.cpu5: completed 80000 read accesses @3574146
system.cpu3: completed 80000 read accesses @3580572
system.cpu2: completed 80000 read accesses @3586246
system.cpu4: completed 80000 read accesses @3599364
system.cpu0: completed 90000 read accesses @4000938
system.cpu7: completed 90000 read accesses @4005441
system.cpu1: completed 90000 read accesses @4006993
system.cpu5: completed 90000 read accesses @4009374
system.cpu6: completed 90000 read accesses @4017392
system.cpu3: completed 90000 read accesses @4018754
system.cpu2: completed 90000 read accesses @4031534
system.cpu4: completed 90000 read accesses @4042150
system.cpu1: completed 100000 read accesses @4446776
["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "8", "-m", "1", "-s", "1024"]
print config: 1
Creating new MessageBuffer for 0 0
Creating new MessageBuffer for 0 1
Creating new MessageBuffer for 0 2
Creating new MessageBuffer for 0 3
Creating new MessageBuffer for 0 4
Creating new MessageBuffer for 0 5
Creating new MessageBuffer for 1 0
Creating new MessageBuffer for 1 1
Creating new MessageBuffer for 1 2
Creating new MessageBuffer for 1 3
Creating new MessageBuffer for 1 4
Creating new MessageBuffer for 1 5
Creating new MessageBuffer for 2 0
Creating new MessageBuffer for 2 1
Creating new MessageBuffer for 2 2
Creating new MessageBuffer for 2 3
Creating new MessageBuffer for 2 4
Creating new MessageBuffer for 2 5
Creating new MessageBuffer for 3 0
Creating new MessageBuffer for 3 1
Creating new MessageBuffer for 3 2
Creating new MessageBuffer for 3 3
Creating new MessageBuffer for 3 4
Creating new MessageBuffer for 3 5
Creating new MessageBuffer for 4 0
Creating new MessageBuffer for 4 1
Creating new MessageBuffer for 4 2
Creating new MessageBuffer for 4 3
Creating new MessageBuffer for 4 4
Creating new MessageBuffer for 4 5
Creating new MessageBuffer for 5 0
Creating new MessageBuffer for 5 1
Creating new MessageBuffer for 5 2
Creating new MessageBuffer for 5 3
Creating new MessageBuffer for 5 4
Creating new MessageBuffer for 5 5
Creating new MessageBuffer for 6 0
Creating new MessageBuffer for 6 1
Creating new MessageBuffer for 6 2
Creating new MessageBuffer for 6 3
Creating new MessageBuffer for 6 4
Creating new MessageBuffer for 6 5
Creating new MessageBuffer for 7 0
Creating new MessageBuffer for 7 1
Creating new MessageBuffer for 7 2
Creating new MessageBuffer for 7 3
Creating new MessageBuffer for 7 4
Creating new MessageBuffer for 7 5
Creating new MessageBuffer for 8 0
Creating new MessageBuffer for 8 1
Creating new MessageBuffer for 8 2
Creating new MessageBuffer for 8 3
Creating new MessageBuffer for 8 4
Creating new MessageBuffer for 8 5
Creating new MessageBuffer for 9 0
Creating new MessageBuffer for 9 1
Creating new MessageBuffer for 9 2
Creating new MessageBuffer for 9 3
Creating new MessageBuffer for 9 4
Creating new MessageBuffer for 9 5
system.cpu3: completed 10000 read accesses @3640772
system.cpu7: completed 10000 read accesses @3649542
system.cpu0: completed 10000 read accesses @3656374
system.cpu1: completed 10000 read accesses @3667859
system.cpu4: completed 10000 read accesses @3675222
system.cpu5: completed 10000 read accesses @3679111
system.cpu6: completed 10000 read accesses @3710014
system.cpu2: completed 10000 read accesses @3743556
system.cpu3: completed 20000 read accesses @6768103
system.cpu7: completed 20000 read accesses @6771442
system.cpu5: completed 20000 read accesses @6772946
system.cpu1: completed 20000 read accesses @6792072
system.cpu0: completed 20000 read accesses @6792088
system.cpu4: completed 20000 read accesses @6847561
system.cpu6: completed 20000 read accesses @6853396
system.cpu2: completed 20000 read accesses @6881032
system.cpu3: completed 30000 read accesses @9874625
system.cpu7: completed 30000 read accesses @9875111
system.cpu1: completed 30000 read accesses @9912008
system.cpu0: completed 30000 read accesses @9916494
system.cpu6: completed 30000 read accesses @9946066
system.cpu5: completed 30000 read accesses @9946502
system.cpu2: completed 30000 read accesses @9972472
system.cpu4: completed 30000 read accesses @9982022
system.cpu7: completed 40000 read accesses @12977880
system.cpu3: completed 40000 read accesses @13034394
system.cpu0: completed 40000 read accesses @13037610
system.cpu1: completed 40000 read accesses @13037678
system.cpu6: completed 40000 read accesses @13044482
system.cpu2: completed 40000 read accesses @13075158
system.cpu5: completed 40000 read accesses @13090802
system.cpu4: completed 40000 read accesses @13091547
system.cpu7: completed 50000 read accesses @16073284
system.cpu0: completed 50000 read accesses @16126074
system.cpu6: completed 50000 read accesses @16130742
system.cpu3: completed 50000 read accesses @16157406
system.cpu1: completed 50000 read accesses @16165456
system.cpu4: completed 50000 read accesses @16201749
system.cpu5: completed 50000 read accesses @16220008
system.cpu2: completed 50000 read accesses @16275764
system.cpu7: completed 60000 read accesses @19232340
system.cpu3: completed 60000 read accesses @19250699
system.cpu1: completed 60000 read accesses @19276836
system.cpu0: completed 60000 read accesses @19287336
system.cpu6: completed 60000 read accesses @19294047
system.cpu4: completed 60000 read accesses @19349695
system.cpu5: completed 60000 read accesses @19406282
system.cpu2: completed 60000 read accesses @19413090
system.cpu7: completed 70000 read accesses @22371848
system.cpu0: completed 70000 read accesses @22393000
system.cpu3: completed 70000 read accesses @22397454
system.cpu6: completed 70000 read accesses @22412286
system.cpu1: completed 70000 read accesses @22421258
system.cpu4: completed 70000 read accesses @22467490
system.cpu5: completed 70000 read accesses @22524837
system.cpu2: completed 70000 read accesses @22560722
system.cpu3: completed 80000 read accesses @25508623
system.cpu1: completed 80000 read accesses @25510110
system.cpu7: completed 80000 read accesses @25511616
system.cpu0: completed 80000 read accesses @25539501
system.cpu6: completed 80000 read accesses @25558545
system.cpu4: completed 80000 read accesses @25588582
system.cpu2: completed 80000 read accesses @25645348
system.cpu5: completed 80000 read accesses @25649504
system.cpu0: completed 90000 read accesses @28620081
system.cpu1: completed 90000 read accesses @28664699
system.cpu6: completed 90000 read accesses @28681534
system.cpu3: completed 90000 read accesses @28684736
system.cpu7: completed 90000 read accesses @28698368
system.cpu4: completed 90000 read accesses @28757223
system.cpu2: completed 90000 read accesses @28817704
system.cpu5: completed 90000 read accesses @28833888
system.cpu1: completed 100000 read accesses @31772571
hack: be nice to actually delete the event here

20
tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout
View file

@ -5,18 +5,12 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 5 2009 07:34:00
M5 revision 8bea207e2193 6172 default qtip tip ruby_tests_refs.diff
M5 started May 5 2009 07:34:03
M5 executing on piton
command line: /n/piton/z/nate/build/xgem5/build/ALPHA_SE/m5.fast -d /n/piton/z/nate/build/xgem5/build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby -re tests/run.py /n/piton/z/nate/build/xgem5/build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby
M5 compiled Jul 6 2009 11:03:45
M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
M5 started Jul 6 2009 11:11:07
M5 executing on maize
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby
Global frequency set at 1000000000000 ticks per second
Ruby Timing Mode
Creating event queue...
Creating event queue done
Creating system...
Processors: 8
Creating system done
Ruby initialization complete
Debug: Adding to filter: 'q' (Queue)
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 4446776 because maximum number of loads reached
Exiting @ tick 31772571 because maximum number of loads reached

40
tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
View file

@ -1,34 +1,34 @@
---------- Begin Simulation Statistics ----------
host_mem_usage 468884 # Number of bytes of host memory used
host_seconds 600.21 # Real time elapsed on the host
host_tick_rate 7409 # Simulator tick rate (ticks/s)
host_mem_usage 1500524 # Number of bytes of host memory used
host_seconds 568.45 # Real time elapsed on the host
host_tick_rate 55893 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_seconds 0.000004 # Number of seconds simulated
sim_ticks 4446776 # Number of ticks simulated
sim_seconds 0.000032 # Number of seconds simulated
sim_ticks 31772571 # Number of ticks simulated
system.cpu0.num_copies 0 # number of copy accesses completed
system.cpu0.num_reads 99923 # number of read accesses completed
system.cpu0.num_writes 53542 # number of write accesses completed
system.cpu0.num_reads 99945 # number of read accesses completed
system.cpu0.num_writes 53478 # number of write accesses completed
system.cpu1.num_copies 0 # number of copy accesses completed
system.cpu1.num_reads 100000 # number of read accesses completed
system.cpu1.num_writes 53649 # number of write accesses completed
system.cpu1.num_writes 53531 # number of write accesses completed
system.cpu2.num_copies 0 # number of copy accesses completed
system.cpu2.num_reads 99460 # number of read accesses completed
system.cpu2.num_writes 53552 # number of write accesses completed
system.cpu2.num_reads 99361 # number of read accesses completed
system.cpu2.num_writes 53707 # number of write accesses completed
system.cpu3.num_copies 0 # number of copy accesses completed
system.cpu3.num_reads 99751 # number of read accesses completed
system.cpu3.num_writes 53614 # number of write accesses completed
system.cpu3.num_reads 99846 # number of read accesses completed
system.cpu3.num_writes 53546 # number of write accesses completed
system.cpu4.num_copies 0 # number of copy accesses completed
system.cpu4.num_reads 99278 # number of read accesses completed
system.cpu4.num_writes 53437 # number of write accesses completed
system.cpu4.num_reads 99583 # number of read accesses completed
system.cpu4.num_writes 53626 # number of write accesses completed
system.cpu5.num_copies 0 # number of copy accesses completed
system.cpu5.num_reads 99949 # number of read accesses completed
system.cpu5.num_writes 53857 # number of write accesses completed
system.cpu5.num_reads 99623 # number of read accesses completed
system.cpu5.num_writes 53679 # number of write accesses completed
system.cpu6.num_copies 0 # number of copy accesses completed
system.cpu6.num_reads 99812 # number of read accesses completed
system.cpu6.num_writes 53539 # number of write accesses completed
system.cpu6.num_reads 99912 # number of read accesses completed
system.cpu6.num_writes 53508 # number of write accesses completed
system.cpu7.num_copies 0 # number of copy accesses completed
system.cpu7.num_reads 99962 # number of read accesses completed
system.cpu7.num_writes 53947 # number of write accesses completed
system.cpu7.num_reads 99813 # number of read accesses completed
system.cpu7.num_writes 53717 # number of write accesses completed
---------- End Simulation Statistics ----------