Fixes for full system compiling.
arch/alpha/arguments.cc: There will not be a phys mem ptr in the XC in the newmem. This read will have to go through something else. arch/alpha/ev5.cc: Remove instantiations of these functions for the FastCPU, as the FastCPU is not really used. Also this messed up the ability to specify which CPU models are being built. cpu/exec_context.hh: Remove getPhysMemPtr() function. cpu/exetrace.cc: Include sim/system.hh, and sort the includes. cpu/simple/cpu.cc: Fixes for full system compilation. kern/system_events.cc: Remove include of encumbered FullCPU. The branch prediction will need to be fixed up in a more generic way in the future. --HG-- extra : convert_revision : a8bbf562a277aa80e8f40112570c0a825298a05c
This commit is contained in:
parent
2ad1db3fde
commit
0b2deb2a88
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@ -60,7 +60,9 @@ AlphaArguments::getArg(bool fp)
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} else {
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} else {
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Addr sp = xc->readIntReg(30);
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Addr sp = xc->readIntReg(30);
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Addr paddr = vtophys(xc, sp + (number-6) * sizeof(uint64_t));
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Addr paddr = vtophys(xc, sp + (number-6) * sizeof(uint64_t));
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return xc->getPhysMemPtr()->phys_read_qword(paddr);
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// @todo: This read must go through the system or something else.
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// return xc->getPhysMemPtr()->phys_read_qword(paddr);
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return 0;
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}
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}
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}
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}
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@ -36,7 +36,6 @@
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#include "cpu/base.hh"
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#include "cpu/base.hh"
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#include "cpu/cpu_exec_context.hh"
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#include "cpu/cpu_exec_context.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/fast/cpu.hh"
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#include "kern/kernel_stats.hh"
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#include "kern/kernel_stats.hh"
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#include "sim/debug.hh"
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#include "sim/debug.hh"
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#include "sim/sim_events.hh"
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#include "sim/sim_events.hh"
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@ -575,12 +574,4 @@ CPUExecContext::simPalCheck(int palFunc)
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return true;
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return true;
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}
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}
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//Forward instantiation for FastCPU object
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template
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void AlphaISA::processInterrupts(FastCPU *xc);
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//Forward instantiation for FastCPU object
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template
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void AlphaISA::zeroRegisters(FastCPU *xc);
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#endif // FULL_SYSTEM
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#endif // FULL_SYSTEM
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@ -54,12 +54,11 @@ using namespace std;
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// constructor
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// constructor
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num, System *_sys,
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CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num, System *_sys,
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AlphaITB *_itb, AlphaDTB *_dtb,
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AlphaITB *_itb, AlphaDTB *_dtb)
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Memory *_mem)
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: _status(ExecContext::Unallocated), cpu(_cpu), thread_num(_thread_num),
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: _status(ExecContext::Unallocated), cpu(_cpu), thread_num(_thread_num),
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cpu_id(-1), lastActivate(0), lastSuspend(0), mem(_mem), itb(_itb),
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cpu_id(-1), lastActivate(0), lastSuspend(0), system(_sys), itb(_itb),
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dtb(_dtb), system(_sys), memctrl(_sys->memctrl), physmem(_sys->physmem),
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dtb(_dtb), memctrl(_sys->memctrl), profile(NULL),
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profile(NULL), quiesceEvent(this), func_exe_inst(0), storeCondFailures(0)
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quiesceEvent(this), func_exe_inst(0), storeCondFailures(0)
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{
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{
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proxy = new ProxyExecContext<CPUExecContext>(this);
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proxy = new ProxyExecContext<CPUExecContext>(this);
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@ -121,9 +121,6 @@ class CPUExecContext
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System *system;
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System *system;
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/// Port that syscalls can use to access memory (provides translation step).
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TranslatingPort *port;
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// Memory *mem;
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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AlphaITB *itb;
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AlphaITB *itb;
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@ -167,6 +164,9 @@ class CPUExecContext
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void profileSample();
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void profileSample();
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#else
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#else
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/// Port that syscalls can use to access memory (provides translation step).
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TranslatingPort *port;
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Process *process;
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Process *process;
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// Address space ID. Note that this is used for TIMING cache
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// Address space ID. Note that this is used for TIMING cache
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// constructor: initialize context from given process structure
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// constructor: initialize context from given process structure
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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CPUExecContext(BaseCPU *_cpu, int _thread_num, System *_system,
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CPUExecContext(BaseCPU *_cpu, int _thread_num, System *_system,
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AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_dem);
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AlphaITB *_itb, AlphaDTB *_dtb);
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#else
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#else
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CPUExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid, Port *mem_port);
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CPUExecContext(BaseCPU *_cpu, int _thread_num, Process *_process,
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int _asid, Port *mem_port);
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// Constructor to use XC to pass reg file around. Not used for anything
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// Constructor to use XC to pass reg file around. Not used for anything
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// else.
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// else.
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CPUExecContext(RegFile *regFile);
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CPUExecContext(RegFile *regFile);
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void serialize(std::ostream &os);
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void serialize(std::ostream &os);
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void unserialize(Checkpoint *cp, const std::string §ion);
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void unserialize(Checkpoint *cp, const std::string §ion);
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TranslatingPort *getMemPort() { return port; }
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BaseCPU *getCpuPtr() { return cpu; }
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BaseCPU *getCpuPtr() { return cpu; }
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ExecContext *getProxy() { return proxy; }
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ExecContext *getProxy() { return proxy; }
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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System *getSystemPtr() { return system; }
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System *getSystemPtr() { return system; }
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PhysicalMemory *getPhysMemPtr() { return physmem; }
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AlphaITB *getITBPtr() { return itb; }
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AlphaITB *getITBPtr() { return itb; }
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AlphaDTB *getDTBPtr() { return dtb; }
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AlphaDTB *getDTBPtr() { return dtb; }
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}
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}
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#else
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#else
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TranslatingPort *getMemPort() { return port; }
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Process *getProcessPtr() { return process; }
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Process *getProcessPtr() { return process; }
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int getInstAsid() { return asid; }
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int getInstAsid() { return asid; }
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#include "sim/serialize.hh"
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#include "sim/serialize.hh"
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#include "sim/byteswap.hh"
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#include "sim/byteswap.hh"
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// forward declaration: see functional_memory.hh
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// @todo: Figure out a more architecture independent way to obtain the ITB and
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// @todo: Figure out a more architecture independent way to obtain the ITB and
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// DTB pointers.
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// DTB pointers.
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class AlphaDTB;
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class AlphaDTB;
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class AlphaITB;
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class AlphaITB;
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class BaseCPU;
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class BaseCPU;
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class Event;
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class Event;
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class PhysicalMemory;
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class TranslatingPort;
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class TranslatingPort;
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class Process;
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class Process;
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class System;
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class System;
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virtual ~ExecContext() { };
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virtual ~ExecContext() { };
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virtual TranslatingPort *getMemPort() = 0;
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virtual BaseCPU *getCpuPtr() = 0;
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virtual BaseCPU *getCpuPtr() = 0;
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virtual void setCpuId(int id) = 0;
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virtual void setCpuId(int id) = 0;
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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virtual System *getSystemPtr() = 0;
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virtual System *getSystemPtr() = 0;
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virtual PhysicalMemory *getPhysMemPtr() = 0;
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virtual AlphaITB *getITBPtr() = 0;
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virtual AlphaITB *getITBPtr() = 0;
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virtual AlphaDTB * getDTBPtr() = 0;
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virtual AlphaDTB * getDTBPtr() = 0;
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#else
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#else
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virtual TranslatingPort *getMemPort() = 0;
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virtual Process *getProcessPtr() = 0;
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virtual Process *getProcessPtr() = 0;
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#endif
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#endif
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public:
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public:
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TranslatingPort *getMemPort() { return actualXC->getMemPort(); }
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BaseCPU *getCpuPtr() { return actualXC->getCpuPtr(); }
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BaseCPU *getCpuPtr() { return actualXC->getCpuPtr(); }
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void setCpuId(int id) { actualXC->setCpuId(id); }
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void setCpuId(int id) { actualXC->setCpuId(id); }
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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System *getSystemPtr() { return actualXC->getSystemPtr(); }
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System *getSystemPtr() { return actualXC->getSystemPtr(); }
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PhysicalMemory *getPhysMemPtr() { return actualXC->getPhysMemPtr(); }
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AlphaITB *getITBPtr() { return actualXC->getITBPtr(); }
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AlphaITB *getITBPtr() { return actualXC->getITBPtr(); }
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AlphaDTB *getDTBPtr() { return actualXC->getDTBPtr(); }
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AlphaDTB *getDTBPtr() { return actualXC->getDTBPtr(); }
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#else
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#else
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TranslatingPort *getMemPort() { return actualXC->getMemPort(); }
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Process *getProcessPtr() { return actualXC->getProcessPtr(); }
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Process *getProcessPtr() { return actualXC->getProcessPtr(); }
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#endif
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#endif
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@ -29,11 +29,12 @@
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#include <fstream>
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#include <fstream>
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#include <iomanip>
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#include <iomanip>
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#include "sim/param.hh"
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#include "cpu/exetrace.hh"
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#include "base/loader/symtab.hh"
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#include "base/loader/symtab.hh"
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#include "cpu/base.hh"
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#include "cpu/base.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/static_inst.hh"
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#include "cpu/static_inst.hh"
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#include "sim/param.hh"
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#include "sim/system.hh"
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using namespace std;
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using namespace std;
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@ -64,8 +64,8 @@
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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#include "base/remote_gdb.hh"
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#include "base/remote_gdb.hh"
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#include "mem/functional/memory_control.hh"
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//#include "mem/functional/memory_control.hh"
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#include "mem/functional/physical.hh"
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//#include "mem/functional/physical.hh"
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#include "sim/system.hh"
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#include "sim/system.hh"
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#include "arch/tlb.hh"
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#include "arch/tlb.hh"
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#include "arch/stacktrace.hh"
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#include "arch/stacktrace.hh"
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}
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}
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SimpleCPU::SimpleCPU(Params *p)
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SimpleCPU::SimpleCPU(Params *p)
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#if !FULL_SYSTEM
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: BaseCPU(p), mem(p->mem), icachePort(this),
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: BaseCPU(p), mem(p->mem), icachePort(this),
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dcachePort(this), tickEvent(this, p->width), cpuXC(NULL)
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dcachePort(this), tickEvent(this, p->width), cpuXC(NULL)
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#else
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: BaseCPU(p), icachePort(this), dcachePort(this),
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tickEvent(this, p->width), cpuXC(NULL)
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#endif
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{
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{
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_status = Idle;
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_status = Idle;
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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cpuXC = new CPUExecContext(this, 0, p->system, p->itb, p->dtb, p->mem);
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cpuXC = new CPUExecContext(this, 0, p->system, p->itb, p->dtb);
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#else
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#else
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cpuXC = new CPUExecContext(this, /* thread_num */ 0, p->process, /* asid */ 0,
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cpuXC = new CPUExecContext(this, /* thread_num */ 0, p->process, /* asid */ 0,
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&dcachePort);
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&dcachePort);
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@ -899,7 +904,7 @@ SimpleCPU::tick()
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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if (checkInterrupts && check_interrupts() && !cpuXC->inPalMode() &&
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if (checkInterrupts && check_interrupts() && !cpuXC->inPalMode() &&
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status() != IcacheMissComplete) {
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status() != IcacheAccessComplete) {
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int ipl = 0;
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int ipl = 0;
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int summary = 0;
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int summary = 0;
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checkInterrupts = false;
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checkInterrupts = false;
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@ -26,8 +26,11 @@
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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#include "encumbered/cpu/full/cpu.hh"
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#include "cpu/base.hh"
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#include "cpu/cpu_exec_context.hh"
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#include "kern/kernel_stats.hh"
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#include "kern/kernel_stats.hh"
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#include "kern/system_events.hh"
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#include "sim/system.hh"
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using namespace TheISA;
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using namespace TheISA;
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@ -41,11 +44,12 @@ SkipFuncEvent::process(ExecContext *xc)
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xc->setPC(newpc);
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xc->setPC(newpc);
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xc->setNextPC(xc->readPC() + sizeof(TheISA::MachInst));
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xc->setNextPC(xc->readPC() + sizeof(TheISA::MachInst));
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/*
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BranchPred *bp = xc->getCpuPtr()->getBranchPred();
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BranchPred *bp = xc->getCpuPtr()->getBranchPred();
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if (bp != NULL) {
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if (bp != NULL) {
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bp->popRAS(xc->getThreadNum());
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bp->popRAS(xc->getThreadNum());
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}
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}
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*/
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}
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}
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Loading…
Reference in a new issue