From 0b2deb2a8897fa857d2b3e1936401c6666fdc728 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Thu, 30 Mar 2006 10:42:55 -0500 Subject: [PATCH] Fixes for full system compiling. arch/alpha/arguments.cc: There will not be a phys mem ptr in the XC in the newmem. This read will have to go through something else. arch/alpha/ev5.cc: Remove instantiations of these functions for the FastCPU, as the FastCPU is not really used. Also this messed up the ability to specify which CPU models are being built. cpu/exec_context.hh: Remove getPhysMemPtr() function. cpu/exetrace.cc: Include sim/system.hh, and sort the includes. cpu/simple/cpu.cc: Fixes for full system compilation. kern/system_events.cc: Remove include of encumbered FullCPU. The branch prediction will need to be fixed up in a more generic way in the future. --HG-- extra : convert_revision : a8bbf562a277aa80e8f40112570c0a825298a05c --- arch/alpha/arguments.cc | 4 +++- arch/alpha/ev5.cc | 9 --------- cpu/cpu_exec_context.cc | 9 ++++----- cpu/cpu_exec_context.hh | 17 ++++++++--------- cpu/exec_context.hh | 14 ++++---------- cpu/exetrace.cc | 5 +++-- cpu/simple/cpu.cc | 13 +++++++++---- kern/system_events.cc | 8 ++++++-- 8 files changed, 37 insertions(+), 42 deletions(-) diff --git a/arch/alpha/arguments.cc b/arch/alpha/arguments.cc index a782ea330..338581e32 100644 --- a/arch/alpha/arguments.cc +++ b/arch/alpha/arguments.cc @@ -60,7 +60,9 @@ AlphaArguments::getArg(bool fp) } else { Addr sp = xc->readIntReg(30); Addr paddr = vtophys(xc, sp + (number-6) * sizeof(uint64_t)); - return xc->getPhysMemPtr()->phys_read_qword(paddr); + // @todo: This read must go through the system or something else. +// return xc->getPhysMemPtr()->phys_read_qword(paddr); + return 0; } } diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc index a5a8851c2..12f7659e6 100644 --- a/arch/alpha/ev5.cc +++ b/arch/alpha/ev5.cc @@ -36,7 +36,6 @@ #include "cpu/base.hh" #include "cpu/cpu_exec_context.hh" #include "cpu/exec_context.hh" -#include "cpu/fast/cpu.hh" #include "kern/kernel_stats.hh" #include "sim/debug.hh" #include "sim/sim_events.hh" @@ -575,12 +574,4 @@ CPUExecContext::simPalCheck(int palFunc) return true; } -//Forward instantiation for FastCPU object -template -void AlphaISA::processInterrupts(FastCPU *xc); - -//Forward instantiation for FastCPU object -template -void AlphaISA::zeroRegisters(FastCPU *xc); - #endif // FULL_SYSTEM diff --git a/cpu/cpu_exec_context.cc b/cpu/cpu_exec_context.cc index 0a3dc5675..4ada24068 100644 --- a/cpu/cpu_exec_context.cc +++ b/cpu/cpu_exec_context.cc @@ -54,12 +54,11 @@ using namespace std; // constructor #if FULL_SYSTEM CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num, System *_sys, - AlphaITB *_itb, AlphaDTB *_dtb, - Memory *_mem) + AlphaITB *_itb, AlphaDTB *_dtb) : _status(ExecContext::Unallocated), cpu(_cpu), thread_num(_thread_num), - cpu_id(-1), lastActivate(0), lastSuspend(0), mem(_mem), itb(_itb), - dtb(_dtb), system(_sys), memctrl(_sys->memctrl), physmem(_sys->physmem), - profile(NULL), quiesceEvent(this), func_exe_inst(0), storeCondFailures(0) + cpu_id(-1), lastActivate(0), lastSuspend(0), system(_sys), itb(_itb), + dtb(_dtb), memctrl(_sys->memctrl), profile(NULL), + quiesceEvent(this), func_exe_inst(0), storeCondFailures(0) { proxy = new ProxyExecContext(this); diff --git a/cpu/cpu_exec_context.hh b/cpu/cpu_exec_context.hh index 236619752..83afb3b85 100644 --- a/cpu/cpu_exec_context.hh +++ b/cpu/cpu_exec_context.hh @@ -121,9 +121,6 @@ class CPUExecContext System *system; - /// Port that syscalls can use to access memory (provides translation step). - TranslatingPort *port; -// Memory *mem; #if FULL_SYSTEM AlphaITB *itb; @@ -167,6 +164,9 @@ class CPUExecContext void profileSample(); #else + /// Port that syscalls can use to access memory (provides translation step). + TranslatingPort *port; + Process *process; // Address space ID. Note that this is used for TIMING cache @@ -203,9 +203,10 @@ class CPUExecContext // constructor: initialize context from given process structure #if FULL_SYSTEM CPUExecContext(BaseCPU *_cpu, int _thread_num, System *_system, - AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_dem); + AlphaITB *_itb, AlphaDTB *_dtb); #else - CPUExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid, Port *mem_port); + CPUExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, + int _asid, Port *mem_port); // Constructor to use XC to pass reg file around. Not used for anything // else. CPUExecContext(RegFile *regFile); @@ -219,8 +220,6 @@ class CPUExecContext void serialize(std::ostream &os); void unserialize(Checkpoint *cp, const std::string §ion); - TranslatingPort *getMemPort() { return port; } - BaseCPU *getCpuPtr() { return cpu; } ExecContext *getProxy() { return proxy; } @@ -230,8 +229,6 @@ class CPUExecContext #if FULL_SYSTEM System *getSystemPtr() { return system; } - PhysicalMemory *getPhysMemPtr() { return physmem; } - AlphaITB *getITBPtr() { return itb; } AlphaDTB *getDTBPtr() { return dtb; } @@ -255,6 +252,8 @@ class CPUExecContext } #else + TranslatingPort *getMemPort() { return port; } + Process *getProcessPtr() { return process; } int getInstAsid() { return asid; } diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh index 2fdb19c73..8f93875a1 100644 --- a/cpu/exec_context.hh +++ b/cpu/exec_context.hh @@ -36,14 +36,12 @@ #include "sim/serialize.hh" #include "sim/byteswap.hh" -// forward declaration: see functional_memory.hh // @todo: Figure out a more architecture independent way to obtain the ITB and // DTB pointers. class AlphaDTB; class AlphaITB; class BaseCPU; class Event; -class PhysicalMemory; class TranslatingPort; class Process; class System; @@ -83,8 +81,6 @@ class ExecContext virtual ~ExecContext() { }; - virtual TranslatingPort *getMemPort() = 0; - virtual BaseCPU *getCpuPtr() = 0; virtual void setCpuId(int id) = 0; @@ -94,12 +90,12 @@ class ExecContext #if FULL_SYSTEM virtual System *getSystemPtr() = 0; - virtual PhysicalMemory *getPhysMemPtr() = 0; - virtual AlphaITB *getITBPtr() = 0; virtual AlphaDTB * getDTBPtr() = 0; #else + virtual TranslatingPort *getMemPort() = 0; + virtual Process *getProcessPtr() = 0; #endif @@ -251,8 +247,6 @@ class ProxyExecContext : public ExecContext public: - TranslatingPort *getMemPort() { return actualXC->getMemPort(); } - BaseCPU *getCpuPtr() { return actualXC->getCpuPtr(); } void setCpuId(int id) { actualXC->setCpuId(id); } @@ -262,12 +256,12 @@ class ProxyExecContext : public ExecContext #if FULL_SYSTEM System *getSystemPtr() { return actualXC->getSystemPtr(); } - PhysicalMemory *getPhysMemPtr() { return actualXC->getPhysMemPtr(); } - AlphaITB *getITBPtr() { return actualXC->getITBPtr(); } AlphaDTB *getDTBPtr() { return actualXC->getDTBPtr(); } #else + TranslatingPort *getMemPort() { return actualXC->getMemPort(); } + Process *getProcessPtr() { return actualXC->getProcessPtr(); } #endif diff --git a/cpu/exetrace.cc b/cpu/exetrace.cc index ebb719b2c..4db72320c 100644 --- a/cpu/exetrace.cc +++ b/cpu/exetrace.cc @@ -29,11 +29,12 @@ #include #include -#include "sim/param.hh" -#include "cpu/exetrace.hh" #include "base/loader/symtab.hh" #include "cpu/base.hh" +#include "cpu/exetrace.hh" #include "cpu/static_inst.hh" +#include "sim/param.hh" +#include "sim/system.hh" using namespace std; diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc index 8a9e41d53..3d37f970f 100644 --- a/cpu/simple/cpu.cc +++ b/cpu/simple/cpu.cc @@ -64,8 +64,8 @@ #if FULL_SYSTEM #include "base/remote_gdb.hh" -#include "mem/functional/memory_control.hh" -#include "mem/functional/physical.hh" +//#include "mem/functional/memory_control.hh" +//#include "mem/functional/physical.hh" #include "sim/system.hh" #include "arch/tlb.hh" #include "arch/stacktrace.hh" @@ -155,13 +155,18 @@ SimpleCPU::CpuPort::recvRetry() } SimpleCPU::SimpleCPU(Params *p) +#if !FULL_SYSTEM : BaseCPU(p), mem(p->mem), icachePort(this), dcachePort(this), tickEvent(this, p->width), cpuXC(NULL) +#else + : BaseCPU(p), icachePort(this), dcachePort(this), + tickEvent(this, p->width), cpuXC(NULL) +#endif { _status = Idle; #if FULL_SYSTEM - cpuXC = new CPUExecContext(this, 0, p->system, p->itb, p->dtb, p->mem); + cpuXC = new CPUExecContext(this, 0, p->system, p->itb, p->dtb); #else cpuXC = new CPUExecContext(this, /* thread_num */ 0, p->process, /* asid */ 0, &dcachePort); @@ -899,7 +904,7 @@ SimpleCPU::tick() #if FULL_SYSTEM if (checkInterrupts && check_interrupts() && !cpuXC->inPalMode() && - status() != IcacheMissComplete) { + status() != IcacheAccessComplete) { int ipl = 0; int summary = 0; checkInterrupts = false; diff --git a/kern/system_events.cc b/kern/system_events.cc index 9b9861497..fd5c12e44 100644 --- a/kern/system_events.cc +++ b/kern/system_events.cc @@ -26,8 +26,11 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include "encumbered/cpu/full/cpu.hh" +#include "cpu/base.hh" +#include "cpu/cpu_exec_context.hh" #include "kern/kernel_stats.hh" +#include "kern/system_events.hh" +#include "sim/system.hh" using namespace TheISA; @@ -41,11 +44,12 @@ SkipFuncEvent::process(ExecContext *xc) xc->setPC(newpc); xc->setNextPC(xc->readPC() + sizeof(TheISA::MachInst)); - +/* BranchPred *bp = xc->getCpuPtr()->getBranchPred(); if (bp != NULL) { bp->popRAS(xc->getThreadNum()); } +*/ }