CPU: fix sparc_fs booting with SimpleTimingCPU.
--HG-- extra : convert_revision : 3d95f6daa7f0e8e376d1a880f64c056619263885
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@ -29,6 +29,7 @@
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*/
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*/
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#include "arch/locked_mem.hh"
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#include "arch/locked_mem.hh"
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#include "arch/mmaped_ipr.hh"
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#include "arch/utility.hh"
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#include "arch/utility.hh"
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#include "base/bigint.hh"
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#include "base/bigint.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/exetrace.hh"
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@ -266,7 +267,13 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
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Packet::Broadcast);
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Packet::Broadcast);
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pkt->dataDynamic<T>(new T);
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pkt->dataDynamic<T>(new T);
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if (!dcachePort.sendTiming(pkt)) {
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if (req->isMmapedIpr()) {
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Tick delay;
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delay = TheISA::handleIprRead(thread->getTC(), pkt);
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new IprEvent(pkt, this, nextCycle(curTick + delay));
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_status = DcacheWaitResponse;
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dcache_pkt = NULL;
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} else if (!dcachePort.sendTiming(pkt)) {
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_status = DcacheRetry;
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_status = DcacheRetry;
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dcache_pkt = pkt;
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dcache_pkt = pkt;
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} else {
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} else {
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@ -375,7 +382,14 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
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dcache_pkt->set(data);
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dcache_pkt->set(data);
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if (do_access) {
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if (do_access) {
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if (!dcachePort.sendTiming(dcache_pkt)) {
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if (req->isMmapedIpr()) {
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Tick delay;
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dcache_pkt->set(htog(data));
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delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
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new IprEvent(dcache_pkt, this, nextCycle(curTick + delay));
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_status = DcacheWaitResponse;
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dcache_pkt = NULL;
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} else if (!dcachePort.sendTiming(dcache_pkt)) {
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_status = DcacheRetry;
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_status = DcacheRetry;
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} else {
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} else {
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_status = DcacheWaitResponse;
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_status = DcacheWaitResponse;
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@ -551,6 +565,10 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
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}
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}
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postExecute();
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postExecute();
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// @todo remove me after debugging with legion done
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if (curStaticInst && (!curStaticInst->isMicroop() ||
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curStaticInst->isFirstMicroop()))
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instCnt++;
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advanceInst(fault);
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advanceInst(fault);
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}
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}
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} else {
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} else {
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@ -567,6 +585,10 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
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}
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}
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postExecute();
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postExecute();
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// @todo remove me after debugging with legion done
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if (curStaticInst && (!curStaticInst->isMicroop() ||
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curStaticInst->isFirstMicroop()))
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instCnt++;
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advanceInst(fault);
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advanceInst(fault);
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}
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}
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@ -730,6 +752,24 @@ TimingSimpleCPU::DcachePort::recvRetry()
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}
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}
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}
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}
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TimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t)
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: Event(&mainEventQueue), pkt(_pkt), cpu(_cpu)
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{
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schedule(t);
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}
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void
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TimingSimpleCPU::IprEvent::process()
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{
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cpu->completeDataAccess(pkt);
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}
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const char *
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TimingSimpleCPU::IprEvent::description()
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{
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return "Timing Simple CPU Delay IPR event";
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}
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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//
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//
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@ -203,6 +203,14 @@ class TimingSimpleCPU : public BaseSimpleCPU
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typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;
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typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;
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FetchEvent *fetchEvent;
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FetchEvent *fetchEvent;
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struct IprEvent : Event {
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Packet *pkt;
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TimingSimpleCPU *cpu;
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IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t);
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virtual void process();
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virtual const char *description();
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};
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void completeDrain();
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void completeDrain();
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};
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};
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@ -56,6 +56,9 @@ Iob::Iob(const Params *p)
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iobJBusAddr = ULL(0x9F00000000);
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iobJBusAddr = ULL(0x9F00000000);
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iobJBusSize = ULL(0x0100000000);
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iobJBusSize = ULL(0x0100000000);
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assert (params()->system->threadContexts.size() <= MaxNiagaraProcs);
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assert (params()->system->threadContexts.size() <= MaxNiagaraProcs);
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pioDelay = p->pio_latency;
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// Get the interrupt controller from the platform
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// Get the interrupt controller from the platform
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ic = platform->intrctrl;
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ic = platform->intrctrl;
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