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Merge zizzer:/bk/newmem

Browse source 
into  zeep.pool:/tmp/newmem

--HG--
extra : convert_revision : 8f173d3522e2e8847e51dfab48f35e34e6d3c1a7
This commit is contained in:
Ali Saidi 2007-04-21 19:12:13 -04:00
commit 088a056583
12 changed files with 103 additions and 68 deletions
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14
src/arch/alpha/ev5.cc
View file

@ -245,13 +245,13 @@ AlphaISA::MiscRegFile::readIpr(int idx, ThreadContext *tc)
{
AlphaISA::PTE &pte = tc->getDTBPtr()->index(!tc->misspeculating());
retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
retval |= ((uint64_t)pte.ppn & ULL(0x7ffffff)) << 32;
retval |= ((uint64_t)pte.xre & ULL(0xf)) << 8;
retval |= ((uint64_t)pte.xwe & ULL(0xf)) << 12;
retval |= ((uint64_t)pte.fonr & ULL(0x1)) << 1;
retval |= ((uint64_t)pte.fonw & ULL(0x1))<< 2;
retval |= ((uint64_t)pte.asma & ULL(0x1)) << 4;
retval |= ((uint64_t)pte.asn & ULL(0x7f)) << 57;
}
break;

4
src/arch/alpha/floatregfile.hh
View file

@ -35,7 +35,7 @@
#include "arch/alpha/isa_traits.hh"
#include "arch/alpha/types.hh"
#include <string.h>
#include <cstring>
#include <iostream>
class Checkpoint;
@ -61,7 +61,7 @@ namespace AlphaISA
void unserialize(Checkpoint *cp, const std::string &section);
void clear()
{ bzero(d, sizeof(d)); }
{ std::memset(d, 0, sizeof(d)); }
};
}

4
src/arch/alpha/intregfile.hh
View file

@ -35,7 +35,7 @@
#include "arch/alpha/types.hh"
#include <iostream>
#include <strings.h>
#include <cstring>
class Checkpoint;
@ -71,7 +71,7 @@ namespace AlphaISA
void unserialize(Checkpoint *cp, const std::string &section);
void clear()
{ bzero(regs, sizeof(regs)); }
{ std::memset(regs, 0, sizeof(regs)); }
};
}

12
src/arch/alpha/isa/fp.isa
View file

@ -192,10 +192,10 @@ output decoder {{
}
const int AlphaFP::alphaToC99RoundingMode[] = {
FE_TOWARDZERO, // Chopped
FE_DOWNWARD, // Minus_Infinity
FE_TONEAREST, // Normal
FE_UPWARD // Dynamic in inst, Plus_Infinity in FPCR
M5_FE_TOWARDZERO, // Chopped
M5_FE_DOWNWARD, // Minus_Infinity
M5_FE_TONEAREST, // Normal
M5_FE_UPWARD // Dynamic in inst, Plus_Infinity in FPCR
};
const char *AlphaFP::roundingModeSuffix[] = { "c", "m", "", "d" };
@ -228,10 +228,10 @@ def template FloatingPointExecute {{
if (roundingMode == Normal) {
%(code)s;
} else {
fesetround(getC99RoundingMode(
m5_fesetround(getC99RoundingMode(
xc->readMiscRegNoEffect(AlphaISA::MISCREG_FPCR)));
%(code)s;
fesetround(FE_TONEAREST);
m5_fesetround(M5_FE_TONEAREST);
}
#else
if (roundingMode != Normal && !warnedOnRounding) {

31
src/arch/sparc/isa/formats/basic.isa
View file

@ -109,37 +109,22 @@ def format FpBasic(code, *flags) {{
fp_code = """
Fsr |= bits(Fsr,4,0) << 5;
Fsr = insertBits(Fsr,4,0,0);
#if defined(__sun) || defined (__OpenBSD__)
fp_rnd newrnd = FP_RN;
int newrnd = M5_FE_TONEAREST;
switch (Fsr<31:30>) {
case 0: newrnd = FP_RN; break;
case 1: newrnd = FP_RZ; break;
case 2: newrnd = FP_RP; break;
case 3: newrnd = FP_RM; break;
case 0: newrnd = M5_FE_TONEAREST; break;
case 1: newrnd = M5_FE_TOWARDZERO; break;
case 2: newrnd = M5_FE_UPWARD; break;
case 3: newrnd = M5_FE_DOWNWARD; break;
}
fp_rnd oldrnd = fpsetround(newrnd);
#else
int newrnd = FE_TONEAREST;
switch (Fsr<31:30>) {
case 0: newrnd = FE_TONEAREST; break;
case 1: newrnd = FE_TOWARDZERO; break;
case 2: newrnd = FE_UPWARD; break;
case 3: newrnd = FE_DOWNWARD; break;
}
int oldrnd = fegetround();
fesetround(newrnd);
#endif
int oldrnd = m5_fegetround();
m5_fesetround(newrnd);
"""
fp_code += code
fp_code += """
#if defined(__sun) || defined (__OpenBSD__)
fpsetround(oldrnd);
#else
fesetround(oldrnd);
#endif
m5_fesetround(oldrnd);
"""
fp_code = filterDoubles(fp_code)
iop = InstObjParams(name, Name, 'SparcStaticInst', fp_code, flags)

12
src/arch/sparc/isa/includes.isa
View file

@ -53,22 +53,14 @@ output decoder {{
#include "cpu/thread_context.hh" // for Jump::branchTarget()
#include "mem/packet.hh"
#if defined(linux) || defined(__APPLE__)
#include <fenv.h>
#endif
#include "base/fenv.hh"
#include <algorithm>
using namespace SparcISA;
}};
output exec {{
#if defined(linux) || defined(__APPLE__)
#include <fenv.h>
#endif
#if defined(__sun) || defined (__OpenBSD__)
#include <ieeefp.h>
#endif
#include "base/fenv.hh"
#if FULL_SYSTEM
#include "sim/pseudo_inst.hh"

1
src/base/SConscript
View file

@ -57,6 +57,7 @@ Source('circlebuf.cc')
Source('cprintf.cc')
Source('crc.cc')
Source('fast_alloc.cc')
Source('fenv.c')
Source('fifo_buffer.cc')
Source('hostinfo.cc')
Source('hybrid_pred.cc')

56
src/base/fenv.c Normal file
View file

@ -0,0 +1,56 @@
/*
* Copyright (c) 2007 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Ali Saidi
*/
#include <assert.h>
#include <stdlib.h>
#include <fenv.h>
void m5_fesetround(int rm);
int m5_fegetround();
static const int m5_round_ops[] = {FE_DOWNWARD, FE_TONEAREST, FE_TOWARDZERO, FE_UPWARD};
void m5_fesetround(int rm)
{
assert(rm > 0 && rm < 4);
fesetround(m5_round_ops[rm]);
}
int m5_fegetround()
{
int x;
int rm = fegetround();
for(x = 0; x < 4; x++)
if (m5_round_ops[x] == rm)
return x;
abort();
return 0;
}

21
src/base/fenv.hh
View file

@ -33,20 +33,21 @@
#include "config/use_fenv.hh"
#define M5_FE_DOWNWARD 0
#define M5_FE_TONEAREST 1
#define M5_FE_TOWARDZERO 2
#define M5_FE_UPWARD 3
#if USE_FENV
#include <fenv.h>
extern "C" {
void m5_fesetround(int rm);
int m5_fegetround();
}
#else
// Dummy definitions to allow code to compile w/o a real <fenv.h>.
#define FE_TONEAREST 0
#define FE_DOWNWARD 0
#define FE_UPWARD 0
#define FE_TOWARDZERO 0
inline int fesetround(int rounding_mode) { return 0; }
inline void m5_fesetround(int rm) { ; }
inline int m5_fegetround() {return 0; }
#endif // USE_FENV

9
src/base/random.cc
View file

@ -29,9 +29,6 @@
* Ali Saidi
*/
#if defined(__sun)
#include <ieeefp.h>
#endif
#ifdef __SUNPRO_CC
#include <stdlib.h>
#include <math.h>
@ -40,6 +37,7 @@
#include <cstdlib>
#include <cmath>
#include "base/fenv.hh"
#include "base/random.hh"
using namespace std;
@ -61,9 +59,10 @@ m5round(double r)
{
#if defined(__sun)
double val;
fp_rnd oldrnd = fpsetround(FP_RN);
int oldrnd = m5_fegetround();
m5_fesetround(M5_FE_TONEAREST);
val = rint(r);
fpsetround(oldrnd);
m5_fesetround(oldrnd);
return val;
#else
return round(r);

5
src/cpu/o3/lsq_unit.hh
View file

@ -33,6 +33,7 @@
#define __CPU_O3_LSQ_UNIT_HH__
#include <algorithm>
#include <cstring>
#include <map>
#include <queue>
@ -292,7 +293,7 @@ class LSQUnit {
: inst(NULL), req(NULL), size(0),
canWB(0), committed(0), completed(0)
{
bzero(data, sizeof(data));
std::memset(data, 0, sizeof(data));
}
/** Constructs a store queue entry for a given instruction. */
@ -300,7 +301,7 @@ class LSQUnit {
: inst(_inst), req(NULL), size(0),
canWB(0), committed(0), completed(0)
{
bzero(data, sizeof(data));
std::memset(data, 0, sizeof(data));
}
/** The store instruction. */

2
src/dev/alpha/console.cc
View file

@ -76,7 +76,7 @@ AlphaConsole::AlphaConsole(Params *p)
alphaAccess->diskOperation = 0;
alphaAccess->outputChar = 0;
alphaAccess->inputChar = 0;
bzero(alphaAccess->cpuStack, sizeof(alphaAccess->cpuStack));
std::memset(alphaAccess->cpuStack, 0, sizeof(alphaAccess->cpuStack));
}