X86: Don't fetch in the simple CPU if you're in the ROM.
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parent
f245358343
commit
0756dbb37a
2 changed files with 56 additions and 38 deletions
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@ -718,31 +718,37 @@ AtomicSimpleCPU::tick()
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checkPcEventQueue();
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Fault fault = setupFetchRequest(&ifetch_req);
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Fault fault = NoFault;
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bool fromRom = isRomMicroPC(thread->readMicroPC());
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if (!fromRom)
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fault = setupFetchRequest(&ifetch_req);
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if (fault == NoFault) {
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Tick icache_latency = 0;
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bool icache_access = false;
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dcache_access = false; // assume no dcache access
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//Fetch more instruction memory if necessary
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//if(predecoder.needMoreBytes())
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//{
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icache_access = true;
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Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq,
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Packet::Broadcast);
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ifetch_pkt.dataStatic(&inst);
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if (!fromRom) {
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//Fetch more instruction memory if necessary
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//if(predecoder.needMoreBytes())
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//{
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icache_access = true;
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Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq,
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Packet::Broadcast);
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ifetch_pkt.dataStatic(&inst);
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if (hasPhysMemPort && ifetch_pkt.getAddr() == physMemAddr)
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icache_latency = physmemPort.sendAtomic(&ifetch_pkt);
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else
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icache_latency = icachePort.sendAtomic(&ifetch_pkt);
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if (hasPhysMemPort && ifetch_pkt.getAddr() == physMemAddr)
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icache_latency = physmemPort.sendAtomic(&ifetch_pkt);
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else
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icache_latency = icachePort.sendAtomic(&ifetch_pkt);
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assert(!ifetch_pkt.isError());
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assert(!ifetch_pkt.isError());
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// ifetch_req is initialized to read the instruction directly
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// into the CPU object's inst field.
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//}
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// ifetch_req is initialized to read the instruction directly
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// into the CPU object's inst field.
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//}
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}
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preExecute();
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@ -531,28 +531,35 @@ TimingSimpleCPU::fetch()
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checkPcEventQueue();
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Request *ifetch_req = new Request();
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ifetch_req->setThreadContext(cpuId, /* thread ID */ 0);
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Fault fault = setupFetchRequest(ifetch_req);
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bool fromRom = isRomMicroPC(thread->readMicroPC());
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ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast);
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ifetch_pkt->dataStatic(&inst);
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if (!fromRom) {
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Request *ifetch_req = new Request();
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ifetch_req->setThreadContext(cpuId, /* thread ID */ 0);
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Fault fault = setupFetchRequest(ifetch_req);
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if (fault == NoFault) {
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if (!icachePort.sendTiming(ifetch_pkt)) {
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// Need to wait for retry
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_status = IcacheRetry;
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ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast);
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ifetch_pkt->dataStatic(&inst);
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if (fault == NoFault) {
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if (!icachePort.sendTiming(ifetch_pkt)) {
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// Need to wait for retry
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_status = IcacheRetry;
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} else {
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// Need to wait for cache to respond
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_status = IcacheWaitResponse;
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// ownership of packet transferred to memory system
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ifetch_pkt = NULL;
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}
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} else {
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// Need to wait for cache to respond
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_status = IcacheWaitResponse;
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// ownership of packet transferred to memory system
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ifetch_pkt = NULL;
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delete ifetch_req;
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delete ifetch_pkt;
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// fetch fault: advance directly to next instruction (fault handler)
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advanceInst(fault);
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}
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} else {
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delete ifetch_req;
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delete ifetch_pkt;
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// fetch fault: advance directly to next instruction (fault handler)
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advanceInst(fault);
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_status = IcacheWaitResponse;
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completeIfetch(NULL);
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}
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numCycles += tickToCycles(curTick - previousTick);
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@ -581,7 +588,8 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
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// received a response from the icache: execute the received
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// instruction
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assert(!pkt->isError());
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assert(!pkt || !pkt->isError());
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assert(_status == IcacheWaitResponse);
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_status = Running;
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@ -590,8 +598,10 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
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previousTick = curTick;
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if (getState() == SimObject::Draining) {
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delete pkt->req;
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delete pkt;
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if (pkt) {
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delete pkt->req;
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delete pkt;
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}
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completeDrain();
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return;
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@ -658,8 +668,10 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
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advanceInst(fault);
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}
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delete pkt->req;
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delete pkt;
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if (pkt) {
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delete pkt->req;
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delete pkt;
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}
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}
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void
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