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Configs: Set the memtest clock to a reasonable value

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This patch changes the memtest clock from 1THz (the default) to 2GHz,
similar to the CPUs in the other regressions. This is useful as the
caches will adopt the same clock as the CPU. The bus clock rate is
scaled accordingly, and the L1-L2 bus is kept at the CPU clock while
the memory bus is at half that frequency.

A separate patch updates the affected stats.
This commit is contained in:
Andreas Hansson 2012-10-15 08:09:57 -04:00
parent 54227f9e57
commit 072a91ee51
2 changed files with 4 additions and 4 deletions
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2
tests/configs/memtest-ruby.py
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@ -69,7 +69,7 @@ options.l3_assoc=2
nb_cores = 8 nb_cores = 8
# ruby does not support atomic, functional, or uncacheable accesses # ruby does not support atomic, functional, or uncacheable accesses
cpus = [ MemTest(atomic=False, percent_functional=50, cpus = [ MemTest(clock = '2GHz', atomic=False, percent_functional=50,
percent_uncacheable=0, suppress_func_warnings=True) \ percent_uncacheable=0, suppress_func_warnings=True) \
for i in xrange(nb_cores) ] for i in xrange(nb_cores) ]

6
tests/configs/memtest.py
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@ -55,16 +55,16 @@ class L2(BaseCache):
#MAX CORES IS 8 with the fals sharing method #MAX CORES IS 8 with the fals sharing method
nb_cores = 8 nb_cores = 8
cpus = [ MemTest() for i in xrange(nb_cores) ] cpus = [ MemTest(clock = '2GHz') for i in xrange(nb_cores) ]
# system simulated # system simulated
system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False), system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False),
funcbus = NoncoherentBus(), funcbus = NoncoherentBus(),
physmem = SimpleMemory(), physmem = SimpleMemory(),
membus = CoherentBus(clock="500GHz", width=16)) membus = CoherentBus(clock="1GHz", width=16))
# l2cache & bus # l2cache & bus
system.toL2Bus = CoherentBus(clock="500GHz", width=16) system.toL2Bus = CoherentBus(clock="2GHz", width=16)
system.l2c = L2(size='64kB', assoc=8) system.l2c = L2(size='64kB', assoc=8)
system.l2c.cpu_side = system.toL2Bus.master system.l2c.cpu_side = system.toL2Bus.master