Use O3DynInst in cpu_models.py and in static_inst_exec_sigs.hh instead of a specific ISA dyn. inst.

src/cpu/cpu_models.py:
    Use O3DynInst
src/cpu/o3/dyn_inst.hh:
    declare O3DynInst here based off of ISA ... this must be updated for each ISA.
src/cpu/static_inst.hh:
    take out O3 forward declarations here and include header file to keep this file clean

--HG--
extra : convert_revision : 0d65463479c3cfc2d1154935b1032dae32c5efd0
This commit is contained in:
Korey Sewell 2006-07-06 12:18:55 -04:00
parent 215041215b
commit 03fa13b27c
3 changed files with 13 additions and 12 deletions

View file

@ -80,5 +80,5 @@ CpuModel('CheckerCPU', 'checker_cpu_exec.cc',
'#include "cpu/checker/cpu.hh"', '#include "cpu/checker/cpu.hh"',
{ 'CPU_exec_context': 'CheckerCPU' }) { 'CPU_exec_context': 'CheckerCPU' })
CpuModel('O3CPU', 'o3_cpu_exec.cc', CpuModel('O3CPU', 'o3_cpu_exec.cc',
'#include "cpu/o3/alpha/dyn_inst.hh"', '#include "cpu/o3/isa_specific.hh"',
{ 'CPU_exec_context': 'AlphaDynInst<AlphaSimpleImpl>' }) { 'CPU_exec_context': 'O3DynInst' })

View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2004-2005 The Regents of The University of Michigan * Copyright (c) 2006 The Regents of The University of Michigan
* All rights reserved. * All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@ -25,15 +25,20 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
* Authors: Kevin Lim * Authors: Korey Sewell
*/ */
#ifndef __CPU_O3_DYN_INST_HH__ #ifndef __CPU_O3_DYN_INST_HH__
#define __CPU_O3_DYN_INST_HH__ #define __CPU_O3_DYN_INST_HH__
#include "cpu/o3/isa_specific.hh"
/** The O3Impl to be used. */ #if THE_ISA == ALPHA_ISA
typedef DynInst O3DynInst; template <class Impl>
class AlphaDynInst;
struct AlphaSimpleImpl;
typedef AlphaDynInst<AlphaSimpleImpl> O3DynInst;
#endif
#endif // __CPU_O3_DYN_INST_HH__ #endif // __CPU_O3_DYN_INST_HH__

View file

@ -39,6 +39,7 @@
#include "base/misc.hh" #include "base/misc.hh"
#include "base/refcnt.hh" #include "base/refcnt.hh"
#include "cpu/op_class.hh" #include "cpu/op_class.hh"
#include "cpu/o3/dyn_inst.hh"
#include "sim/host.hh" #include "sim/host.hh"
#include "arch/isa_traits.hh" #include "arch/isa_traits.hh"
@ -50,11 +51,6 @@ class ThreadContext;
class DynInst; class DynInst;
class Packet; class Packet;
template <class Impl>
class AlphaDynInst;
//class O3DynInst;
template <class Impl> template <class Impl>
class OzoneDynInst; class OzoneDynInst;