Move IntrFlag into the MiscRegFile and get rid of specialized accessor functions.
--HG-- extra : convert_revision : e0d12a150b01d05de9bc02bcbc7c22797975a5b9
This commit is contained in:
parent
4862879a94
commit
038217049a
|
@ -661,12 +661,12 @@ decode OPCODE default Unknown::unknown() {
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
format BasicOperate {
|
format BasicOperate {
|
||||||
0xe000: rc({{
|
0xe000: rc({{
|
||||||
Ra = xc->readIntrFlag();
|
Ra = IntrFlag;
|
||||||
xc->setIntrFlag(0);
|
IntrFlag = 0;
|
||||||
}}, IsNonSpeculative, IsUnverifiable);
|
}}, IsNonSpeculative, IsUnverifiable);
|
||||||
0xf000: rs({{
|
0xf000: rs({{
|
||||||
Ra = xc->readIntrFlag();
|
Ra = IntrFlag;
|
||||||
xc->setIntrFlag(1);
|
IntrFlag = 1;
|
||||||
}}, IsNonSpeculative, IsUnverifiable);
|
}}, IsNonSpeculative, IsUnverifiable);
|
||||||
}
|
}
|
||||||
#else
|
#else
|
||||||
|
|
|
@ -183,8 +183,9 @@ def operands {{
|
||||||
'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
|
'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
|
||||||
'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
|
'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
|
||||||
'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
|
'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
|
||||||
'Runiq': ('ControlReg', 'uq', 'TheISA::Uniq_DepTag', None, 1),
|
'Runiq': ('ControlReg', 'uq', 'AlphaISA::Uniq_DepTag', None, 1),
|
||||||
'FPCR': (' ControlReg', 'uq', 'TheISA::Fpcr_DepTag', None, 1),
|
'FPCR': ('ControlReg', 'uq', 'AlphaISA::Fpcr_DepTag', None, 1),
|
||||||
|
'IntrFlag': ('ControlReg', 'uq', 'AlphaISA::Intr_Flag_DepTag', None, 1),
|
||||||
# The next two are hacks for non-full-system call-pal emulation
|
# The next two are hacks for non-full-system call-pal emulation
|
||||||
'R0': ('IntReg', 'uq', '0', None, 1),
|
'R0': ('IntReg', 'uq', '0', None, 1),
|
||||||
'R16': ('IntReg', 'uq', '16', None, 1),
|
'R16': ('IntReg', 'uq', '16', None, 1),
|
||||||
|
|
|
@ -54,7 +54,8 @@ namespace AlphaISA
|
||||||
Uniq_DepTag = 73,
|
Uniq_DepTag = 73,
|
||||||
Lock_Flag_DepTag = 74,
|
Lock_Flag_DepTag = 74,
|
||||||
Lock_Addr_DepTag = 75,
|
Lock_Addr_DepTag = 75,
|
||||||
IPR_Base_DepTag = 76
|
Intr_Flag_DepTag = 76,
|
||||||
|
IPR_Base_DepTag = 77
|
||||||
};
|
};
|
||||||
|
|
||||||
StaticInstPtr decodeInst(ExtMachInst);
|
StaticInstPtr decodeInst(ExtMachInst);
|
||||||
|
|
|
@ -109,6 +109,7 @@ namespace AlphaISA
|
||||||
uint64_t uniq; // process-unique register
|
uint64_t uniq; // process-unique register
|
||||||
bool lock_flag; // lock flag for LL/SC
|
bool lock_flag; // lock flag for LL/SC
|
||||||
Addr lock_addr; // lock address for LL/SC
|
Addr lock_addr; // lock address for LL/SC
|
||||||
|
int intr_flag;
|
||||||
|
|
||||||
public:
|
public:
|
||||||
MiscReg readReg(int misc_reg);
|
MiscReg readReg(int misc_reg);
|
||||||
|
@ -131,6 +132,7 @@ namespace AlphaISA
|
||||||
fpcr = uniq = 0;
|
fpcr = uniq = 0;
|
||||||
lock_flag = 0;
|
lock_flag = 0;
|
||||||
lock_addr = 0;
|
lock_addr = 0;
|
||||||
|
intr_flag = 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
void serialize(std::ostream &os);
|
void serialize(std::ostream &os);
|
||||||
|
|
|
@ -328,8 +328,6 @@ class CheckerCPU : public BaseCPU
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
Fault hwrei() { return thread->hwrei(); }
|
Fault hwrei() { return thread->hwrei(); }
|
||||||
int readIntrFlag() { return thread->readIntrFlag(); }
|
|
||||||
void setIntrFlag(int val) { thread->setIntrFlag(val); }
|
|
||||||
bool inPalMode() { return thread->inPalMode(); }
|
bool inPalMode() { return thread->inPalMode(); }
|
||||||
void ev5_trap(Fault fault) { fault->invoke(tc); }
|
void ev5_trap(Fault fault) { fault->invoke(tc); }
|
||||||
bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
|
bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
|
||||||
|
|
|
@ -144,10 +144,6 @@ class ExecContext {
|
||||||
/** Somewhat Alpha-specific function that handles returning from
|
/** Somewhat Alpha-specific function that handles returning from
|
||||||
* an error or interrupt. */
|
* an error or interrupt. */
|
||||||
Fault hwrei();
|
Fault hwrei();
|
||||||
/** Reads the interrupt flags. */
|
|
||||||
int readIntrFlag();
|
|
||||||
/** Sets the interrupt flags to a value. */
|
|
||||||
void setIntrFlag(int val);
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Check for special simulator handling of specific PAL calls. If
|
* Check for special simulator handling of specific PAL calls. If
|
||||||
|
|
|
@ -145,10 +145,6 @@ class AlphaO3CPU : public FullO3CPU<Impl>
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
/** Posts an interrupt. */
|
/** Posts an interrupt. */
|
||||||
void post_interrupt(int int_num, int index);
|
void post_interrupt(int int_num, int index);
|
||||||
/** Reads the interrupt flag. */
|
|
||||||
int readIntrFlag();
|
|
||||||
/** Sets the interrupt flags. */
|
|
||||||
void setIntrFlag(int val);
|
|
||||||
/** HW return from error interrupt. */
|
/** HW return from error interrupt. */
|
||||||
Fault hwrei(unsigned tid);
|
Fault hwrei(unsigned tid);
|
||||||
/** Returns if a specific PC is a PAL mode PC. */
|
/** Returns if a specific PC is a PAL mode PC. */
|
||||||
|
|
|
@ -241,20 +241,6 @@ AlphaO3CPU<Impl>::post_interrupt(int int_num, int index)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
template <class Impl>
|
|
||||||
int
|
|
||||||
AlphaO3CPU<Impl>::readIntrFlag()
|
|
||||||
{
|
|
||||||
return this->regFile.readIntrFlag();
|
|
||||||
}
|
|
||||||
|
|
||||||
template <class Impl>
|
|
||||||
void
|
|
||||||
AlphaO3CPU<Impl>::setIntrFlag(int val)
|
|
||||||
{
|
|
||||||
this->regFile.setIntrFlag(val);
|
|
||||||
}
|
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
Fault
|
Fault
|
||||||
AlphaO3CPU<Impl>::hwrei(unsigned tid)
|
AlphaO3CPU<Impl>::hwrei(unsigned tid)
|
||||||
|
|
|
@ -127,20 +127,6 @@ AlphaDynInst<Impl>::hwrei()
|
||||||
return NoFault;
|
return NoFault;
|
||||||
}
|
}
|
||||||
|
|
||||||
template <class Impl>
|
|
||||||
int
|
|
||||||
AlphaDynInst<Impl>::readIntrFlag()
|
|
||||||
{
|
|
||||||
return this->cpu->readIntrFlag();
|
|
||||||
}
|
|
||||||
|
|
||||||
template <class Impl>
|
|
||||||
void
|
|
||||||
AlphaDynInst<Impl>::setIntrFlag(int val)
|
|
||||||
{
|
|
||||||
this->cpu->setIntrFlag(val);
|
|
||||||
}
|
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
bool
|
bool
|
||||||
AlphaDynInst<Impl>::inPalMode()
|
AlphaDynInst<Impl>::inPalMode()
|
||||||
|
|
|
@ -251,12 +251,6 @@ class PhysRegFile
|
||||||
cpu->tcBase(thread_id));
|
cpu->tcBase(thread_id));
|
||||||
}
|
}
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
|
||||||
int readIntrFlag() { return intrflag; }
|
|
||||||
/** Sets an interrupt flag. */
|
|
||||||
void setIntrFlag(int val) { intrflag = val; }
|
|
||||||
#endif
|
|
||||||
|
|
||||||
public:
|
public:
|
||||||
/** (signed) integer register file. */
|
/** (signed) integer register file. */
|
||||||
IntReg *intRegFile;
|
IntReg *intRegFile;
|
||||||
|
|
|
@ -583,8 +583,6 @@ class OzoneCPU : public BaseCPU
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
Fault hwrei();
|
Fault hwrei();
|
||||||
int readIntrFlag() { return thread.intrflag; }
|
|
||||||
void setIntrFlag(int val) { thread.intrflag = val; }
|
|
||||||
bool inPalMode() { return AlphaISA::PcPAL(thread.PC); }
|
bool inPalMode() { return AlphaISA::PcPAL(thread.PC); }
|
||||||
bool inPalMode(Addr pc) { return AlphaISA::PcPAL(pc); }
|
bool inPalMode(Addr pc) { return AlphaISA::PcPAL(pc); }
|
||||||
bool simPalCheck(int palFunc);
|
bool simPalCheck(int palFunc);
|
||||||
|
|
|
@ -238,8 +238,6 @@ class OzoneDynInst : public BaseDynInst<Impl>
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
Fault hwrei();
|
Fault hwrei();
|
||||||
int readIntrFlag();
|
|
||||||
void setIntrFlag(int val);
|
|
||||||
bool inPalMode();
|
bool inPalMode();
|
||||||
void trap(Fault fault);
|
void trap(Fault fault);
|
||||||
bool simPalCheck(int palFunc);
|
bool simPalCheck(int palFunc);
|
||||||
|
|
|
@ -260,20 +260,6 @@ OzoneDynInst<Impl>::hwrei()
|
||||||
return NoFault;
|
return NoFault;
|
||||||
}
|
}
|
||||||
|
|
||||||
template <class Impl>
|
|
||||||
int
|
|
||||||
OzoneDynInst<Impl>::readIntrFlag()
|
|
||||||
{
|
|
||||||
return this->cpu->readIntrFlag();
|
|
||||||
}
|
|
||||||
|
|
||||||
template <class Impl>
|
|
||||||
void
|
|
||||||
OzoneDynInst<Impl>::setIntrFlag(int val)
|
|
||||||
{
|
|
||||||
this->cpu->setIntrFlag(val);
|
|
||||||
}
|
|
||||||
|
|
||||||
template <class Impl>
|
template <class Impl>
|
||||||
bool
|
bool
|
||||||
OzoneDynInst<Impl>::inPalMode()
|
OzoneDynInst<Impl>::inPalMode()
|
||||||
|
|
|
@ -305,8 +305,6 @@ class BaseSimpleCPU : public BaseCPU
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
Fault hwrei() { return thread->hwrei(); }
|
Fault hwrei() { return thread->hwrei(); }
|
||||||
int readIntrFlag() { return thread->readIntrFlag(); }
|
|
||||||
void setIntrFlag(int val) { thread->setIntrFlag(val); }
|
|
||||||
bool inPalMode() { return thread->inPalMode(); }
|
bool inPalMode() { return thread->inPalMode(); }
|
||||||
void ev5_trap(Fault fault) { fault->invoke(tc); }
|
void ev5_trap(Fault fault) { fault->invoke(tc); }
|
||||||
bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
|
bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
|
||||||
|
|
|
@ -168,8 +168,6 @@ class SimpleThread : public ThreadState
|
||||||
|
|
||||||
void dumpFuncProfile();
|
void dumpFuncProfile();
|
||||||
|
|
||||||
int readIntrFlag() { return regs.intrflag; }
|
|
||||||
void setIntrFlag(int val) { regs.intrflag = val; }
|
|
||||||
Fault hwrei();
|
Fault hwrei();
|
||||||
|
|
||||||
bool simPalCheck(int palFunc);
|
bool simPalCheck(int palFunc);
|
||||||
|
|
Loading…
Reference in a new issue