diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa index 5bd19b677..93b941d72 100644 --- a/src/arch/alpha/isa/decoder.isa +++ b/src/arch/alpha/isa/decoder.isa @@ -661,12 +661,12 @@ decode OPCODE default Unknown::unknown() { #if FULL_SYSTEM format BasicOperate { 0xe000: rc({{ - Ra = xc->readIntrFlag(); - xc->setIntrFlag(0); + Ra = IntrFlag; + IntrFlag = 0; }}, IsNonSpeculative, IsUnverifiable); 0xf000: rs({{ - Ra = xc->readIntrFlag(); - xc->setIntrFlag(1); + Ra = IntrFlag; + IntrFlag = 1; }}, IsNonSpeculative, IsUnverifiable); } #else diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa index 2024b1117..1df6ac603 100644 --- a/src/arch/alpha/isa/main.isa +++ b/src/arch/alpha/isa/main.isa @@ -183,8 +183,9 @@ def operands {{ 'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3), 'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4), 'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4), - 'Runiq': ('ControlReg', 'uq', 'TheISA::Uniq_DepTag', None, 1), - 'FPCR': (' ControlReg', 'uq', 'TheISA::Fpcr_DepTag', None, 1), + 'Runiq': ('ControlReg', 'uq', 'AlphaISA::Uniq_DepTag', None, 1), + 'FPCR': ('ControlReg', 'uq', 'AlphaISA::Fpcr_DepTag', None, 1), + 'IntrFlag': ('ControlReg', 'uq', 'AlphaISA::Intr_Flag_DepTag', None, 1), # The next two are hacks for non-full-system call-pal emulation 'R0': ('IntReg', 'uq', '0', None, 1), 'R16': ('IntReg', 'uq', '16', None, 1), diff --git a/src/arch/alpha/isa_traits.hh b/src/arch/alpha/isa_traits.hh index 4f439b8df..66cb21235 100644 --- a/src/arch/alpha/isa_traits.hh +++ b/src/arch/alpha/isa_traits.hh @@ -54,7 +54,8 @@ namespace AlphaISA Uniq_DepTag = 73, Lock_Flag_DepTag = 74, Lock_Addr_DepTag = 75, - IPR_Base_DepTag = 76 + Intr_Flag_DepTag = 76, + IPR_Base_DepTag = 77 }; StaticInstPtr decodeInst(ExtMachInst); diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh index 43b48a0ab..ea6fc67b2 100644 --- a/src/arch/alpha/regfile.hh +++ b/src/arch/alpha/regfile.hh @@ -109,6 +109,7 @@ namespace AlphaISA uint64_t uniq; // process-unique register bool lock_flag; // lock flag for LL/SC Addr lock_addr; // lock address for LL/SC + int intr_flag; public: MiscReg readReg(int misc_reg); @@ -131,6 +132,7 @@ namespace AlphaISA fpcr = uniq = 0; lock_flag = 0; lock_addr = 0; + intr_flag = 0; } void serialize(std::ostream &os); diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index 00b01171f..7c01bdc39 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -328,8 +328,6 @@ class CheckerCPU : public BaseCPU #if FULL_SYSTEM Fault hwrei() { return thread->hwrei(); } - int readIntrFlag() { return thread->readIntrFlag(); } - void setIntrFlag(int val) { thread->setIntrFlag(val); } bool inPalMode() { return thread->inPalMode(); } void ev5_trap(Fault fault) { fault->invoke(tc); } bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh index f6e8d7c25..e28b33193 100644 --- a/src/cpu/exec_context.hh +++ b/src/cpu/exec_context.hh @@ -144,10 +144,6 @@ class ExecContext { /** Somewhat Alpha-specific function that handles returning from * an error or interrupt. */ Fault hwrei(); - /** Reads the interrupt flags. */ - int readIntrFlag(); - /** Sets the interrupt flags to a value. */ - void setIntrFlag(int val); /** * Check for special simulator handling of specific PAL calls. If diff --git a/src/cpu/o3/alpha/cpu.hh b/src/cpu/o3/alpha/cpu.hh index 9d97f9701..474fce02a 100644 --- a/src/cpu/o3/alpha/cpu.hh +++ b/src/cpu/o3/alpha/cpu.hh @@ -145,10 +145,6 @@ class AlphaO3CPU : public FullO3CPU #if FULL_SYSTEM /** Posts an interrupt. */ void post_interrupt(int int_num, int index); - /** Reads the interrupt flag. */ - int readIntrFlag(); - /** Sets the interrupt flags. */ - void setIntrFlag(int val); /** HW return from error interrupt. */ Fault hwrei(unsigned tid); /** Returns if a specific PC is a PAL mode PC. */ diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh index b7362fad9..a57c5d9ed 100644 --- a/src/cpu/o3/alpha/cpu_impl.hh +++ b/src/cpu/o3/alpha/cpu_impl.hh @@ -241,20 +241,6 @@ AlphaO3CPU::post_interrupt(int int_num, int index) } } -template -int -AlphaO3CPU::readIntrFlag() -{ - return this->regFile.readIntrFlag(); -} - -template -void -AlphaO3CPU::setIntrFlag(int val) -{ - this->regFile.setIntrFlag(val); -} - template Fault AlphaO3CPU::hwrei(unsigned tid) diff --git a/src/cpu/o3/alpha/dyn_inst_impl.hh b/src/cpu/o3/alpha/dyn_inst_impl.hh index b273a7b9b..f27cd5961 100644 --- a/src/cpu/o3/alpha/dyn_inst_impl.hh +++ b/src/cpu/o3/alpha/dyn_inst_impl.hh @@ -127,20 +127,6 @@ AlphaDynInst::hwrei() return NoFault; } -template -int -AlphaDynInst::readIntrFlag() -{ - return this->cpu->readIntrFlag(); -} - -template -void -AlphaDynInst::setIntrFlag(int val) -{ - this->cpu->setIntrFlag(val); -} - template bool AlphaDynInst::inPalMode() diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh index 512cf0721..10f6db390 100644 --- a/src/cpu/o3/regfile.hh +++ b/src/cpu/o3/regfile.hh @@ -251,12 +251,6 @@ class PhysRegFile cpu->tcBase(thread_id)); } -#if FULL_SYSTEM - int readIntrFlag() { return intrflag; } - /** Sets an interrupt flag. */ - void setIntrFlag(int val) { intrflag = val; } -#endif - public: /** (signed) integer register file. */ IntReg *intRegFile; diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh index 70ec1d101..bd46b198b 100644 --- a/src/cpu/ozone/cpu.hh +++ b/src/cpu/ozone/cpu.hh @@ -583,8 +583,6 @@ class OzoneCPU : public BaseCPU #if FULL_SYSTEM Fault hwrei(); - int readIntrFlag() { return thread.intrflag; } - void setIntrFlag(int val) { thread.intrflag = val; } bool inPalMode() { return AlphaISA::PcPAL(thread.PC); } bool inPalMode(Addr pc) { return AlphaISA::PcPAL(pc); } bool simPalCheck(int palFunc); diff --git a/src/cpu/ozone/dyn_inst.hh b/src/cpu/ozone/dyn_inst.hh index e7390626e..d3871568a 100644 --- a/src/cpu/ozone/dyn_inst.hh +++ b/src/cpu/ozone/dyn_inst.hh @@ -238,8 +238,6 @@ class OzoneDynInst : public BaseDynInst #if FULL_SYSTEM Fault hwrei(); - int readIntrFlag(); - void setIntrFlag(int val); bool inPalMode(); void trap(Fault fault); bool simPalCheck(int palFunc); diff --git a/src/cpu/ozone/dyn_inst_impl.hh b/src/cpu/ozone/dyn_inst_impl.hh index 9d42ab05b..d86f2dc8b 100644 --- a/src/cpu/ozone/dyn_inst_impl.hh +++ b/src/cpu/ozone/dyn_inst_impl.hh @@ -260,20 +260,6 @@ OzoneDynInst::hwrei() return NoFault; } -template -int -OzoneDynInst::readIntrFlag() -{ -return this->cpu->readIntrFlag(); -} - -template -void -OzoneDynInst::setIntrFlag(int val) -{ - this->cpu->setIntrFlag(val); -} - template bool OzoneDynInst::inPalMode() diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index 1a9fc5127..1d208b8df 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -305,8 +305,6 @@ class BaseSimpleCPU : public BaseCPU #if FULL_SYSTEM Fault hwrei() { return thread->hwrei(); } - int readIntrFlag() { return thread->readIntrFlag(); } - void setIntrFlag(int val) { thread->setIntrFlag(val); } bool inPalMode() { return thread->inPalMode(); } void ev5_trap(Fault fault) { fault->invoke(tc); } bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index 10ec8faaa..d005b2914 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -168,8 +168,6 @@ class SimpleThread : public ThreadState void dumpFuncProfile(); - int readIntrFlag() { return regs.intrflag; } - void setIntrFlag(int val) { regs.intrflag = val; } Fault hwrei(); bool simPalCheck(int palFunc);