MEM: Fix master/slave ports in Ruby and non-regression scripts
This patch brings the Ruby and other scripts up to date with the introduction of the master/slave ports.
This commit is contained in:
parent
0d46708dc2
commit
00978170f3
13 changed files with 29 additions and 29 deletions
|
@ -195,8 +195,8 @@ if len(bm) == 2:
|
||||||
drive_sys.kernel = binary(options.kernel)
|
drive_sys.kernel = binary(options.kernel)
|
||||||
drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
|
drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
|
||||||
ranges = [AddrRange(bm[1].mem())])
|
ranges = [AddrRange(bm[1].mem())])
|
||||||
drive_sys.iobridge.slave = drive_sys.iobus.port
|
drive_sys.iobridge.slave = drive_sys.iobus.master
|
||||||
drive_sys.iobridge.master = drive_sys.membus.port
|
drive_sys.iobridge.master = drive_sys.membus.slave
|
||||||
|
|
||||||
drive_sys.init_param = options.init_param
|
drive_sys.init_param = options.init_param
|
||||||
root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
|
root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
|
||||||
|
|
|
@ -102,7 +102,7 @@ for ruby_port in system.ruby._cpu_ruby_ports:
|
||||||
#
|
#
|
||||||
# Tie the ruby tester ports to the ruby cpu ports
|
# Tie the ruby tester ports to the ruby cpu ports
|
||||||
#
|
#
|
||||||
system.tester.cpuPort = ruby_port.port
|
system.tester.cpuPort = ruby_port.slave
|
||||||
|
|
||||||
# -----------------------
|
# -----------------------
|
||||||
# run simulation
|
# run simulation
|
||||||
|
|
|
@ -125,11 +125,11 @@ for (i, cpu) in enumerate(system.cpu):
|
||||||
#
|
#
|
||||||
# Tie the cpu ports to the correct ruby system ports
|
# Tie the cpu ports to the correct ruby system ports
|
||||||
#
|
#
|
||||||
cpu.icache_port = system.ruby._cpu_ruby_ports[i].port
|
cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave
|
||||||
cpu.dcache_port = system.ruby._cpu_ruby_ports[i].port
|
cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave
|
||||||
if buildEnv['TARGET_ISA'] == "x86":
|
if buildEnv['TARGET_ISA'] == "x86":
|
||||||
cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].port
|
cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].slave
|
||||||
cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].port
|
cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave
|
||||||
cpu.interrupts.pio = system.piobus.master
|
cpu.interrupts.pio = system.piobus.master
|
||||||
cpu.interrupts.int_master = system.piobus.slave
|
cpu.interrupts.int_master = system.piobus.slave
|
||||||
cpu.interrupts.int_slave = system.piobus.master
|
cpu.interrupts.int_slave = system.piobus.master
|
||||||
|
|
|
@ -133,7 +133,7 @@ for (i, cpu) in enumerate(cpus):
|
||||||
#
|
#
|
||||||
# Tie the cpu memtester ports to the correct system ports
|
# Tie the cpu memtester ports to the correct system ports
|
||||||
#
|
#
|
||||||
cpu.test = system.ruby._cpu_ruby_ports[i].port
|
cpu.test = system.ruby._cpu_ruby_ports[i].slave
|
||||||
cpu.functional = system.funcmem.port
|
cpu.functional = system.funcmem.port
|
||||||
|
|
||||||
#
|
#
|
||||||
|
|
|
@ -109,7 +109,7 @@ for ruby_port in system.ruby._cpu_ruby_ports:
|
||||||
#
|
#
|
||||||
# Tie the cpu test ports to the ruby cpu port
|
# Tie the cpu test ports to the ruby cpu port
|
||||||
#
|
#
|
||||||
cpus[i].test = ruby_port.port
|
cpus[i].test = ruby_port.slave
|
||||||
ruby_port.access_phys_mem = False
|
ruby_port.access_phys_mem = False
|
||||||
|
|
||||||
i += 1
|
i += 1
|
||||||
|
|
|
@ -110,7 +110,7 @@ for ruby_port in system.ruby._cpu_ruby_ports:
|
||||||
#
|
#
|
||||||
# Tie the ruby tester ports to the ruby cpu ports
|
# Tie the ruby tester ports to the ruby cpu ports
|
||||||
#
|
#
|
||||||
tester.cpuPort = ruby_port.port
|
tester.cpuPort = ruby_port.slave
|
||||||
|
|
||||||
#
|
#
|
||||||
# Tell each sequencer this is the ruby tester so that it
|
# Tell each sequencer this is the ruby tester so that it
|
||||||
|
|
|
@ -190,8 +190,8 @@ for i in xrange(np):
|
||||||
system.cpu[i].workload = multiprocesses[i]
|
system.cpu[i].workload = multiprocesses[i]
|
||||||
|
|
||||||
if options.ruby:
|
if options.ruby:
|
||||||
system.cpu[i].icache_port = system.ruby._cpu_ruby_ports[i].port
|
system.cpu[i].icache_port = system.ruby._cpu_ruby_ports[i].slave
|
||||||
system.cpu[i].dcache_port = system.ruby._cpu_ruby_ports[i].port
|
system.cpu[i].dcache_port = system.ruby._cpu_ruby_ports[i].slave
|
||||||
|
|
||||||
if options.fastmem:
|
if options.fastmem:
|
||||||
system.cpu[0].physmem_port = system.physmem.port
|
system.cpu[0].physmem_port = system.physmem.port
|
||||||
|
|
|
@ -103,7 +103,7 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
|
||||||
l1_cntrl.sequencer = cpu_seq
|
l1_cntrl.sequencer = cpu_seq
|
||||||
|
|
||||||
if piobus != None:
|
if piobus != None:
|
||||||
cpu_seq.pio_port = piobus.port
|
cpu_seq.pio_port = piobus.slave
|
||||||
|
|
||||||
exec("system.l1_cntrl%d = l1_cntrl" % i)
|
exec("system.l1_cntrl%d = l1_cntrl" % i)
|
||||||
|
|
||||||
|
@ -180,9 +180,9 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
|
||||||
|
|
||||||
exec("system.dma_cntrl%d = dma_cntrl" % i)
|
exec("system.dma_cntrl%d = dma_cntrl" % i)
|
||||||
if dma_device.type == 'MemTest':
|
if dma_device.type == 'MemTest':
|
||||||
exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
|
exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" % i)
|
||||||
else:
|
else:
|
||||||
exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
|
exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
|
||||||
dma_cntrl_nodes.append(dma_cntrl)
|
dma_cntrl_nodes.append(dma_cntrl)
|
||||||
|
|
||||||
cntrl_count += 1
|
cntrl_count += 1
|
||||||
|
|
|
@ -95,7 +95,7 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
|
||||||
l1_cntrl.sequencer = cpu_seq
|
l1_cntrl.sequencer = cpu_seq
|
||||||
|
|
||||||
if piobus != None:
|
if piobus != None:
|
||||||
cpu_seq.pio_port = piobus.port
|
cpu_seq.pio_port = piobus.slave
|
||||||
|
|
||||||
exec("system.l1_cntrl%d = l1_cntrl" % i)
|
exec("system.l1_cntrl%d = l1_cntrl" % i)
|
||||||
#
|
#
|
||||||
|
@ -153,10 +153,10 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
|
||||||
|
|
||||||
exec("system.dma_cntrl%d = dma_cntrl" % i)
|
exec("system.dma_cntrl%d = dma_cntrl" % i)
|
||||||
if dma_device.type == 'MemTest':
|
if dma_device.type == 'MemTest':
|
||||||
exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
|
exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" % i)
|
||||||
else:
|
else:
|
||||||
exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
|
exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
|
||||||
dma_cntrl.dma_sequencer.port = dma_device.dma
|
dma_cntrl.dma_sequencer.slave = dma_device.dma
|
||||||
dma_cntrl_nodes.append(dma_cntrl)
|
dma_cntrl_nodes.append(dma_cntrl)
|
||||||
|
|
||||||
cntrl_count += 1
|
cntrl_count += 1
|
||||||
|
|
|
@ -103,7 +103,7 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
|
||||||
l1_cntrl.sequencer = cpu_seq
|
l1_cntrl.sequencer = cpu_seq
|
||||||
|
|
||||||
if piobus != None:
|
if piobus != None:
|
||||||
cpu_seq.pio_port = piobus.port
|
cpu_seq.pio_port = piobus.slave
|
||||||
|
|
||||||
exec("system.l1_cntrl%d = l1_cntrl" % i)
|
exec("system.l1_cntrl%d = l1_cntrl" % i)
|
||||||
#
|
#
|
||||||
|
@ -177,9 +177,9 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
|
||||||
|
|
||||||
exec("system.dma_cntrl%d = dma_cntrl" % i)
|
exec("system.dma_cntrl%d = dma_cntrl" % i)
|
||||||
if dma_device.type == 'MemTest':
|
if dma_device.type == 'MemTest':
|
||||||
exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
|
exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" % i)
|
||||||
else:
|
else:
|
||||||
exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
|
exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
|
||||||
dma_cntrl_nodes.append(dma_cntrl)
|
dma_cntrl_nodes.append(dma_cntrl)
|
||||||
|
|
||||||
cntrl_count += 1
|
cntrl_count += 1
|
||||||
|
|
|
@ -125,7 +125,7 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
|
||||||
l1_cntrl.sequencer = cpu_seq
|
l1_cntrl.sequencer = cpu_seq
|
||||||
|
|
||||||
if piobus != None:
|
if piobus != None:
|
||||||
cpu_seq.pio_port = piobus.port
|
cpu_seq.pio_port = piobus.slave
|
||||||
|
|
||||||
exec("system.l1_cntrl%d = l1_cntrl" % i)
|
exec("system.l1_cntrl%d = l1_cntrl" % i)
|
||||||
#
|
#
|
||||||
|
@ -201,9 +201,9 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
|
||||||
|
|
||||||
exec("system.dma_cntrl%d = dma_cntrl" % i)
|
exec("system.dma_cntrl%d = dma_cntrl" % i)
|
||||||
if dma_device.type == 'MemTest':
|
if dma_device.type == 'MemTest':
|
||||||
exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
|
exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" % i)
|
||||||
else:
|
else:
|
||||||
exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
|
exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
|
||||||
dma_cntrl_nodes.append(dma_cntrl)
|
dma_cntrl_nodes.append(dma_cntrl)
|
||||||
|
|
||||||
cntrl_count += 1
|
cntrl_count += 1
|
||||||
|
|
|
@ -118,7 +118,7 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
|
||||||
l1_cntrl.sequencer = cpu_seq
|
l1_cntrl.sequencer = cpu_seq
|
||||||
|
|
||||||
if piobus != None:
|
if piobus != None:
|
||||||
cpu_seq.pio_port = piobus.port
|
cpu_seq.pio_port = piobus.slave
|
||||||
|
|
||||||
if options.recycle_latency:
|
if options.recycle_latency:
|
||||||
l1_cntrl.recycle_latency = options.recycle_latency
|
l1_cntrl.recycle_latency = options.recycle_latency
|
||||||
|
@ -213,9 +213,9 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
|
||||||
|
|
||||||
exec("system.dma_cntrl%d = dma_cntrl" % i)
|
exec("system.dma_cntrl%d = dma_cntrl" % i)
|
||||||
if dma_device.type == 'MemTest':
|
if dma_device.type == 'MemTest':
|
||||||
exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
|
exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" % i)
|
||||||
else:
|
else:
|
||||||
exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
|
exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
|
||||||
dma_cntrl_nodes.append(dma_cntrl)
|
dma_cntrl_nodes.append(dma_cntrl)
|
||||||
|
|
||||||
if options.recycle_latency:
|
if options.recycle_latency:
|
||||||
|
|
|
@ -96,7 +96,7 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
|
||||||
l1_cntrl.sequencer = cpu_seq
|
l1_cntrl.sequencer = cpu_seq
|
||||||
|
|
||||||
if piobus != None:
|
if piobus != None:
|
||||||
cpu_seq.pio_port = piobus.port
|
cpu_seq.pio_port = piobus.slave
|
||||||
|
|
||||||
exec("system.l1_cntrl%d = l1_cntrl" % i)
|
exec("system.l1_cntrl%d = l1_cntrl" % i)
|
||||||
#
|
#
|
||||||
|
|
Loading…
Reference in a new issue