2004-11-13 23:10:48 +01:00
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/*
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2005-06-05 11:16:00 +02:00
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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2004-11-13 23:10:48 +01:00
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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2006-06-01 01:26:56 +02:00
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*
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* Authors: Nathan Binkert
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2004-11-13 23:10:48 +01:00
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*/
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#ifndef __DEV_SINIC_HH__
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#define __DEV_SINIC_HH__
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#include "base/inet.hh"
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#include "base/statistics.hh"
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2012-11-02 17:32:01 +01:00
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#include "dev/etherdevice.hh"
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2004-11-13 23:10:48 +01:00
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#include "dev/etherint.hh"
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#include "dev/etherpkt.hh"
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#include "dev/io_device.hh"
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#include "dev/pcidev.hh"
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#include "dev/pktfifo.hh"
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#include "dev/sinicreg.hh"
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2007-07-24 06:51:38 +02:00
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#include "params/Sinic.hh"
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2004-11-13 23:10:48 +01:00
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#include "sim/eventq.hh"
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namespace Sinic {
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class Interface;
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2012-11-02 17:32:01 +01:00
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class Base : public EtherDevBase
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2004-11-13 23:10:48 +01:00
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{
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protected:
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bool rxEnable;
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bool txEnable;
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protected:
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Tick intrDelay;
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Tick intrTick;
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bool cpuIntrEnable;
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bool cpuPendingIntr;
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void cpuIntrPost(Tick when);
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void cpuInterrupt();
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void cpuIntrClear();
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typedef EventWrapper<Base, &Base::cpuInterrupt> IntrEvent;
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2005-01-15 00:34:56 +01:00
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friend void IntrEvent::process();
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2004-11-13 23:10:48 +01:00
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IntrEvent *intrEvent;
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Interface *interface;
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bool cpuIntrPending() const;
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void cpuIntrAck() { cpuIntrClear(); }
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/**
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* Serialization stuff
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*/
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public:
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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/**
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* Construction/Destruction/Parameters
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*/
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public:
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2007-07-24 06:51:38 +02:00
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typedef SinicParams Params;
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const Params *params() const { return (const Params *)_params; }
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2007-08-16 22:49:02 +02:00
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Base(const Params *p);
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2004-11-13 23:10:48 +01:00
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};
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class Device : public Base
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{
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protected:
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/** Receive State Machine States */
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enum RxState {
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rxIdle,
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rxFifoBlock,
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rxBeginCopy,
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rxCopy,
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rxCopyDone
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};
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/** Transmit State Machine states */
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enum TxState {
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txIdle,
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txFifoBlock,
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txBeginCopy,
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txCopy,
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txCopyDone
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};
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/** device register file */
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struct {
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Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
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uint32_t Config; // 0x00
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uint32_t Command; // 0x04
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uint32_t IntrStatus; // 0x08
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uint32_t IntrMask; // 0x0c
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uint32_t RxMaxCopy; // 0x10
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uint32_t TxMaxCopy; // 0x14
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2008-10-09 13:58:23 +02:00
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uint32_t ZeroCopySize; // 0x18
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uint32_t ZeroCopyMark; // 0x1c
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uint32_t VirtualCount; // 0x20
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uint32_t RxMaxIntr; // 0x24
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uint32_t RxFifoSize; // 0x28
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uint32_t TxFifoSize; // 0x2c
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uint32_t RxFifoLow; // 0x30
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uint32_t TxFifoLow; // 0x34
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uint32_t RxFifoHigh; // 0x38
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uint32_t TxFifoHigh; // 0x3c
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uint64_t RxData; // 0x40
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uint64_t RxDone; // 0x48
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uint64_t RxWait; // 0x50
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uint64_t TxData; // 0x58
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uint64_t TxDone; // 0x60
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uint64_t TxWait; // 0x68
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uint64_t HwAddr; // 0x70
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uint64_t RxStatus; // 0x78
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2004-11-13 23:10:48 +01:00
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} regs;
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2005-11-25 19:33:36 +01:00
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struct VirtualReg {
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uint64_t RxData;
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uint64_t RxDone;
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uint64_t TxData;
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uint64_t TxDone;
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2008-10-09 13:58:23 +02:00
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PacketFifo::iterator rxIndex;
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2009-06-05 08:21:12 +02:00
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unsigned rxPacketOffset;
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unsigned rxPacketBytes;
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2005-11-25 19:33:36 +01:00
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uint64_t rxDoneData;
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2006-04-26 23:52:33 +02:00
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Counter rxUnique;
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Counter txUnique;
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2005-11-25 19:33:36 +01:00
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VirtualReg()
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: RxData(0), RxDone(0), TxData(0), TxDone(0),
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rxPacketOffset(0), rxPacketBytes(0), rxDoneData(0)
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{ }
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};
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typedef std::vector<VirtualReg> VirtualRegs;
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2009-06-05 08:21:12 +02:00
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typedef std::list<unsigned> VirtualList;
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2006-04-26 23:52:33 +02:00
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Counter rxUnique;
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Counter txUnique;
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2005-11-25 19:33:36 +01:00
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VirtualRegs virtualRegs;
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VirtualList rxList;
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2006-04-26 23:52:33 +02:00
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VirtualList rxBusy;
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int rxActive;
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2005-11-25 19:33:36 +01:00
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VirtualList txList;
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2008-10-09 13:58:23 +02:00
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int rxBusyCount;
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int rxMappedCount;
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int rxDirtyCount;
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Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
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uint8_t ®Data8(Addr daddr) { return *((uint8_t *)®s + daddr); }
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uint32_t ®Data32(Addr daddr) { return *(uint32_t *)®Data8(daddr); }
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uint64_t ®Data64(Addr daddr) { return *(uint64_t *)®Data8(daddr); }
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2004-11-13 23:10:48 +01:00
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protected:
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RxState rxState;
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PacketFifo rxFifo;
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2005-11-25 19:33:36 +01:00
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PacketFifo::iterator rxFifoPtr;
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Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
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bool rxEmpty;
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2006-04-26 23:52:33 +02:00
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bool rxLow;
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2004-11-13 23:10:48 +01:00
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Addr rxDmaAddr;
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uint8_t *rxDmaData;
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2009-06-05 08:21:12 +02:00
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unsigned rxDmaLen;
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2004-11-13 23:10:48 +01:00
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TxState txState;
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PacketFifo txFifo;
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Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
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bool txFull;
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2006-04-25 01:31:50 +02:00
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EthPacketPtr txPacket;
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2005-11-25 19:33:36 +01:00
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int txPacketOffset;
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int txPacketBytes;
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2004-11-13 23:10:48 +01:00
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Addr txDmaAddr;
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uint8_t *txDmaData;
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int txDmaLen;
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protected:
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void reset();
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void rxKick();
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Tick rxKickTick;
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typedef EventWrapper<Device, &Device::rxKick> RxKickEvent;
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2005-01-15 00:34:56 +01:00
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friend void RxKickEvent::process();
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2004-11-13 23:10:48 +01:00
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void txKick();
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Tick txKickTick;
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typedef EventWrapper<Device, &Device::txKick> TxKickEvent;
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2005-01-15 00:34:56 +01:00
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friend void TxKickEvent::process();
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2004-11-13 23:10:48 +01:00
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/**
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* Retransmit event
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*/
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void transmit();
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void txEventTransmit()
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{
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transmit();
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if (txState == txFifoBlock)
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txKick();
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}
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typedef EventWrapper<Device, &Device::txEventTransmit> TxEvent;
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2005-01-15 00:34:56 +01:00
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friend void TxEvent::process();
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2004-11-13 23:10:48 +01:00
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|
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TxEvent txEvent;
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|
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void txDump() const;
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|
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void rxDump() const;
|
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/**
|
|
|
|
* receive address filter
|
|
|
|
*/
|
2006-04-25 01:31:50 +02:00
|
|
|
bool rxFilter(const EthPacketPtr &packet);
|
2004-11-13 23:10:48 +01:00
|
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|
|
|
/**
|
|
|
|
* device configuration
|
|
|
|
*/
|
|
|
|
void changeConfig(uint32_t newconfig);
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
void command(uint32_t command);
|
2004-11-13 23:10:48 +01:00
|
|
|
|
|
|
|
/**
|
|
|
|
* device ethernet interface
|
|
|
|
*/
|
|
|
|
public:
|
2006-04-25 01:31:50 +02:00
|
|
|
bool recvPacket(EthPacketPtr packet);
|
2004-11-13 23:10:48 +01:00
|
|
|
void transferDone();
|
2007-08-16 22:49:02 +02:00
|
|
|
virtual EtherInt *getEthPort(const std::string &if_name, int idx);
|
2004-11-13 23:10:48 +01:00
|
|
|
|
|
|
|
/**
|
|
|
|
* DMA parameters
|
|
|
|
*/
|
|
|
|
protected:
|
|
|
|
void rxDmaDone();
|
|
|
|
friend class EventWrapper<Device, &Device::rxDmaDone>;
|
|
|
|
EventWrapper<Device, &Device::rxDmaDone> rxDmaEvent;
|
|
|
|
|
|
|
|
void txDmaDone();
|
|
|
|
friend class EventWrapper<Device, &Device::txDmaDone>;
|
Major changes to sinic device model. Rearrage read/write, better
interrupts.
dev/sinic.cc:
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
Includes RxDone, RxWait, TxDone, and TxWait
- Use the new register information accessor functions to grab
validity and size information for the read and write functions
- read all registers directly from the register space by offset
and size, not by actual name (less code)
- The side effect of reading the interrupt status (clearing it) now
happens outside the actual chunk of code where the value is loaded.
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- When RxData or TxData are written, their busy flag is set to
indicate that they have an outstanding transaction.
- The RxHigh and TxLow interrupts are special, they only interrupt
if the rxEmpty or txFull limits were hit
- Move reset to the command register
- Update more registers on reset, clear rxEmpty and txFull
- Data dumps only happen if EthernetData trace flag set
- When a DMA completes, kick the other engine if it was waiting
- implement all of the new interrupts
- serialize the new stuff
dev/sinic.hh:
- Put all registers with their proper size and alignment into
the regs struct so that we can copy multiple at a time.
- Provide accessor functions for accessing the registers with
different sizes.
- Flags to track when the rx fifo hit empty and the tx fifo became
full. These flags are used to determine what to do when below
the watermarks, and are reset when crossing the watermark.
- the txDmaEvent should actually trigger the txDmaDone function
- Add an iprRead function for when we may want speculative access
to device registers through an ipr or special instruction.
- The prepareRead function sets all the variables in the register
file that depend on various state bits that change on the fly.
- add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
rename XxThreshold to XxFifoMark
Move Reset to the Command register
Add Thread to the Config register
New interrupts, better names
More info in RxDone and TxDone
Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
Both sinic and nsgige have the dedicated thread
Add a parameter to configure the maximum number for receive
packets per interrupt
--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-22 02:28:21 +02:00
|
|
|
EventWrapper<Device, &Device::txDmaDone> txDmaEvent;
|
2004-11-13 23:10:48 +01:00
|
|
|
|
|
|
|
Tick dmaReadDelay;
|
|
|
|
Tick dmaReadFactor;
|
|
|
|
Tick dmaWriteDelay;
|
|
|
|
Tick dmaWriteFactor;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Interrupt management
|
|
|
|
*/
|
|
|
|
protected:
|
|
|
|
void devIntrPost(uint32_t interrupts);
|
|
|
|
void devIntrClear(uint32_t interrupts = Regs::Intr_All);
|
|
|
|
void devIntrChangeMask(uint32_t newmask);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Memory Interface
|
|
|
|
*/
|
|
|
|
public:
|
2006-10-20 09:10:12 +02:00
|
|
|
virtual Tick read(PacketPtr pkt);
|
|
|
|
virtual Tick write(PacketPtr pkt);
|
2012-11-02 17:32:01 +01:00
|
|
|
virtual void drainResume();
|
2005-11-22 03:52:04 +01:00
|
|
|
|
2005-11-25 19:33:36 +01:00
|
|
|
void prepareIO(int cpu, int index);
|
|
|
|
void prepareRead(int cpu, int index);
|
|
|
|
void prepareWrite(int cpu, int index);
|
2006-04-25 01:31:50 +02:00
|
|
|
// Fault iprRead(Addr daddr, int cpu, uint64_t &result);
|
2004-11-13 23:10:48 +01:00
|
|
|
|
|
|
|
/**
|
|
|
|
* Statistics
|
|
|
|
*/
|
|
|
|
private:
|
2009-03-06 04:09:53 +01:00
|
|
|
Stats::Scalar totalVnicDistance;
|
|
|
|
Stats::Scalar numVnicDistance;
|
|
|
|
Stats::Scalar maxVnicDistance;
|
2008-10-09 13:58:23 +02:00
|
|
|
Stats::Formula avgVnicDistance;
|
|
|
|
|
|
|
|
int _maxVnicDistance;
|
|
|
|
|
2004-11-13 23:10:48 +01:00
|
|
|
public:
|
|
|
|
virtual void regStats();
|
2008-10-09 13:58:23 +02:00
|
|
|
virtual void resetStats();
|
2004-11-13 23:10:48 +01:00
|
|
|
|
|
|
|
/**
|
|
|
|
* Serialization stuff
|
|
|
|
*/
|
|
|
|
public:
|
|
|
|
virtual void serialize(std::ostream &os);
|
|
|
|
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
|
|
|
|
|
|
|
public:
|
2007-08-16 22:49:02 +02:00
|
|
|
Device(const Params *p);
|
2004-11-13 23:10:48 +01:00
|
|
|
~Device();
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Ethernet Interface for an Ethernet Device
|
|
|
|
*/
|
|
|
|
class Interface : public EtherInt
|
|
|
|
{
|
|
|
|
private:
|
|
|
|
Device *dev;
|
|
|
|
|
|
|
|
public:
|
|
|
|
Interface(const std::string &name, Device *d)
|
2007-08-16 22:49:02 +02:00
|
|
|
: EtherInt(name), dev(d)
|
|
|
|
{ }
|
2004-11-13 23:10:48 +01:00
|
|
|
|
2006-04-25 01:31:50 +02:00
|
|
|
virtual bool recvPacket(EthPacketPtr pkt) { return dev->recvPacket(pkt); }
|
2004-11-13 23:10:48 +01:00
|
|
|
virtual void sendDone() { dev->transferDone(); }
|
|
|
|
};
|
|
|
|
|
2011-01-03 23:35:43 +01:00
|
|
|
} // namespace Sinic
|
2004-11-13 23:10:48 +01:00
|
|
|
|
|
|
|
#endif // __DEV_SINIC_HH__
|