2007-05-28 04:21:17 +02:00
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# Copyright (c) 2005-2007 The Regents of The University of Michigan
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2011-02-07 07:14:17 +01:00
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# Copyright (c) 2011 Regents of the University of California
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2007-05-28 04:21:17 +02:00
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Nathan Binkert
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2011-02-07 07:14:17 +01:00
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# Rick Strong
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2007-05-28 04:21:17 +02:00
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from m5.SimObject import SimObject
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2009-09-23 00:24:16 +02:00
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from m5.defines import buildEnv
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2007-05-28 04:21:17 +02:00
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from m5.params import *
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from m5.proxy import *
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2009-09-23 00:24:16 +02:00
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power: Add basic DVFS support for gem5
Adds DVFS capabilities to gem5, by allowing users to specify lists for
frequencies and voltages in SrcClockDomains and VoltageDomains respectively.
A separate component, DVFSHandler, provides a small interface to change
operating points of the associated domains.
Clock domains will be linked to voltage domains and thus allow separate clock,
but shared voltage lines.
Currently all the valid performance-level updates are performed with a fixed
transition latency as specified for the domain.
Config file example:
...
vd = VoltageDomain(voltage = ['1V','0.95V','0.90V','0.85V'])
tsys.cluster1.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz']
tsys.cluster2.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz']
tsys.cluster1.clk_domain.domain_id = 0
tsys.cluster2.clk_domain.domain_id = 1
tsys.cluster1.clk_domain.voltage_domain = vd
tsys.cluster2.clk_domain.voltage_domain = vd
tsys.dvfs_handler.domains = [tsys.cluster1.clk_domain,
tsys.cluster2.clk_domain]
tsys.dvfs_handler.enable = True
2014-06-30 19:56:06 +02:00
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from DVFSHandler import *
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2012-04-06 19:46:31 +02:00
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from SimpleMemory import *
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2007-05-28 04:21:17 +02:00
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2013-02-15 23:40:09 +01:00
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class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing',
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'atomic_noncaching']
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2007-05-28 04:21:17 +02:00
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2012-01-17 19:55:07 +01:00
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class System(MemObject):
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2007-05-28 04:21:17 +02:00
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type = 'System'
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2012-11-02 17:32:01 +01:00
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cxx_header = "sim/system.hh"
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2012-02-13 12:43:09 +01:00
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system_port = MasterPort("System port")
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2010-09-09 23:15:41 +02:00
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@classmethod
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2011-10-20 22:09:10 +02:00
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def export_method_cxx_predecls(cls, code):
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code('#include "sim/system.hh"')
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@classmethod
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def export_methods(cls, code):
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code('''
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2013-02-15 23:40:09 +01:00
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Enums::MemoryMode getMemoryMode() const;
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2011-10-20 22:09:10 +02:00
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void setMemoryMode(Enums::MemoryMode mode);
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''')
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2007-08-03 07:50:02 +02:00
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2012-04-06 19:46:31 +02:00
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memories = VectorParam.AbstractMemory(Self.all,
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"All memories in the system")
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2007-05-28 04:21:17 +02:00
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mem_mode = Param.MemoryMode('atomic', "The mode the memory system is in")
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2013-01-07 19:05:38 +01:00
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2015-02-16 09:33:47 +01:00
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# When reserving memory on the host, we have the option of
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# reserving swap space or not (by passing MAP_NORESERVE to
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# mmap). By enabling this flag, we accomodate cases where a large
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# (but sparse) memory is simulated.
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mmap_using_noreserve = Param.Bool(False, "mmap the backing store " \
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"without reserving swap")
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2013-01-07 19:05:38 +01:00
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# The memory ranges are to be populated when creating the system
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# such that these can be passed from the I/O subsystem through an
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# I/O bridge or cache
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mem_ranges = VectorParam.AddrRange([], "Ranges that constitute main memory")
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2013-07-18 14:31:16 +02:00
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cache_line_size = Param.Unsigned(64, "Cache line size in bytes")
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2011-02-07 07:14:19 +01:00
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work_item_id = Param.Int(-1, "specific work item id")
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2012-01-10 01:08:20 +01:00
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num_work_ids = Param.Int(16, "Number of distinct work item types")
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2011-02-07 07:14:19 +01:00
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work_begin_cpu_id_exit = Param.Int(-1,
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"work started on specific id, now exit simulation")
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work_begin_ckpt_count = Param.Counter(0,
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"create checkpoint when work items begin count value is reached")
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work_begin_exit_count = Param.Counter(0,
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"exit simulation when work items begin count value is reached")
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work_end_ckpt_count = Param.Counter(0,
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"create checkpoint when work items end count value is reached")
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work_end_exit_count = Param.Counter(0,
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"exit simulation when work items end count value is reached")
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work_cpus_ckpt_count = Param.Counter(0,
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"create checkpoint when active cpu count value is reached")
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2011-10-30 10:30:55 +01:00
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init_param = Param.UInt64(0, "numerical value to pass into simulator")
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boot_osflags = Param.String("a", "boot flags to pass to the kernel")
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kernel = Param.String("", "file that contains the kernel code")
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2014-08-13 12:57:35 +02:00
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kernel_addr_check = Param.Bool(True,
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"whether to address check on kernel (disable for baremetal)")
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2011-10-30 10:30:55 +01:00
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readfile = Param.String("", "file to read startup script from")
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symbolfile = Param.String("", "file to get the symbols from")
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load_addr_mask = Param.UInt64(0xffffffffff,
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arm: Add support for ARMv8 (AArch64 & AArch32)
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64
kernel you are restricted to AArch64 user-mode binaries. This will be addressed
in a later patch.
Note: Virtualization is only supported in AArch32 mode. This will also be fixed
in a later patch.
Contributors:
Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation)
Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation)
Mbou Eyole (AArch64 NEON, validation)
Ali Saidi (AArch64 Linux support, code integration, validation)
Edmund Grimley-Evans (AArch64 FP)
William Wang (AArch64 Linux support)
Rene De Jong (AArch64 Linux support, performance opt.)
Matt Horsnell (AArch64 MP, validation)
Matt Evans (device models, code integration, validation)
Chris Adeniyi-Jones (AArch64 syscall-emulation)
Prakash Ramrakhyani (validation)
Dam Sunwoo (validation)
Chander Sudanthi (validation)
Stephan Diestelhorst (validation)
Andreas Hansson (code integration, performance opt.)
Eric Van Hensbergen (performance opt.)
Gabe Black
2014-01-24 22:29:34 +01:00
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"Address to mask loading binaries with")
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load_offset = Param.UInt64(0, "Address to offset loading binaries with")
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power: Add basic DVFS support for gem5
Adds DVFS capabilities to gem5, by allowing users to specify lists for
frequencies and voltages in SrcClockDomains and VoltageDomains respectively.
A separate component, DVFSHandler, provides a small interface to change
operating points of the associated domains.
Clock domains will be linked to voltage domains and thus allow separate clock,
but shared voltage lines.
Currently all the valid performance-level updates are performed with a fixed
transition latency as specified for the domain.
Config file example:
...
vd = VoltageDomain(voltage = ['1V','0.95V','0.90V','0.85V'])
tsys.cluster1.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz']
tsys.cluster2.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz']
tsys.cluster1.clk_domain.domain_id = 0
tsys.cluster2.clk_domain.domain_id = 1
tsys.cluster1.clk_domain.voltage_domain = vd
tsys.cluster2.clk_domain.voltage_domain = vd
tsys.dvfs_handler.domains = [tsys.cluster1.clk_domain,
tsys.cluster2.clk_domain]
tsys.dvfs_handler.enable = True
2014-06-30 19:56:06 +02:00
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# Dynamic voltage and frequency handler for the system, disabled by default
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# Provide list of domains that need to be controlled by the handler
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dvfs_handler = DVFSHandler()
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