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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt

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tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
---------- Begin Simulation Statistics ----------
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
sim_seconds 2.608779 # Number of seconds simulated
sim_ticks 2608778789000 # Number of ticks simulated
final_tick 2608778789000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
host_inst_rate 458042 # Simulator instruction rate (inst/s)
host_op_rate 582855 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 19847185908 # Simulator tick rate (ticks/s)
host_mem_usage 403628 # Number of bytes of host memory used
host_seconds 131.44 # Real time elapsed on the host
sim_insts 60206536 # Number of instructions simulated
sim_ops 76612339 # Number of ops (including micro ops) simulated
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.bytes_read::cpu0.inst 419296 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 4486284 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 285888 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 4557412 # Number of bytes read from this memory
system.physmem.bytes_read::total 132432464 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 419296 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 285888 # Number of instructions bytes read from this memory
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.bytes_inst_read::total 705184 # Number of instructions bytes read from this memory
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.bytes_written::writebacks 3671168 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 1520308 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 1495832 # Number of bytes written to this memory
system.physmem.bytes_written::total 6687308 # Number of bytes written to this memory
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.num_reads::cpu0.inst 12754 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 70131 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 4467 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 71233 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15494012 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 57362 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 380077 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 373958 # Number of write requests responded to by this memory
system.physmem.num_writes::total 811397 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 47027135 # Total read bandwidth from this memory (bytes/s)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.bw_read::cpu0.dtb.walker 25 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.bw_read::cpu0.inst 160725 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 1719687 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 109587 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 1746952 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 50764160 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 160725 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 109587 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 270312 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1407236 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 582766 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 573384 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2563386 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1407236 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 47027135 # Total bandwidth to/from this memory (bytes/s)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.bw_total::cpu0.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.bw_total::cpu0.inst 160725 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 2302454 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 109587 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 2320336 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 53327546 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 15494012 # Total number of read requests seen
system.physmem.writeReqs 811397 # Total number of write requests seen
system.physmem.cpureqs 213789 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 991616768 # Total number of bytes read from memory
system.physmem.bytesWritten 51929408 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 132432464 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 6687308 # bytesWritten derated as per pkt->getSize()
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.servicedByWrQ 26 # Number of read reqs serviced by write Q
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.neitherReadNorWrite 4515 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 974838 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 967895 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 967761 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 968555 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 968388 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 967634 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 967725 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 968240 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 968100 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 967669 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 967706 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 968019 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 968146 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 967639 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 967512 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 968159 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 50747 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 50350 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 50307 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 50989 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 50784 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 50138 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 50200 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 50702 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 51143 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 50687 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 50721 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 51041 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 51142 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 50663 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 50586 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 51197 # Track writes on a per bank basis
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.totGap 2608774377500 # Total gap between requests
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.readPktSize::2 6676 # Categorize read packet sizes
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.readPktSize::3 15335424 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.readPktSize::6 151912 # Categorize read packet sizes
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.writePktSize::2 754035 # categorize write packet sizes
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.writePktSize::6 57362 # categorize write packet sizes
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.neitherpktsize::6 4515 # categorize neither packet sizes
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.rdQLenPdf::0 1116413 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 960010 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 974367 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 3651904 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2754719 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2759720 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 2733933 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 61766 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 60421 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 111612 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 162702 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 111491 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 8813 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 8742 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 8677 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 8643 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 53 # What read queue length does an incoming req see
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.wrQLenPdf::0 35437 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 35422 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 35405 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 35390 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 35375 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 35363 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 35347 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 35331 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 35321 # What write queue length does an incoming req see
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.wrQLenPdf::9 35304 # What write queue length does an incoming req see
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.wrQLenPdf::10 35300 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 35287 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 35272 # What write queue length does an incoming req see
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.wrQLenPdf::13 35257 # What write queue length does an incoming req see
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.wrQLenPdf::14 35243 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 35231 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 35210 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 35193 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 35169 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 35156 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 35140 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 35124 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 35107 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 13 # What write queue length does an incoming req see
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.totQLat 338341857800 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 433208122800 # Sum of mem lat for all requests
system.physmem.totBusLat 77469930000 # Total cycles spent in databus access
system.physmem.totBankLat 17396335000 # Total cycles spent in bank access
system.physmem.avgQLat 21836.98 # Average queueing delay per request
system.physmem.avgBankLat 1122.78 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 27959.76 # Average memory access latency
system.physmem.avgRdBW 380.11 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 19.91 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 50.76 # Average consumed read bandwidth in MB/s
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.avgConsumedWrBW 2.56 # Average consumed write bandwidth in MB/s
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 3.13 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.17 # Average read queue length over time
system.physmem.avgWrQLen 1.24 # Average write queue length over time
system.physmem.readRowHits 15419486 # Number of row buffer hits during reads
system.physmem.writeRowHits 793977 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 97.85 # Row buffer hit rate for writes
system.physmem.avgGap 159994.42 # Average gap between requests
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.replacements 61800 # number of replacements
system.l2c.tagsinuse 50918.253702 # Cycle average of tags in use
system.l2c.total_refs 1698591 # Total number of references to valid blocks.
system.l2c.sampled_refs 127185 # Sample count of references to valid blocks.
system.l2c.avg_refs 13.355278 # Average number of references to valid blocks.
system.l2c.warmup_cycle 2557152484500 # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks 37907.717848 # Average occupied blocks per requestor
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.occ_blocks::cpu0.dtb.walker 0.000184 # Average occupied blocks per requestor
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.occ_blocks::cpu0.itb.walker 0.000642 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst 4327.115126 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data 3096.490855 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst 2668.881351 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data 2918.047697 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.578426 # Average percentage of cache occupancy
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.occ_percent::cpu0.inst 0.066027 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data 0.047249 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst 0.040724 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data 0.044526 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.776951 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker 10142 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 3715 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 409497 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 188260 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 9560 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 3405 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 434855 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 182318 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1241752 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 596435 # number of Writeback hits
system.l2c.Writeback_hits::total 596435 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 11 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 15 # number of UpgradeReq hits
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.ReadExReq_hits::cpu0.data 57590 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 56979 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 114569 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 10142 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 3715 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 409497 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 245850 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 9560 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 3405 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 434855 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 239297 # number of demand (read+write) hits
system.l2c.demand_hits::total 1356321 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 10142 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 3715 # number of overall hits
system.l2c.overall_hits::cpu0.inst 409497 # number of overall hits
system.l2c.overall_hits::cpu0.data 245850 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 9560 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 3405 # number of overall hits
system.l2c.overall_hits::cpu1.inst 434855 # number of overall hits
system.l2c.overall_hits::cpu1.data 239297 # number of overall hits
system.l2c.overall_hits::total 1356321 # number of overall hits
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.ReadReq_misses::cpu0.inst 6138 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 5512 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 4467 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 4338 # number of ReadReq misses
system.l2c.ReadReq_misses::total 20458 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 1394 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 1477 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 2871 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 65401 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 67697 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 133098 # number of ReadExReq misses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.demand_misses::cpu0.inst 6138 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 70913 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 4467 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 72035 # number of demand (read+write) misses
system.l2c.demand_misses::total 153556 # number of demand (read+write) misses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.overall_misses::cpu0.inst 6138 # number of overall misses
system.l2c.overall_misses::cpu0.data 70913 # number of overall misses
system.l2c.overall_misses::cpu1.inst 4467 # number of overall misses
system.l2c.overall_misses::cpu1.data 72035 # number of overall misses
system.l2c.overall_misses::total 153556 # number of overall misses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 69000 # number of ReadReq miss cycles
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 82500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst 318096500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 286803500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 246123500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 241819000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 1092994000 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 227000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 228000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 455000 # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 2952460500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 3124906000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 6077366500 # number of ReadExReq miss cycles
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.demand_miss_latency::cpu0.dtb.walker 69000 # number of demand (read+write) miss cycles
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.demand_miss_latency::cpu0.itb.walker 82500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 318096500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 3239264000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 246123500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 3366725000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 7170360500 # number of demand (read+write) miss cycles
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.overall_miss_latency::cpu0.dtb.walker 69000 # number of overall miss cycles
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.overall_miss_latency::cpu0.itb.walker 82500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 318096500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 3239264000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 246123500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 3366725000 # number of overall miss cycles
system.l2c.overall_miss_latency::total 7170360500 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 10143 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 3717 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 415635 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 193772 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 9560 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 3405 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 439322 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 186656 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 1262210 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 596435 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 596435 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 1405 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 1492 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 2897 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 122991 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 124676 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 247667 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 10143 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 3717 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 415635 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 316763 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 9560 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 3405 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 439322 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 311332 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 1509877 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 10143 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 3717 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 415635 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 316763 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 9560 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 3405 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 439322 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 311332 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 1509877 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000099 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000538 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.014768 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.028446 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.010168 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.023241 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.016208 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.992171 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989946 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.991025 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.531754 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.542983 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.537407 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000099 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.000538 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.014768 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.223868 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.010168 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.231377 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.101701 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000099 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.000538 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.014768 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.223868 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.010168 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.231377 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.101701 # miss rate for overall accesses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 69000 # average ReadReq miss latency
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 41250 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 51824.128381 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 52032.565312 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 55098.164316 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 55744.352236 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 53426.239124 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 162.840746 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 154.366960 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 158.481365 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 45143.965689 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 46160.184351 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 45660.840133 # average ReadExReq miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 69000 # average overall miss latency
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 41250 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 51824.128381 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 45679.409981 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 55098.164316 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 46737.349899 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 46695.410795 # average overall miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 69000 # average overall miss latency
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 41250 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 51824.128381 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 45679.409981 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 55098.164316 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 46737.349899 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 46695.410795 # average overall miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.writebacks::writebacks 57362 # number of writebacks
system.l2c.writebacks::total 57362 # number of writebacks
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.ReadReq_mshr_misses::cpu0.inst 6138 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data 5512 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst 4467 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 4338 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 20458 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 1394 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 1477 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 2871 # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 65401 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 67697 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 133098 # number of ReadExReq MSHR misses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.demand_mshr_misses::cpu0.dtb.walker 1 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.demand_mshr_misses::cpu0.inst 6138 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 70913 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 4467 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 72035 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 153556 # number of demand (read+write) MSHR misses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.overall_mshr_misses::cpu0.dtb.walker 1 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.overall_mshr_misses::cpu0.inst 6138 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 70913 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 4467 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 72035 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 153556 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 56252 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 57504 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 241157706 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 218147951 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 190156606 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 187657351 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 837233370 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 13941394 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 14811949 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 28753343 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2130052049 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2272372420 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 4402424469 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 56252 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 57504 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 241157706 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 2348200000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 190156606 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 2460029771 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 5239657839 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 56252 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 57504 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 241157706 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 2348200000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 190156606 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 2460029771 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 5239657839 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 209122550 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83655977314 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 83046075777 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 166911175641 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4790521424 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 4370138455 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 9160659879 # number of WriteReq MSHR uncacheable cycles
system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 76254 # number of LoadLockedReq MSHR uncacheable cycles
system.l2c.LoadLockedReq_mshr_uncacheable_latency::total 76254 # number of LoadLockedReq MSHR uncacheable cycles
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data 30003 # number of StoreCondReq MSHR uncacheable cycles
system.l2c.StoreCondReq_mshr_uncacheable_latency::total 30003 # number of StoreCondReq MSHR uncacheable cycles
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 209122550 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 88446498738 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 87416214232 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 176071835520 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000099 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000538 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014768 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.028446 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010168 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.023241 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.016208 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.992171 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.989946 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.991025 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.531754 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.542983 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.537407 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000099 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000538 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014768 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.223868 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010168 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.231377 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.101701 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000099 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000538 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014768 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.223868 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010168 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.231377 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.101701 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 56252 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 28752 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39289.297165 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 39576.914187 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 42569.197672 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 43258.955970 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40924.497507 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10028.401490 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10015.096830 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 32569.105197 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 33566.811232 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 33076.563652 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 56252 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 28752 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39289.297165 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 33113.815520 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42569.197672 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 34150.479225 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 34122.130291 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 56252 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 28752 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39289.297165 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 33113.815520 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42569.197672 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 34150.479225 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 34122.130291 # average overall mshr miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency
system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency
system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency
system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.dtb.read_hits 7507423 # DTB read hits
system.cpu0.dtb.read_misses 6880 # DTB read misses
system.cpu0.dtb.write_hits 5552288 # DTB write hits
system.cpu0.dtb.write_misses 1844 # DTB write misses
system.cpu0.dtb.flush_tlb 1276 # Number of times complete TLB was flushed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.dtb.flush_tlb_mva_asid 721 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 6531 # Number of entries that have been flushed from TLB
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.dtb.prefetch_faults 127 # Number of TLB faults due to prefetch
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.dtb.perms_faults 245 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 7514303 # DTB read accesses
system.cpu0.dtb.write_accesses 5554132 # DTB write accesses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.dtb.hits 13059711 # DTB hits
system.cpu0.dtb.misses 8724 # DTB misses
system.cpu0.dtb.accesses 13068435 # DTB accesses
system.cpu0.itb.inst_hits 30766737 # ITB inst hits
system.cpu0.itb.inst_misses 3610 # ITB inst misses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.itb.flush_tlb 1276 # Number of times complete TLB was flushed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.itb.flush_tlb_mva_asid 721 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 2714 # Number of entries that have been flushed from TLB
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.itb.inst_accesses 30770347 # ITB inst accesses
system.cpu0.itb.hits 30766737 # DTB hits
system.cpu0.itb.misses 3610 # DTB misses
system.cpu0.itb.accesses 30770347 # DTB accesses
system.cpu0.numCycles 2552892042 # number of cpu cycles simulated
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.committedInsts 30144083 # Number of instructions committed
system.cpu0.committedOps 38293118 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 34424567 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 5276 # Number of float alu accesses
system.cpu0.num_func_calls 1041312 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 4017319 # number of instructions that are conditional controls
system.cpu0.num_int_insts 34424567 # number of integer instructions
system.cpu0.num_fp_insts 5276 # number of float instructions
system.cpu0.num_int_register_reads 197342497 # number of times the integer registers were read
system.cpu0.num_int_register_writes 37147622 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 3922 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 1356 # number of times the floating registers were written
system.cpu0.num_mem_refs 13659512 # number of memory refs
system.cpu0.num_load_insts 7847120 # Number of load instructions
system.cpu0.num_store_insts 5812392 # Number of store instructions
system.cpu0.num_idle_cycles 3486759367.777020 # Number of idle cycles
system.cpu0.num_busy_cycles -933867325.777020 # Number of busy cycles
system.cpu0.not_idle_fraction -0.365808 # Percentage of non-idle cycles
system.cpu0.idle_fraction 1.365808 # Percentage of idle cycles
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.kern.inst.quiesce 83016 # number of quiesce instructions executed
system.cpu0.icache.replacements 856082 # number of replacements
system.cpu0.icache.tagsinuse 510.977353 # Cycle average of tags in use
system.cpu0.icache.total_refs 60644038 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 856594 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 70.796711 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 18804733000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst 354.105005 # Average occupied blocks per requestor
system.cpu0.icache.occ_blocks::cpu1.inst 156.872348 # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst 0.691611 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::cpu1.inst 0.306391 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total 0.998003 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 30350365 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 30293673 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 60644038 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 30350365 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 30293673 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 60644038 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 30350365 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 30293673 # number of overall hits
system.cpu0.icache.overall_hits::total 60644038 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 416372 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 440222 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 856594 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 416372 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 440222 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 856594 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 416372 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 440222 # number of overall misses
system.cpu0.icache.overall_misses::total 856594 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5679878500 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 5933784000 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 11613662500 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 5679878500 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 5933784000 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 11613662500 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 5679878500 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 5933784000 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 11613662500 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 30766737 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 30733895 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 61500632 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 30766737 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 30733895 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 61500632 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 30766737 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 30733895 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 61500632 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013533 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014324 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.013928 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013533 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014324 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.013928 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013533 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014324 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.013928 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13641.355567 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13479.071923 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13557.954527 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13641.355567 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13479.071923 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13557.954527 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13641.355567 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13479.071923 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13557.954527 # average overall miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 416372 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 440222 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 856594 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 416372 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 440222 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 856594 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 416372 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 440222 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 856594 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4847134500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5053340000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 9900474500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4847134500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5053340000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 9900474500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4847134500 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5053340000 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 9900474500 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 298856500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 298856500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 298856500 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 298856500 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013533 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014324 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013928 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013533 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014324 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.013928 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013533 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014324 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.013928 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11641.355567 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11479.071923 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11557.954527 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11641.355567 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11479.071923 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11557.954527 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11641.355567 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11479.071923 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11557.954527 # average overall mshr miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.dcache.replacements 627582 # number of replacements
system.cpu0.dcache.tagsinuse 511.912781 # Cycle average of tags in use
system.cpu0.dcache.total_refs 23658997 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 628094 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 37.667924 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 472186000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data 366.656660 # Average occupied blocks per requestor
system.cpu0.dcache.occ_blocks::cpu1.data 145.256121 # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data 0.716126 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::cpu1.data 0.283703 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total 0.999830 # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data 6610551 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 6586942 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 13197493 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 4931268 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 5043253 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 9974521 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 109193 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 127143 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 236336 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 114800 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 132950 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 247750 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 11541819 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 11630195 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 23172014 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 11541819 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 11630195 # number of overall hits
system.cpu0.dcache.overall_hits::total 23172014 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 188165 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 180848 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 369013 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 124396 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 126168 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 250564 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 5607 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 5808 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 11415 # number of LoadLockedReq misses
system.cpu0.dcache.demand_misses::cpu0.data 312561 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 307016 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 619577 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 312561 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 307016 # number of overall misses
system.cpu0.dcache.overall_misses::total 619577 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2684596500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2560064500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 5244661000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 3933387000 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 4106921000 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 8040308000 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 77883000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 77590000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 155473000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 6617983500 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 6666985500 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 13284969000 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 6617983500 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 6666985500 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 13284969000 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 6798716 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 6767790 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 13566506 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5055664 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 5169421 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 10225085 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 114800 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 132951 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 247751 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 114800 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 132950 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 247750 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 11854380 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 11937211 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 23791591 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 11854380 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 11937211 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 23791591 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027677 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.026722 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.027200 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.024605 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.024407 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.024505 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048841 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.043685 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046074 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026367 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025719 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.026042 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026367 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.025719 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.026042 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14267.246831 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14155.890582 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14212.672724 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 31619.883276 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 32551.209498 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 32088.839578 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13890.315677 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13359.159780 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13620.061323 # average LoadLockedReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 21173.414150 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21715.433398 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 21441.998331 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21173.414150 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 21715.433398 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 21441.998331 # average overall miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.dcache.writebacks::writebacks 596435 # number of writebacks
system.cpu0.dcache.writebacks::total 596435 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188165 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 180848 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 369013 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 124396 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 126168 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 250564 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 5607 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5808 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11415 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 312561 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 307016 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 619577 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 312561 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 307016 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 619577 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2308266500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2198368500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4506635000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3684595000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 3854585000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7539180000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66669000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 65974000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 132643000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 5992861500 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6052953500 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 12045815000 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 5992861500 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6052953500 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 12045815000 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91377449500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90718593500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182096043000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 9611433000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 9088267500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 18699700500 # number of WriteReq MSHR uncacheable cycles
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 117500 # number of LoadLockedReq MSHR uncacheable cycles
system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 117500 # number of LoadLockedReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 100988882500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 99806861000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 200795743500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027677 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026722 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027200 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024605 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024407 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024505 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048841 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.043685 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046074 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026367 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025719 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.026042 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026367 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025719 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.026042 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12267.246831 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12155.890582 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12212.672724 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29619.883276 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30551.209498 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30088.839578 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11890.315677 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11359.159780 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11620.061323 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19173.414150 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19715.433398 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19441.998331 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19173.414150 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19715.433398 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19441.998331 # average overall mshr miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency
system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency
system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu1.dtb.read_hits 7490923 # DTB read hits
system.cpu1.dtb.read_misses 7080 # DTB read misses
system.cpu1.dtb.write_hits 5680189 # DTB write hits
system.cpu1.dtb.write_misses 1780 # DTB write misses
system.cpu1.dtb.flush_tlb 1275 # Number of times complete TLB was flushed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu1.dtb.flush_tlb_mva_asid 718 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 6451 # Number of entries that have been flushed from TLB
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu1.dtb.prefetch_faults 157 # Number of TLB faults due to prefetch
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu1.dtb.perms_faults 207 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 7498003 # DTB read accesses
system.cpu1.dtb.write_accesses 5681969 # DTB write accesses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu1.dtb.hits 13171112 # DTB hits
system.cpu1.dtb.misses 8860 # DTB misses
system.cpu1.dtb.accesses 13179972 # DTB accesses
system.cpu1.itb.inst_hits 30733895 # ITB inst hits
system.cpu1.itb.inst_misses 3661 # ITB inst misses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu1.itb.flush_tlb 1275 # Number of times complete TLB was flushed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu1.itb.flush_tlb_mva_asid 718 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 2756 # Number of entries that have been flushed from TLB
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu1.itb.inst_accesses 30737556 # ITB inst accesses
system.cpu1.itb.hits 30733895 # DTB hits
system.cpu1.itb.misses 3661 # DTB misses
system.cpu1.itb.accesses 30737556 # DTB accesses
system.cpu1.numCycles 2664665536 # number of cpu cycles simulated
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu1.committedInsts 30062453 # Number of instructions committed
system.cpu1.committedOps 38319221 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 34454483 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 4993 # Number of float alu accesses
system.cpu1.num_func_calls 1098871 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 3931518 # number of instructions that are conditional controls
system.cpu1.num_int_insts 34454483 # number of integer instructions
system.cpu1.num_fp_insts 4993 # number of float instructions
system.cpu1.num_int_register_reads 197476279 # number of times the integer registers were read
system.cpu1.num_int_register_writes 37039984 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 3571 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 1424 # number of times the floating registers were written
system.cpu1.num_mem_refs 13738954 # number of memory refs
system.cpu1.num_load_insts 7815473 # Number of load instructions
system.cpu1.num_store_insts 5923481 # Number of store instructions
system.cpu1.num_idle_cycles 1359992851.787481 # Number of idle cycles
system.cpu1.num_busy_cycles 1304672684.212520 # Number of busy cycles
system.cpu1.not_idle_fraction 0.489620 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.510380 # Percentage of idle cycles
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.avg_refs nan # Average number of references to valid blocks.
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1196180344448 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1196180344448 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1196180344448 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1196180344448 # number of overall MSHR uncacheable cycles
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink