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gem5/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt

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cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
---------- Begin Simulation Statistics ----------
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
sim_seconds 1.199774 # Number of seconds simulated
sim_ticks 1199774280000 # Number of ticks simulated
final_tick 1199774280000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
host_inst_rate 216625 # Simulator instruction rate (inst/s)
host_op_rate 216625 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 142303871 # Simulator tick rate (ticks/s)
host_mem_usage 282608 # Number of bytes of host memory used
host_seconds 8431.08 # Real time elapsed on the host
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
sim_insts 1826378509 # Number of instructions simulated
sim_ops 1826378509 # Number of ops (including micro ops) simulated
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.voltage_domain.voltage 1 # Voltage in Volts
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
system.clk_domain.clock 1000 # Clock period in ticks
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.physmem.bytes_read::cpu.inst 61376 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 125444608 # Number of bytes read from this memory
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.bytes_read::total 125505984 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 61376 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 61376 # Number of instructions bytes read from this memory
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.bytes_written::writebacks 65167488 # Number of bytes written to this memory
system.physmem.bytes_written::total 65167488 # Number of bytes written to this memory
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.physmem.num_reads::cpu.inst 959 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1960072 # Number of read requests responded to by this memory
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.num_reads::total 1961031 # Number of read requests responded to by this memory
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.num_writes::writebacks 1018242 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1018242 # Number of write requests responded to by this memory
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.physmem.bw_read::cpu.inst 51156 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 104556840 # Total read bandwidth from this memory (bytes/s)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.bw_read::total 104607997 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 51156 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 51156 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 54316457 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 54316457 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 54316457 # Total bandwidth to/from this memory (bytes/s)
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.physmem.bw_total::cpu.inst 51156 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 104556840 # Total bandwidth to/from this memory (bytes/s)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.bw_total::total 158924454 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 1961031 # Number of read requests accepted
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.writeReqs 1018242 # Number of write requests accepted
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.readBursts 1961031 # Number of DRAM read bursts, including those serviced by the write queue
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.writeBursts 1018242 # Number of DRAM write bursts, including those merged in the write queue
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.bytesReadDRAM 125423808 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 82176 # Total number of bytes read from write queue
system.physmem.bytesWritten 65166208 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 125505984 # Total read bytes from the system interface side
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.bytesWrittenSys 65167488 # Total written bytes from the system interface side
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.servicedByWrQ 1284 # Number of DRAM read bursts serviced by the write queue
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.perBankRdBursts::0 118757 # Per bank write bursts
system.physmem.perBankRdBursts::1 114096 # Per bank write bursts
system.physmem.perBankRdBursts::2 116226 # Per bank write bursts
system.physmem.perBankRdBursts::3 117770 # Per bank write bursts
system.physmem.perBankRdBursts::4 117824 # Per bank write bursts
system.physmem.perBankRdBursts::5 117523 # Per bank write bursts
system.physmem.perBankRdBursts::6 119882 # Per bank write bursts
system.physmem.perBankRdBursts::7 124516 # Per bank write bursts
system.physmem.perBankRdBursts::8 126973 # Per bank write bursts
system.physmem.perBankRdBursts::9 130090 # Per bank write bursts
system.physmem.perBankRdBursts::10 128654 # Per bank write bursts
system.physmem.perBankRdBursts::11 130347 # Per bank write bursts
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.perBankRdBursts::12 126055 # Per bank write bursts
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.perBankRdBursts::13 125249 # Per bank write bursts
system.physmem.perBankRdBursts::14 122591 # Per bank write bursts
system.physmem.perBankRdBursts::15 123194 # Per bank write bursts
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.perBankWrBursts::0 61222 # Per bank write bursts
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.perBankWrBursts::1 61485 # Per bank write bursts
system.physmem.perBankWrBursts::2 60564 # Per bank write bursts
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.perBankWrBursts::3 61239 # Per bank write bursts
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.perBankWrBursts::4 61658 # Per bank write bursts
system.physmem.perBankWrBursts::5 63101 # Per bank write bursts
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.perBankWrBursts::6 64148 # Per bank write bursts
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.perBankWrBursts::7 65617 # Per bank write bursts
system.physmem.perBankWrBursts::8 65332 # Per bank write bursts
system.physmem.perBankWrBursts::9 65778 # Per bank write bursts
system.physmem.perBankWrBursts::10 65295 # Per bank write bursts
system.physmem.perBankWrBursts::11 65646 # Per bank write bursts
system.physmem.perBankWrBursts::12 64171 # Per bank write bursts
system.physmem.perBankWrBursts::13 64211 # Per bank write bursts
system.physmem.perBankWrBursts::14 64568 # Per bank write bursts
system.physmem.perBankWrBursts::15 64187 # Per bank write bursts
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.totGap 1199774169500 # Total gap between requests
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.readPktSize::6 1961031 # Read request sizes (log2)
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.writePktSize::6 1018242 # Write request sizes (log2)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.rdQLenPdf::0 1834284 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 125445 # What read queue length does an incoming req see
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.wrQLenPdf::15 30311 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 31746 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 55277 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 59244 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 59773 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 59999 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 60000 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 59968 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 59954 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 60029 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 60015 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 60058 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 60509 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 60796 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 60183 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 61128 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 59690 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 59431 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 88 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 10 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.bytesPerActivate::samples 1838370 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 103.671596 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 81.054008 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 129.842659 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 1459678 79.40% 79.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 262161 14.26% 93.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 49287 2.68% 96.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 20645 1.12% 97.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 12893 0.70% 98.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 7143 0.39% 98.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 5357 0.29% 98.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 4451 0.24% 99.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 16755 0.91% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1838370 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 59429 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 32.975652 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 161.968947 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 59388 99.93% 99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 14 0.02% 99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071 11 0.02% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.98% # Reads before turning the bus around for writes
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.rdPerTurnAround::total 59429 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 59429 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 17.133420 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.097680 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 1.110939 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 27565 46.38% 46.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17 1269 2.14% 48.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 26249 44.17% 92.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 3908 6.58% 99.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 362 0.61% 99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21 56 0.09% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22 12 0.02% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23 5 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24 2 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 59429 # Writes before turning the bus around for reads
system.physmem.totQLat 36751953000 # Total ticks spent queuing
system.physmem.totMemAccLat 73497209250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 9798735000 # Total ticks spent in databus transfers
system.physmem.avgQLat 18753.42 # Average queueing delay per DRAM burst
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.avgMemAccLat 37503.42 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 104.54 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 54.32 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 104.61 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 54.32 # Average system write bandwidth in MiByte/s
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.busUtil 1.24 # Data bus utilization in percentage
system.physmem.busUtilRead 0.82 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.42 # Data bus utilization in percentage for writes
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.avgWrQLen 24.53 # Average write queue length when enqueuing
system.physmem.readRowHits 726418 # Number of row buffer hits during reads
system.physmem.writeRowHits 413172 # Number of row buffer hits during writes
system.physmem.readRowHitRate 37.07 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 40.58 # Row buffer hit rate for writes
system.physmem.avgGap 402707.03 # Average gap between requests
system.physmem.pageHitRate 38.27 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 6745500720 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 3680580750 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 7383386400 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 3233733840 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 78362993280 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 409753789290 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 360427621500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 869587605780 # Total energy per rank (pJ)
system.physmem_0.averagePower 724.796496 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 596865139750 # Time in different power states
system.physmem_0.memoryStateTime::REF 40062880000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 562842538250 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 7152516000 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 3902662500 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 7901961600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 3364241040 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 78362993280 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 422708761260 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 349063611000 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 872456746680 # Total energy per rank (pJ)
system.physmem_1.averagePower 727.187909 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 577877428500 # Time in different power states
system.physmem_1.memoryStateTime::REF 40062880000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 581827655250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 246222594 # Number of BP lookups
system.cpu.branchPred.condPredicted 186441188 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 15682162 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 167748253 # Number of BTB lookups
system.cpu.branchPred.BTBHits 165224895 # Number of BTB hits
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.branchPred.BTBHitPct 98.495747 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 18427327 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 104678 # Number of incorrect RAS predictions.
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dtb.read_hits 452533853 # DTB read hits
system.cpu.dtb.read_misses 4979561 # DTB read misses
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.dtb.read_acv 0 # DTB read access violations
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dtb.read_accesses 457513414 # DTB read accesses
system.cpu.dtb.write_hits 161377742 # DTB write hits
system.cpu.dtb.write_misses 1710117 # DTB write misses
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.dtb.write_acv 0 # DTB write access violations
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dtb.write_accesses 163087859 # DTB write accesses
system.cpu.dtb.data_hits 613911595 # DTB hits
system.cpu.dtb.data_misses 6689678 # DTB misses
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.dtb.data_acv 0 # DTB access violations
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dtb.data_accesses 620601273 # DTB accesses
system.cpu.itb.fetch_hits 598493672 # ITB hits
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.itb.fetch_misses 19 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.itb.fetch_accesses 598493691 # ITB accesses
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.numCycles 2399548560 # number of cpu cycles simulated
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1826378509 # Number of instructions committed
system.cpu.committedOps 1826378509 # Number of ops (including micro ops) committed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.discardedOps 52395177 # Number of ops (including micro ops) which were discarded before commit
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.cpi 1.313829 # CPI: cycles per instruction
system.cpu.ipc 0.761134 # IPC: instructions per cycle
system.cpu.tickCycles 2077217503 # Number of cycles that the object actually ticked
system.cpu.idleCycles 322331057 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 9121997 # number of replacements
system.cpu.dcache.tags.tagsinuse 4080.675710 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 601828569 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 9126093 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 65.945917 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 16789907000 # Cycle when the warmup percentage was hit.
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.tags.occ_blocks::cpu.data 4080.675710 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.996259 # Average percentage of cache occupancy
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.occ_percent::total 0.996259 # Average percentage of cache occupancy
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1613 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2310 # Occupied blocks per task id
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::3 65 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.tag_accesses 1231839903 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1231839903 # Number of data accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.ReadReq_hits::cpu.data 443338834 # number of ReadReq hits
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.ReadReq_hits::total 443338834 # number of ReadReq hits
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.WriteReq_hits::cpu.data 158489735 # number of WriteReq hits
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_hits::total 158489735 # number of WriteReq hits
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.demand_hits::cpu.data 601828569 # number of demand (read+write) hits
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.demand_hits::total 601828569 # number of demand (read+write) hits
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.overall_hits::cpu.data 601828569 # number of overall hits
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.overall_hits::total 601828569 # number of overall hits
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.ReadReq_misses::cpu.data 7289569 # number of ReadReq misses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.ReadReq_misses::total 7289569 # number of ReadReq misses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.WriteReq_misses::cpu.data 2238767 # number of WriteReq misses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_misses::total 2238767 # number of WriteReq misses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.demand_misses::cpu.data 9528336 # number of demand (read+write) misses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.demand_misses::total 9528336 # number of demand (read+write) misses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.overall_misses::cpu.data 9528336 # number of overall misses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.overall_misses::total 9528336 # number of overall misses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.ReadReq_miss_latency::cpu.data 178039686000 # number of ReadReq miss cycles
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.ReadReq_miss_latency::total 178039686000 # number of ReadReq miss cycles
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.WriteReq_miss_latency::cpu.data 100958450500 # number of WriteReq miss cycles
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_miss_latency::total 100958450500 # number of WriteReq miss cycles
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.demand_miss_latency::cpu.data 278998136500 # number of demand (read+write) miss cycles
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.demand_miss_latency::total 278998136500 # number of demand (read+write) miss cycles
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.overall_miss_latency::cpu.data 278998136500 # number of overall miss cycles
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.overall_miss_latency::total 278998136500 # number of overall miss cycles
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.ReadReq_accesses::cpu.data 450628403 # number of ReadReq accesses(hits+misses)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.ReadReq_accesses::total 450628403 # number of ReadReq accesses(hits+misses)
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses)
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.demand_accesses::cpu.data 611356905 # number of demand (read+write) accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.demand_accesses::total 611356905 # number of demand (read+write) accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.overall_accesses::cpu.data 611356905 # number of overall (read+write) accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.overall_accesses::total 611356905 # number of overall (read+write) accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016176 # miss rate for ReadReq accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.ReadReq_miss_rate::total 0.016176 # miss rate for ReadReq accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013929 # miss rate for WriteReq accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.WriteReq_miss_rate::total 0.013929 # miss rate for WriteReq accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.015586 # miss rate for demand accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.demand_miss_rate::total 0.015586 # miss rate for demand accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.overall_miss_rate::cpu.data 0.015586 # miss rate for overall accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.overall_miss_rate::total 0.015586 # miss rate for overall accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24423.897490 # average ReadReq miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.ReadReq_avg_miss_latency::total 24423.897490 # average ReadReq miss latency
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45095.559520 # average WriteReq miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_avg_miss_latency::total 45095.559520 # average WriteReq miss latency
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.demand_avg_miss_latency::cpu.data 29280.887712 # average overall miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.demand_avg_miss_latency::total 29280.887712 # average overall miss latency
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.overall_avg_miss_latency::cpu.data 29280.887712 # average overall miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.overall_avg_miss_latency::total 29280.887712 # average overall miss latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.writebacks::writebacks 3700624 # number of writebacks
system.cpu.dcache.writebacks::total 3700624 # number of writebacks
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 50811 # number of ReadReq MSHR hits
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.ReadReq_mshr_hits::total 50811 # number of ReadReq MSHR hits
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 351432 # number of WriteReq MSHR hits
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_mshr_hits::total 351432 # number of WriteReq MSHR hits
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.demand_mshr_hits::cpu.data 402243 # number of demand (read+write) MSHR hits
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.demand_mshr_hits::total 402243 # number of demand (read+write) MSHR hits
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.overall_mshr_hits::cpu.data 402243 # number of overall MSHR hits
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.overall_mshr_hits::total 402243 # number of overall MSHR hits
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7238758 # number of ReadReq MSHR misses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.ReadReq_mshr_misses::total 7238758 # number of ReadReq MSHR misses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1887335 # number of WriteReq MSHR misses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_mshr_misses::total 1887335 # number of WriteReq MSHR misses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.demand_mshr_misses::cpu.data 9126093 # number of demand (read+write) MSHR misses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.demand_mshr_misses::total 9126093 # number of demand (read+write) MSHR misses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.overall_mshr_misses::cpu.data 9126093 # number of overall MSHR misses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.overall_mshr_misses::total 9126093 # number of overall MSHR misses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 162083992000 # number of ReadReq MSHR miss cycles
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.ReadReq_mshr_miss_latency::total 162083992000 # number of ReadReq MSHR miss cycles
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 75948494500 # number of WriteReq MSHR miss cycles
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_mshr_miss_latency::total 75948494500 # number of WriteReq MSHR miss cycles
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 238032486500 # number of demand (read+write) MSHR miss cycles
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.demand_mshr_miss_latency::total 238032486500 # number of demand (read+write) MSHR miss cycles
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 238032486500 # number of overall MSHR miss cycles
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.overall_mshr_miss_latency::total 238032486500 # number of overall MSHR miss cycles
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016064 # mshr miss rate for ReadReq accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016064 # mshr miss rate for ReadReq accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011742 # mshr miss rate for WriteReq accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011742 # mshr miss rate for WriteReq accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014928 # mshr miss rate for demand accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.demand_mshr_miss_rate::total 0.014928 # mshr miss rate for demand accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014928 # mshr miss rate for overall accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.overall_mshr_miss_rate::total 0.014928 # mshr miss rate for overall accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22391.132844 # average ReadReq mshr miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22391.132844 # average ReadReq mshr miss latency
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40241.130748 # average WriteReq mshr miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40241.130748 # average WriteReq mshr miss latency
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26082.627747 # average overall mshr miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26082.627747 # average overall mshr miss latency
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26082.627747 # average overall mshr miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26082.627747 # average overall mshr miss latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.icache.tags.replacements 3 # number of replacements
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.icache.tags.tagsinuse 752.081160 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 598492713 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 959 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 624079.992701 # Average number of references to valid blocks.
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.icache.tags.occ_blocks::cpu.inst 752.081160 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.367227 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.367227 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 956 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 876 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.466797 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 1196988303 # Number of tag accesses
system.cpu.icache.tags.data_accesses 1196988303 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 598492713 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 598492713 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 598492713 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 598492713 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 598492713 # number of overall hits
system.cpu.icache.overall_hits::total 598492713 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 959 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 959 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 959 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 959 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 959 # number of overall misses
system.cpu.icache.overall_misses::total 959 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 71027250 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 71027250 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 71027250 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 71027250 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 71027250 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 71027250 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 598493672 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 598493672 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 598493672 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 598493672 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 598493672 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 598493672 # number of overall (read+write) accesses
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74063.868613 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 74063.868613 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 74063.868613 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 74063.868613 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 74063.868613 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 74063.868613 # average overall miss latency
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 959 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 959 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 959 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 959 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 959 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 959 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 68715750 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 68715750 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 68715750 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 68715750 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 68715750 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 68715750 # number of overall MSHR miss cycles
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71653.545360 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71653.545360 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71653.545360 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 71653.545360 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71653.545360 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 71653.545360 # average overall mshr miss latency
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.tags.replacements 1928296 # number of replacements
system.cpu.l2cache.tags.tagsinuse 30756.810610 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 8981713 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 1958100 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 4.586953 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 89009074750 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 14951.890642 # Average occupied blocks per requestor
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.tags.occ_blocks::cpu.inst 43.293989 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 15761.625979 # Average occupied blocks per requestor
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.tags.occ_percent::writebacks 0.456295 # Average percentage of cache occupancy
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001321 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.481007 # Average percentage of cache occupancy
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.tags.occ_percent::total 0.938623 # Average percentage of cache occupancy
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29804 # Occupied blocks per task id
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 166 # Occupied blocks per task id
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1226 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12860 # Occupied blocks per task id
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15531 # Occupied blocks per task id
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909546 # Percentage of cache occupancy per task id
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.tags.tag_accesses 106466843 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 106466843 # Number of data accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.ReadReq_hits::cpu.data 6058136 # number of ReadReq hits
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadReq_hits::total 6058136 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 3700624 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 3700624 # number of Writeback hits
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.ReadExReq_hits::cpu.data 1107885 # number of ReadExReq hits
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadExReq_hits::total 1107885 # number of ReadExReq hits
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.demand_hits::cpu.data 7166021 # number of demand (read+write) hits
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.demand_hits::total 7166021 # number of demand (read+write) hits
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.overall_hits::cpu.data 7166021 # number of overall hits
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.overall_hits::total 7166021 # number of overall hits
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.ReadReq_misses::cpu.inst 959 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 1180622 # number of ReadReq misses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadReq_misses::total 1181581 # number of ReadReq misses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 779450 # number of ReadExReq misses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadExReq_misses::total 779450 # number of ReadExReq misses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.demand_misses::cpu.inst 959 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 1960072 # number of demand (read+write) misses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.demand_misses::total 1961031 # number of demand (read+write) misses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.overall_misses::cpu.inst 959 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 1960072 # number of overall misses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.overall_misses::total 1961031 # number of overall misses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 67755750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 94247592500 # number of ReadReq miss cycles
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadReq_miss_latency::total 94315348250 # number of ReadReq miss cycles
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 62933867000 # number of ReadExReq miss cycles
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadExReq_miss_latency::total 62933867000 # number of ReadExReq miss cycles
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.demand_miss_latency::cpu.inst 67755750 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 157181459500 # number of demand (read+write) miss cycles
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.demand_miss_latency::total 157249215250 # number of demand (read+write) miss cycles
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.overall_miss_latency::cpu.inst 67755750 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 157181459500 # number of overall miss cycles
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.overall_miss_latency::total 157249215250 # number of overall miss cycles
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.ReadReq_accesses::cpu.inst 959 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 7238758 # number of ReadReq accesses(hits+misses)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadReq_accesses::total 7239717 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 3700624 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 3700624 # number of Writeback accesses(hits+misses)
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1887335 # number of ReadExReq accesses(hits+misses)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadExReq_accesses::total 1887335 # number of ReadExReq accesses(hits+misses)
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.demand_accesses::cpu.inst 959 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 9126093 # number of demand (read+write) accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.demand_accesses::total 9127052 # number of demand (read+write) accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.overall_accesses::cpu.inst 959 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 9126093 # number of overall (read+write) accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.overall_accesses::total 9127052 # number of overall (read+write) accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163097 # miss rate for ReadReq accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadReq_miss_rate::total 0.163208 # miss rate for ReadReq accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.412990 # miss rate for ReadExReq accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadExReq_miss_rate::total 0.412990 # miss rate for ReadExReq accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.214777 # miss rate for demand accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.demand_miss_rate::total 0.214859 # miss rate for demand accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.214777 # miss rate for overall accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.overall_miss_rate::total 0.214859 # miss rate for overall accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70652.502607 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79828.761873 # average ReadReq miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadReq_avg_miss_latency::total 79821.314197 # average ReadReq miss latency
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80741.377895 # average ReadExReq miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80741.377895 # average ReadExReq miss latency
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70652.502607 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80191.676377 # average overall miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.demand_avg_miss_latency::total 80187.011450 # average overall miss latency
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70652.502607 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80191.676377 # average overall miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.overall_avg_miss_latency::total 80187.011450 # average overall miss latency
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.writebacks::writebacks 1018242 # number of writebacks
system.cpu.l2cache.writebacks::total 1018242 # number of writebacks
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 959 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1180622 # number of ReadReq MSHR misses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadReq_mshr_misses::total 1181581 # number of ReadReq MSHR misses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 779450 # number of ReadExReq MSHR misses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadExReq_mshr_misses::total 779450 # number of ReadExReq MSHR misses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 959 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 1960072 # number of demand (read+write) MSHR misses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.demand_mshr_misses::total 1961031 # number of demand (read+write) MSHR misses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.overall_mshr_misses::cpu.inst 959 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1960072 # number of overall MSHR misses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.overall_mshr_misses::total 1961031 # number of overall MSHR misses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 55699750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 79417889000 # number of ReadReq MSHR miss cycles
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 79473588750 # number of ReadReq MSHR miss cycles
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53122771000 # number of ReadExReq MSHR miss cycles
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53122771000 # number of ReadExReq MSHR miss cycles
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 55699750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 132540660000 # number of demand (read+write) MSHR miss cycles
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.demand_mshr_miss_latency::total 132596359750 # number of demand (read+write) MSHR miss cycles
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 55699750 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 132540660000 # number of overall MSHR miss cycles
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.overall_mshr_miss_latency::total 132596359750 # number of overall MSHR miss cycles
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163097 # mshr miss rate for ReadReq accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163208 # mshr miss rate for ReadReq accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.412990 # mshr miss rate for ReadExReq accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.412990 # mshr miss rate for ReadExReq accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214777 # mshr miss rate for demand accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::total 0.214859 # mshr miss rate for demand accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214777 # mshr miss rate for overall accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::total 0.214859 # mshr miss rate for overall accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58081.074035 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67267.837631 # average ReadReq mshr miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67260.381430 # average ReadReq mshr miss latency
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68154.174097 # average ReadExReq mshr miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68154.174097 # average ReadExReq mshr miss latency
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58081.074035 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67620.301703 # average overall mshr miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67615.636749 # average overall mshr miss latency
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58081.074035 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67620.301703 # average overall mshr miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67615.636749 # average overall mshr miss latency
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.trans_dist::ReadReq 7239717 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 7239717 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 3700624 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1887335 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1887335 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1918 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21952810 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 21954728 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61376 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820909888 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 820971264 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::samples 12827676 # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::1 12827676 100.00% 100.00% # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::total 12827676 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 10114462000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.respLayer0.occupancy 1635250 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.respLayer1.occupancy 14011262000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.trans_dist::ReadReq 1181581 # Transaction distribution
system.membus.trans_dist::ReadResp 1181581 # Transaction distribution
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.trans_dist::Writeback 1018242 # Transaction distribution
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.trans_dist::ReadExReq 779450 # Transaction distribution
system.membus.trans_dist::ReadExResp 779450 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4940304 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 4940304 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190673472 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 190673472 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.snoops 0 # Total snoops (count)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::samples 2979273 # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::0 2979273 100.00% 100.00% # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::total 2979273 # Request fanout histogram
system.membus.reqLayer0.occupancy 11833185000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.reqLayer0.utilization 1.0 # Layer utilization (%)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.respLayer1.occupancy 18446289250 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.respLayer1.utilization 1.5 # Layer utilization (%)
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
---------- End Simulation Statistics ----------
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