2012-09-21 17:48:11 +02:00
|
|
|
# Copyright (c) 2012 ARM Limited
|
|
|
|
|
# All rights reserved.
|
|
|
|
|
#
|
|
|
|
|
# The license below extends only to copyright in the software and shall
|
|
|
|
|
# not be construed as granting a license to any other intellectual
|
|
|
|
|
# property including but not limited to intellectual property relating
|
|
|
|
|
# to a hardware implementation of the functionality of the software
|
|
|
|
|
# licensed hereunder. You may use the software subject to the license
|
|
|
|
|
# terms below provided that you ensure that this notice is replicated
|
|
|
|
|
# unmodified and in its entirety in all distributions of the software,
|
|
|
|
|
# modified or unmodified, in source code or in binary form.
|
|
|
|
|
#
|
|
|
|
|
# Redistribution and use in source and binary forms, with or without
|
|
|
|
|
# modification, are permitted provided that the following conditions are
|
|
|
|
|
# met: redistributions of source code must retain the above copyright
|
|
|
|
|
# notice, this list of conditions and the following disclaimer;
|
|
|
|
|
# redistributions in binary form must reproduce the above copyright
|
|
|
|
|
# notice, this list of conditions and the following disclaimer in the
|
|
|
|
|
# documentation and/or other materials provided with the distribution;
|
|
|
|
|
# neither the name of the copyright holders nor the names of its
|
|
|
|
|
# contributors may be used to endorse or promote products derived from
|
|
|
|
|
# this software without specific prior written permission.
|
|
|
|
|
#
|
|
|
|
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
|
|
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
|
|
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
|
|
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
|
|
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
|
|
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
|
|
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
|
|
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
|
|
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
|
|
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
|
|
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
|
|
|
#
|
|
|
|
|
# Authors: Andreas Hansson
|
|
|
|
|
|
|
|
|
|
import m5
|
|
|
|
|
from m5.objects import *
|
|
|
|
|
|
2013-01-07 19:05:37 +01:00
|
|
|
# both traffic generator and communication monitor are only available
|
|
|
|
|
# if we have protobuf support, so potentially skip this test
|
|
|
|
|
require_sim_object("TrafficGen")
|
|
|
|
|
require_sim_object("CommMonitor")
|
|
|
|
|
|
2012-09-21 17:48:11 +02:00
|
|
|
# even if this is only a traffic generator, call it cpu to make sure
|
|
|
|
|
# the scripts are happy
|
|
|
|
|
cpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-mem.cfg")
|
|
|
|
|
|
|
|
|
|
# system simulated
|
|
|
|
|
system = System(cpu = cpu, physmem = SimpleMemory(),
|
sim: Add the notion of clock domains to all ClockedObjects
This patch adds the notion of source- and derived-clock domains to the
ClockedObjects. As such, all clock information is moved to the clock
domain, and the ClockedObjects are grouped into domains.
The clock domains are either source domains, with a specific clock
period, or derived domains that have a parent domain and a divider
(potentially chained). For piece of logic that runs at a derived clock
(a ratio of the clock its parent is running at) the necessary derived
clock domain is created from its corresponding parent clock
domain. For now, the derived clock domain only supports a divider,
thus ensuring a lower speed compared to its parent. Multiplier
functionality implies a PLL logic that has not been modelled yet
(create a separate clock instead).
The clock domains should be used as a mechanism to provide a
controllable clock source that affects clock for every clocked object
lying beneath it. The clock of the domain can (in a future patch) be
controlled by a handler responsible for dynamic frequency scaling of
the respective clock domains.
All the config scripts have been retro-fitted with clock domains. For
the System a default SrcClockDomain is created. For CPUs that run at a
different speed than the system, there is a seperate clock domain
created. This domain incorporates the CPU and the associated
caches. As before, Ruby runs under its own clock domain.
The clock period of all domains are pre-computed, such that no virtual
functions or multiplications are needed when calling
clockPeriod. Instead, the clock period is pre-computed when any
changes occur. For this to be possible, each clock domain tracks its
children.
2013-06-27 11:49:49 +02:00
|
|
|
membus = NoncoherentBus(width = 16),
|
|
|
|
|
clk_domain = SrcClockDomain(clock = '1GHz'))
|
2012-09-21 17:48:11 +02:00
|
|
|
|
2013-01-07 19:05:37 +01:00
|
|
|
# add a communication monitor, and also trace all the packets
|
|
|
|
|
system.monitor = CommMonitor(trace_file = "monitor.ptrc.gz")
|
2012-09-21 17:48:11 +02:00
|
|
|
|
|
|
|
|
# connect the traffic generator to the bus via a communication monitor
|
|
|
|
|
system.cpu.port = system.monitor.slave
|
|
|
|
|
system.monitor.master = system.membus.slave
|
|
|
|
|
|
|
|
|
|
# connect the system port even if it is not used in this example
|
|
|
|
|
system.system_port = system.membus.slave
|
|
|
|
|
|
|
|
|
|
# connect memory to the membus
|
|
|
|
|
system.physmem.port = system.membus.master
|
|
|
|
|
|
|
|
|
|
# -----------------------
|
|
|
|
|
# run simulation
|
|
|
|
|
# -----------------------
|
|
|
|
|
|
|
|
|
|
root = Root(full_system = False, system = system)
|
|
|
|
|
root.system.mem_mode = 'timing'
|
