2011-01-18 23:30:06 +01:00
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---------- Begin Simulation Statistics ----------
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2011-09-13 18:58:09 +02:00
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sim_seconds 0.031208 # Number of seconds simulated
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sim_ticks 31207726500 # Number of ticks simulated
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2011-01-18 23:30:06 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-09-13 18:58:09 +02:00
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host_inst_rate 157603 # Simulator instruction rate (inst/s)
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host_tick_rate 48874778 # Simulator tick rate (ticks/s)
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host_mem_usage 225884 # Number of bytes of host memory used
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host_seconds 638.52 # Real time elapsed on the host
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sim_insts 100633520 # Number of instructions simulated
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2011-01-18 23:30:06 +01:00
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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2011-05-23 17:59:13 +02:00
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 1946 # Number of system calls
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2011-09-13 18:58:09 +02:00
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system.cpu.numCycles 62415454 # number of cpu cycles simulated
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2011-05-23 17:59:13 +02:00
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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2011-09-13 18:58:09 +02:00
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system.cpu.BPredUnit.lookups 17712573 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 11586024 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 828480 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 15104552 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 9800008 # Number of BTB hits
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2011-05-23 17:59:13 +02:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2011-09-13 18:58:09 +02:00
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system.cpu.BPredUnit.usedRAS 1894610 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 179140 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 13000723 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 88894307 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 17712573 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 11694618 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 23068870 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 2942261 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 22994151 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 49 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 1125 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 12237155 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 232722 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 61101347 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.028542 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.080485 # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2011-09-13 18:58:09 +02:00
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system.cpu.fetch.rateDist::0 38048418 62.27% 62.27% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 2437383 3.99% 66.26% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 2590379 4.24% 70.50% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 2495519 4.08% 74.58% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 1726071 2.82% 77.41% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 1712649 2.80% 80.21% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 1014415 1.66% 81.87% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 1324144 2.17% 84.04% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 9752369 15.96% 100.00% # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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2011-09-13 18:58:09 +02:00
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system.cpu.fetch.rateDist::total 61101347 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.283785 # Number of branch fetches per cycle
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system.cpu.fetch.rate 1.424236 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 14911699 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 21729904 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 21442913 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 1077075 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 1939756 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 3477546 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 98242 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 120762342 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 332405 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 1939756 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 16842041 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 2003570 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 15407287 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 20561842 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 4346851 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 117493872 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 3565 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 3003461 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.FullRegisterEvents 318 # Number of times there has been no free registers
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system.cpu.rename.RenamedOperands 119392349 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 540581981 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 540487699 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 94282 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 99143301 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 20249043 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 768563 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 768716 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 12082768 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 29799998 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 22399772 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 2425661 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 3419073 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 112105098 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 764637 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 107812126 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 316132 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 12020521 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 30346065 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 63680 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 61101347 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 1.764480 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.904021 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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2011-09-13 18:58:09 +02:00
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system.cpu.iq.issued_per_cycle::0 22159484 36.27% 36.27% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 11621982 19.02% 55.29% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 8561362 14.01% 69.30% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 7410232 12.13% 81.43% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 4801172 7.86% 89.28% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 3527397 5.77% 95.06% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 1679086 2.75% 97.81% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 804521 1.32% 99.12% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 536111 0.88% 100.00% # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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2011-09-13 18:58:09 +02:00
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system.cpu.iq.issued_per_cycle::total 61101347 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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2011-09-13 18:58:09 +02:00
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system.cpu.iq.fu_full::IntAlu 88099 3.31% 3.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 0 0.00% 3.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 3.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 3.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 3.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 3.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.31% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 1498283 56.35% 59.66% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 1072737 40.34% 100.00% # attempts to use FU when none available
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
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2011-09-13 18:58:09 +02:00
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system.cpu.iq.FU_type_0::IntAlu 57136904 53.00% 53.00% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 87447 0.08% 53.08% # Type of FU issued
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system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.08% # Type of FU issued
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|
system.cpu.iq.FU_type_0::FloatAdd 25 0.00% 53.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 4 0.00% 53.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.08% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemRead 29022906 26.92% 80.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 21564833 20.00% 100.00% # Type of FU issued
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iq.FU_type_0::total 107812126 # Type of FU issued
|
|
|
|
|
system.cpu.iq.rate 1.727331 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 2659119 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.024664 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 279700662 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 124905792 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 105547410 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 188 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 166 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 69 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_alu_accesses 110471148 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 97 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 1884692 # Number of loads that had data forwarded from stores
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 2491561 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 3411 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 16339 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 1842707 # Number of stores squashed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 50 # Number of loads that were rescheduled
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 62 # Number of times an access to memory failed due to the cache being blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 1939756 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 952120 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 28627 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 112946418 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 627319 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 29799998 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 22399772 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 747490 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 1210 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 1207 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 16339 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 688631 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 200572 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 889203 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 106427513 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 28649084 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 1384613 # Number of squashed instructions skipped in execute
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.exec_nop 76683 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_refs 49896710 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 14628801 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 21247626 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 1.705147 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 105874797 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 105547479 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 52578934 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 101387160 # num instructions consuming a value
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.wb_rate 1.691047 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.518596 # average fanout of values written-back
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.commitCommittedInsts 100639072 # The number of committed instructions
|
|
|
|
|
system.cpu.commit.commitSquashedInsts 12225024 # The number of squashed insts skipped by commit
|
|
|
|
|
system.cpu.commit.commitNonSpecStalls 700957 # The number of times commit has been forced to stall to communicate backwards
|
|
|
|
|
system.cpu.commit.branchMispredicts 794036 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 59161592 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 1.701088 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 2.430633 # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::0 26262806 44.39% 44.39% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 14615219 24.70% 69.10% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 4224786 7.14% 76.24% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 3635680 6.15% 82.38% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 2285256 3.86% 86.24% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 1889118 3.19% 89.44% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 706435 1.19% 90.63% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 496319 0.84% 91.47% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 5045973 8.53% 100.00% # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::total 59161592 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.count 100639072 # Number of instructions committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.refs 47865501 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads 27308436 # Number of loads committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.membars 15920 # Number of memory barriers committed
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.branches 13669955 # Number of branches committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.fp_insts 56 # Number of committed floating point instructions.
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.int_insts 91478095 # Number of committed integer instructions.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.function_calls 1679850 # Number of function calls committed.
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.bw_lim_events 5045973 # number cycles where commit BW limit reached
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.rob.rob_reads 166954416 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 227673782 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 61616 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 1314107 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.committedInsts 100633520 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 100633520 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.cpi 0.620225 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 0.620225 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 1.612317 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.612317 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 512325342 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 104042616 # number of integer regfile writes
|
|
|
|
|
system.cpu.fp_regfile_reads 124 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 92 # number of floating regfile writes
|
|
|
|
|
system.cpu.misc_regfile_reads 146636710 # number of misc regfile reads
|
|
|
|
|
system.cpu.misc_regfile_writes 34494 # number of misc regfile writes
|
|
|
|
|
system.cpu.icache.replacements 26059 # number of replacements
|
|
|
|
|
system.cpu.icache.tagsinuse 1807.414724 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 12207911 # Total number of references to valid blocks.
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.sampled_refs 28088 # Sample count of references to valid blocks.
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.avg_refs 434.630839 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.occ_blocks::0 1807.414724 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.occ_percent::0 0.882527 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits 12207928 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits 12207928 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits 12207928 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses 29227 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses 29227 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses 29227 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 359488500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency 359488500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency 359488500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 12237155 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses 12237155 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses 12237155 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.002388 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.002388 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.002388 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 12299.876826 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 12299.876826 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 12299.876826 # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.writebacks 1 # number of writebacks
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits 1106 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 1106 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 1106 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 28121 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 28121 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 28121 # number of overall MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 247525500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 247525500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 247525500 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.002298 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.002298 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.002298 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 8802.158529 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 8802.158529 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 8802.158529 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.replacements 157957 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 4072.327719 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 44754174 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 162053 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 276.169981 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.warmup_cycle 306664000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.occ_blocks::0 4072.327719 # Average occupied blocks per context
|
|
|
|
|
system.cpu.dcache.occ_percent::0 0.994221 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 26407726 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits 18310440 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits 18642 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.StoreCondReq_hits 17246 # number of StoreCondReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits 44718166 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits 44718166 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses 109117 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 1539461 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_misses 29 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu.dcache.demand_misses 1648578 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses 1648578 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 2423500000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency 52284424500 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency 398000 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency 54707924500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 54707924500 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 26516843 # number of ReadReq accesses(hits+misses)
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.WriteReq_accesses 19849901 # number of WriteReq accesses(hits+misses)
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_accesses 18671 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses 17246 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.demand_accesses 46366744 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses 46366744 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.004115 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.077555 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate 0.001553 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate 0.035555 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.035555 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 22210.104750 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 33962.811984 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency 13724.137931 # average LoadLockedReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency 33184.917244 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 33184.917244 # average overall miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 190500 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 19050 # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.writebacks 123460 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 53919 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 1432572 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits 29 # number of LoadLockedReq MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits 1486491 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 1486491 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 55198 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 106889 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses 162087 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 162087 # number of overall MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 1037796500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 3662032500 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 4699829000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 4699829000 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002082 # mshr miss rate for ReadReq accesses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.005385 # mshr miss rate for WriteReq accesses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.003496 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.003496 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18801.342440 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34260.143700 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 28995.718349 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 28995.718349 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.replacements 114992 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 18307.930672 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 72391 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 133845 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 0.540857 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.occ_blocks::0 2377.365392 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 15930.565280 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_percent::0 0.072551 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::1 0.486162 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 50505 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 123461 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_hits 12 # number of UpgradeReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits 4300 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits 54805 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits 54805 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 32740 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses 21 # number of UpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 102589 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses 135329 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses 135329 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 1120810000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 3525271500 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 4646081500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 4646081500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 83245 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 123461 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses 33 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses 106889 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses 190134 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses 190134 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.393297 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 0.636364 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.959771 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.711756 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.711756 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34233.659133 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34363.055493 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34331.750770 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34331.750770 # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.writebacks 88460 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits 79 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits 79 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 79 # number of overall MSHR hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 32661 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 21 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 102589 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 135250 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 135250 # number of overall MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 1015115500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 652000 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 3196978500 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 4212094000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 4212094000 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.392348 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.636364 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.959771 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.711340 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.711340 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31080.355776 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31047.619048 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31162.975563 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31143.024030 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31143.024030 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-01-18 23:30:06 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
