2011-01-18 23:30:06 +01:00
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---------- Begin Simulation Statistics ----------
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2011-08-19 22:08:08 +02:00
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sim_seconds 0.031378 # Number of seconds simulated
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sim_ticks 31377609500 # Number of ticks simulated
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2011-01-18 23:30:06 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-08-19 22:08:08 +02:00
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host_inst_rate 86505 # Simulator instruction rate (inst/s)
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host_tick_rate 26972311 # Simulator tick rate (ticks/s)
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host_mem_usage 272452 # Number of bytes of host memory used
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host_seconds 1163.33 # Real time elapsed on the host
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sim_insts 100633440 # Number of instructions simulated
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2011-01-18 23:30:06 +01:00
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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2011-05-23 17:59:13 +02:00
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 1946 # Number of system calls
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2011-08-19 22:08:08 +02:00
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system.cpu.numCycles 62755220 # number of cpu cycles simulated
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2011-05-23 17:59:13 +02:00
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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2011-08-19 22:08:08 +02:00
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system.cpu.BPredUnit.lookups 17750529 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 11606544 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 829921 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 15137991 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 9794974 # Number of BTB hits
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2011-05-23 17:59:13 +02:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2011-08-19 22:08:08 +02:00
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system.cpu.BPredUnit.usedRAS 1897089 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 178911 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 13034693 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 89118710 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 17750529 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 11692063 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 23121914 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 2980918 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 23222293 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 38 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 1054 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 12266935 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 235956 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 61445707 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.021826 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.078498 # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2011-08-19 22:08:08 +02:00
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system.cpu.fetch.rateDist::0 38339721 62.40% 62.40% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 2446048 3.98% 66.38% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 2617640 4.26% 70.64% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 2484251 4.04% 74.68% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 1726192 2.81% 77.49% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 1710249 2.78% 80.27% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 1014832 1.65% 81.92% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 1300729 2.12% 84.04% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 9806045 15.96% 100.00% # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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2011-08-19 22:08:08 +02:00
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system.cpu.fetch.rateDist::total 61445707 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.282853 # Number of branch fetches per cycle
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system.cpu.fetch.rate 1.420100 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 14959115 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 21951327 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 21472779 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 1093721 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 1968765 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 3488107 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 98503 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 121008055 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 332806 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 1968765 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 16904329 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 2023707 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 15518382 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 20592468 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 4438056 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 117725717 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 3874 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 3096804 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.FullRegisterEvents 422 # Number of times there has been no free registers
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system.cpu.rename.RenamedOperands 119617057 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 541668803 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 541574389 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 94414 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 99143173 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 20473879 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 769482 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 769728 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 12274515 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 29853222 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 22441342 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 2796873 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 3745515 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 112284917 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 766220 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 107896322 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 310095 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 12199571 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 30868237 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 65279 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 61445707 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 1.755962 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.898029 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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2011-08-19 22:08:08 +02:00
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system.cpu.iq.issued_per_cycle::0 22301465 36.29% 36.29% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 11812133 19.22% 55.52% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 8597395 13.99% 69.51% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 7417461 12.07% 81.58% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 4807172 7.82% 89.41% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 3508678 5.71% 95.12% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 1667450 2.71% 97.83% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 811386 1.32% 99.15% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 522567 0.85% 100.00% # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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2011-08-19 22:08:08 +02:00
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system.cpu.iq.issued_per_cycle::total 61445707 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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2011-08-19 22:08:08 +02:00
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system.cpu.iq.fu_full::IntAlu 87227 3.33% 3.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 0 0.00% 3.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 3.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 3.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 3.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 3.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 1494399 56.99% 60.32% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 1040416 39.68% 100.00% # attempts to use FU when none available
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
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2011-08-19 22:08:08 +02:00
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system.cpu.iq.FU_type_0::IntAlu 57176503 52.99% 52.99% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 87495 0.08% 53.07% # Type of FU issued
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system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.07% # Type of FU issued
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|
|
system.cpu.iq.FU_type_0::FloatAdd 25 0.00% 53.07% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.07% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.07% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.07% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.07% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.07% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 4 0.00% 53.07% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.07% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.07% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.07% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.07% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.07% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.07% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.07% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.07% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.07% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.07% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.07% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.07% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.07% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.07% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.07% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.07% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.07% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.07% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.07% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemRead 29053069 26.93% 80.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 21579219 20.00% 100.00% # Type of FU issued
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iq.FU_type_0::total 107896322 # Type of FU issued
|
|
|
|
|
system.cpu.iq.rate 1.719320 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 2622042 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.024301 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 280170245 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 125277700 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 105616251 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 243 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 246 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 88 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_alu_accesses 110518239 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 125 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 1858517 # Number of loads that had data forwarded from stores
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 2544801 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 4085 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 28033 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 1884293 # Number of stores squashed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 50 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 54 # Number of times an access to memory failed due to the cache being blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 1968765 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 949271 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 28405 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 113127739 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 631806 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 29853222 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 22441342 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 749089 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 969 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 1264 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 28033 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 689722 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 200512 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 890234 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 106504319 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 28672397 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 1392003 # Number of squashed instructions skipped in execute
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iew.exec_nop 76602 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_refs 49938031 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 14639990 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 21265634 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 1.697139 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 105945343 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 105616339 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 52584494 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 101353649 # num instructions consuming a value
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iew.wb_rate 1.682989 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.518822 # average fanout of values written-back
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.commitCommittedInsts 100638992 # The number of committed instructions
|
|
|
|
|
system.cpu.commit.commitSquashedInsts 12404270 # The number of squashed insts skipped by commit
|
|
|
|
|
system.cpu.commit.commitNonSpecStalls 700941 # The number of times commit has been forced to stall to communicate backwards
|
|
|
|
|
system.cpu.commit.branchMispredicts 795177 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 59476943 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 1.692067 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 2.421797 # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::0 26426974 44.43% 44.43% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 14734590 24.77% 69.21% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 4278530 7.19% 76.40% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 3643335 6.13% 82.53% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 2295146 3.86% 86.38% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 1888116 3.17% 89.56% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 696870 1.17% 90.73% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 492103 0.83% 91.56% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 5021279 8.44% 100.00% # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::total 59476943 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.count 100638992 # Number of instructions committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.refs 47865469 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads 27308420 # Number of loads committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.membars 15920 # Number of memory barriers committed
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.branches 13669939 # Number of branches committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.fp_insts 56 # Number of committed floating point instructions.
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.int_insts 91478031 # Number of committed integer instructions.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.function_calls 1679850 # Number of function calls committed.
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.bw_lim_events 5021279 # number cycles where commit BW limit reached
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.rob.rob_reads 167473627 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 228061528 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 61721 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 1309513 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.committedInsts 100633440 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 100633440 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.cpi 0.623602 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 0.623602 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 1.603587 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.603587 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 512681755 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 104103098 # number of integer regfile writes
|
|
|
|
|
system.cpu.fp_regfile_reads 154 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 120 # number of floating regfile writes
|
|
|
|
|
system.cpu.misc_regfile_reads 146929222 # number of misc regfile reads
|
|
|
|
|
system.cpu.misc_regfile_writes 34462 # number of misc regfile writes
|
|
|
|
|
system.cpu.icache.replacements 26055 # number of replacements
|
|
|
|
|
system.cpu.icache.tagsinuse 1807.169356 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 12237713 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.sampled_refs 28088 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.avg_refs 435.691861 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.occ_blocks::0 1807.169356 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.occ_percent::0 0.882407 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits 12237715 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits 12237715 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits 12237715 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses 29220 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses 29220 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses 29220 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 359586000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency 359586000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency 359586000 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 12266935 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses 12266935 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses 12266935 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.002382 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.002382 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.002382 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 12306.160164 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 12306.160164 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 12306.160164 # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits 1104 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 1104 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 1104 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 28116 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 28116 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 28116 # number of overall MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 247135000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 247135000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 247135000 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.002292 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.002292 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.002292 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 8789.834969 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 8789.834969 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 8789.834969 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.replacements 157895 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 4072.454592 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 44804358 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 161991 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 276.585477 # Average number of references to valid blocks.
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.warmup_cycle 307509000 # Cycle when the warmup percentage was hit.
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.occ_blocks::0 4072.454592 # Average occupied blocks per context
|
|
|
|
|
system.cpu.dcache.occ_percent::0 0.994252 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 26458104 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits 18310282 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits 18655 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.StoreCondReq_hits 17230 # number of StoreCondReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits 44768386 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits 44768386 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses 108049 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 1539619 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_misses 28 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu.dcache.demand_misses 1647668 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses 1647668 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 2398708000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency 52285313500 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency 392000 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency 54684021500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 54684021500 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 26566153 # number of ReadReq accesses(hits+misses)
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.WriteReq_accesses 19849901 # number of WriteReq accesses(hits+misses)
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_accesses 18683 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses 17230 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.demand_accesses 46416054 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses 46416054 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.004067 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.077563 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate 0.001499 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate 0.035498 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.035498 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 22200.186952 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 33959.904041 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency 14000 # average LoadLockedReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency 33188.737962 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 33188.737962 # average overall miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 196000 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 19600 # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.writebacks 123449 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 52916 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 1432732 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits 28 # number of LoadLockedReq MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits 1485648 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 1485648 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 55133 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 106887 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses 162020 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 162020 # number of overall MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 1036639500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 3662530000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 4699169500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 4699169500 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002075 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.005385 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.003491 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.003491 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18802.522990 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34265.439202 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 29003.638440 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 29003.638440 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.replacements 114951 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 18297.678495 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 72351 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 133808 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 0.540708 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.occ_blocks::0 2366.019129 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 15931.659366 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_percent::0 0.072205 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::1 0.486196 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 50475 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 123449 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_hits 9 # number of UpgradeReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits 4296 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits 54771 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits 54771 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 32704 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses 19 # number of UpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 102598 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses 135302 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses 135302 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 1119458500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_latency 34000 # number of UpgradeReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 3525951000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 4645409500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 4645409500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 83179 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 123449 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses 28 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses 106894 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses 190073 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses 190073 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.393176 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 0.678571 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.959811 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.711842 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.711842 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34230.017735 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 1789.473684 # average UpgradeReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34366.664068 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34333.635127 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34333.635127 # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.writebacks 88458 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits 87 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits 87 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 87 # number of overall MSHR hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 32617 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 102598 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 135215 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 135215 # number of overall MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 1013752000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 589000 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 3197491000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 4211243000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 4211243000 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.392130 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.678571 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.959811 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.711385 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.711385 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31080.479505 # average ReadReq mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31165.237139 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31144.791628 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31144.791628 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-01-18 23:30:06 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
