2011-01-18 23:30:06 +01:00
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---------- Begin Simulation Statistics ----------
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2011-07-10 19:56:09 +02:00
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sim_seconds 0.036245 # Number of seconds simulated
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2011-08-07 18:22:18 +02:00
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sim_ticks 36244602000 # Number of ticks simulated
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2011-01-18 23:30:06 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-08-07 18:22:18 +02:00
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host_inst_rate 65776 # Simulator instruction rate (inst/s)
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host_tick_rate 23690223 # Simulator tick rate (ticks/s)
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host_mem_usage 246996 # Number of bytes of host memory used
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host_seconds 1529.94 # Real time elapsed on the host
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2011-07-10 19:56:09 +02:00
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sim_insts 100633890 # Number of instructions simulated
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2011-01-18 23:30:06 +01:00
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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2011-05-23 17:59:13 +02:00
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 1946 # Number of system calls
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2011-08-07 18:22:18 +02:00
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system.cpu.numCycles 72489205 # number of cpu cycles simulated
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2011-05-23 17:59:13 +02:00
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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2011-07-10 19:56:09 +02:00
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system.cpu.BPredUnit.lookups 18012293 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 11774570 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 831874 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 15324494 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 9861947 # Number of BTB hits
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2011-05-23 17:59:13 +02:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2011-07-10 19:56:09 +02:00
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system.cpu.BPredUnit.usedRAS 1962775 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 178630 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 13228591 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 90356599 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 18012293 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 11824722 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 23464914 # Number of cycles fetch has run and was not squashing or blocked
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2011-08-07 18:22:18 +02:00
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system.cpu.fetch.SquashCycles 3236872 # Number of cycles fetch has spent squashing
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2011-07-10 19:56:09 +02:00
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system.cpu.fetch.BlockedCycles 32247240 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 76 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 1180 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 12447619 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 228695 # Number of outstanding Icache misses that were squashed
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2011-08-07 18:22:18 +02:00
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system.cpu.fetch.rateDist::samples 71274246 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 1.770512 # Number of instructions fetched each cycle (Total)
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2011-07-10 19:56:09 +02:00
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system.cpu.fetch.rateDist::stdev 2.958690 # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2011-08-07 18:22:18 +02:00
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system.cpu.fetch.rateDist::0 47826012 67.10% 67.10% # Number of instructions fetched each cycle (Total)
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2011-07-10 19:56:09 +02:00
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system.cpu.fetch.rateDist::1 2503425 3.51% 70.61% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 2625051 3.68% 74.30% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 2508744 3.52% 77.82% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 1756176 2.46% 80.28% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 1729968 2.43% 82.71% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 1023399 1.44% 84.14% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 1314592 1.84% 85.99% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 9986879 14.01% 100.00% # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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2011-08-07 18:22:18 +02:00
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system.cpu.fetch.rateDist::total 71274246 # Number of instructions fetched each cycle (Total)
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2011-07-10 19:56:09 +02:00
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system.cpu.fetch.branchRate 0.248482 # Number of branch fetches per cycle
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2011-08-07 18:22:18 +02:00
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system.cpu.fetch.rate 1.246484 # Number of inst fetches per cycle
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2011-07-10 19:56:09 +02:00
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system.cpu.decode.IdleCycles 15570258 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 30538007 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 21052115 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 1880159 # Number of cycles decode is unblocking
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2011-08-07 18:22:18 +02:00
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system.cpu.decode.SquashCycles 2233707 # Number of cycles decode is squashing
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2011-07-10 19:56:09 +02:00
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system.cpu.decode.BranchResolved 3555145 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 100131 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 123096705 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 322054 # Number of squashed instructions handled by decode
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2011-08-07 18:22:18 +02:00
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system.cpu.rename.SquashCycles 2233707 # Number of cycles rename is squashing
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2011-07-10 19:56:09 +02:00
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system.cpu.rename.IdleCycles 17831809 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 3189949 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 20082985 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 20587918 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 7347878 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 119869132 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 121794 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 5771428 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.FullRegisterEvents 352 # Number of times there has been no free registers
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system.cpu.rename.RenamedOperands 121512131 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 551578616 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 551477586 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 101030 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 99143893 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 22368233 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 776347 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 776986 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 18154637 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 30367199 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 22985654 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 18156398 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 16040246 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 114470256 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 775996 # Number of non-speculative instructions added to the IQ
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2011-08-07 18:22:18 +02:00
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system.cpu.iq.iqInstsIssued 107895564 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 172091 # Number of squashed instructions issued
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.iqSquashedInstsExamined 14439119 # Number of squashed instructions iterated over during squash; mainly for profiling
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2011-08-07 18:22:18 +02:00
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system.cpu.iq.iqSquashedOperandsExamined 40080699 # Number of squashed operands that are examined and possibly removed from graph
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.iqSquashedNonSpecRemoved 74965 # Number of squashed non-spec instructions that were removed
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2011-08-07 18:22:18 +02:00
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system.cpu.iq.issued_per_cycle::samples 71274246 # Number of insts issued each cycle
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.issued_per_cycle::mean 1.513809 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.644216 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.issued_per_cycle::0 25395561 35.63% 35.63% # Number of insts issued each cycle
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2011-08-07 18:22:18 +02:00
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system.cpu.iq.issued_per_cycle::1 17825654 25.01% 60.64% # Number of insts issued each cycle
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.issued_per_cycle::2 10968613 15.39% 76.03% # Number of insts issued each cycle
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2011-08-07 18:22:18 +02:00
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system.cpu.iq.issued_per_cycle::3 7406584 10.39% 86.42% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 5364631 7.53% 93.95% # Number of insts issued each cycle
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.issued_per_cycle::5 2359706 3.31% 97.26% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 1195437 1.68% 98.94% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 581224 0.82% 99.75% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 176836 0.25% 100.00% # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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2011-08-07 18:22:18 +02:00
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system.cpu.iq.issued_per_cycle::total 71274246 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.fu_full::IntAlu 116212 6.09% 6.09% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 0 0.00% 6.09% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 6.09% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.09% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.09% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.09% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 6.09% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.09% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.09% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.09% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.09% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.09% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.09% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.09% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.09% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 6.09% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.09% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 6.09% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.09% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.09% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.09% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.09% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.09% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.09% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.09% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.09% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.09% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.09% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.09% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 1547826 81.16% 87.25% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 243196 12.75% 100.00% # attempts to use FU when none available
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2011-05-23 17:59:13 +02:00
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|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
2011-08-07 18:22:18 +02:00
|
|
|
system.cpu.iq.FU_type_0::IntAlu 57756459 53.53% 53.53% # Type of FU issued
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.FU_type_0::IntMult 87061 0.08% 53.61% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.61% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatAdd 21 0.00% 53.61% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.61% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.61% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.61% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.61% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.61% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 2 0.00% 53.61% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.61% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.61% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.61% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.61% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.61% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.61% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.61% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.61% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.61% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.61% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.61% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.61% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.61% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.61% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.61% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.61% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.61% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.61% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.61% # Type of FU issued
|
2011-08-07 18:22:18 +02:00
|
|
|
system.cpu.iq.FU_type_0::MemRead 28748786 26.65% 80.26% # Type of FU issued
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.FU_type_0::MemWrite 21303228 19.74% 100.00% # Type of FU issued
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2011-08-07 18:22:18 +02:00
|
|
|
system.cpu.iq.FU_type_0::total 107895564 # Type of FU issued
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.rate 1.488436 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 1907234 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.017677 # FU busy rate (busy events/executed inst)
|
2011-08-07 18:22:18 +02:00
|
|
|
system.cpu.iq.int_inst_queue_reads 289144535 # Number of integer instruction queue reads
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.int_inst_queue_writes 129693775 # Number of integer instruction queue writes
|
2011-08-07 18:22:18 +02:00
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 105980229 # Number of integer instruction queue wakeup accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.fp_inst_queue_reads 164 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 164 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 71 # Number of floating instruction queue wakeup accesses
|
2011-08-07 18:22:18 +02:00
|
|
|
system.cpu.iq.int_alu_accesses 109802715 # Number of integer alu accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.fp_alu_accesses 83 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 1086375 # Number of loads that had data forwarded from stores
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 3058688 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 1951 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 8954 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 2428515 # Number of stores squashed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 42 # Number of loads that were rescheduled
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 45 # Number of times an access to memory failed due to the cache being blocked
|
|
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2011-08-07 18:22:18 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 2233707 # Number of cycles IEW is squashing
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.iewBlockCycles 1028781 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 38378 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 115325010 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 602761 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 30367199 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 22985654 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 758781 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 5441 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 5622 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 8954 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 689500 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 204403 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 893903 # Number of branch mispredicts detected at execute
|
2011-08-07 18:22:18 +02:00
|
|
|
system.cpu.iew.iewExecutedInsts 106692633 # Number of executed instructions
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.iewExecLoadInsts 28420136 # Number of load instructions executed
|
2011-08-07 18:22:18 +02:00
|
|
|
system.cpu.iew.iewExecSquashedInsts 1202931 # Number of squashed instructions skipped in execute
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.exec_nop 78758 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_refs 49527893 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 14765827 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 21107757 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 1.471842 # Inst execution rate
|
2011-08-07 18:22:18 +02:00
|
|
|
system.cpu.iew.wb_sent 106228536 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 105980300 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 55087780 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 106077595 # num instructions consuming a value
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.wb_rate 1.462015 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.519316 # average fanout of values written-back
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.commitCommittedInsts 100639442 # The number of committed instructions
|
|
|
|
|
system.cpu.commit.commitSquashedInsts 14606204 # The number of squashed insts skipped by commit
|
|
|
|
|
system.cpu.commit.commitNonSpecStalls 701031 # The number of times commit has been forced to stall to communicate backwards
|
|
|
|
|
system.cpu.commit.branchMispredicts 796162 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 69040540 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 1.457686 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 2.138867 # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::0 30680365 44.44% 44.44% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 19612880 28.41% 72.85% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 4794365 6.94% 79.79% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 4311364 6.24% 86.03% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 3142866 4.55% 90.59% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 1355731 1.96% 92.55% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 737162 1.07% 93.62% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 515807 0.75% 94.37% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 3890000 5.63% 100.00% # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::total 69040540 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.count 100639442 # Number of instructions committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.refs 47865649 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads 27308510 # Number of loads committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.membars 15920 # Number of memory barriers committed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.branches 13670029 # Number of branches committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.fp_insts 56 # Number of committed floating point instructions.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.int_insts 91478391 # Number of committed integer instructions.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.function_calls 1679850 # Number of function calls committed.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.bw_lim_events 3890000 # number cycles where commit BW limit reached
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.rob.rob_reads 180370887 # The number of ROB reads
|
2011-08-07 18:22:18 +02:00
|
|
|
system.cpu.rob.rob_writes 232731383 # The number of ROB writes
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.timesIdled 61980 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
2011-08-07 18:22:18 +02:00
|
|
|
system.cpu.idleCycles 1214959 # Total number of cycles that the CPU has spent unscheduled due to idling
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.committedInsts 100633890 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 100633890 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.cpi 0.720326 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 0.720326 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 1.388260 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.388260 # IPC: Total IPC of All Threads
|
2011-08-07 18:22:18 +02:00
|
|
|
system.cpu.int_regfile_reads 512693420 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 104594221 # number of integer regfile writes
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.fp_regfile_reads 142 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 118 # number of floating regfile writes
|
|
|
|
|
system.cpu.misc_regfile_reads 148024846 # number of misc regfile reads
|
|
|
|
|
system.cpu.misc_regfile_writes 34642 # number of misc regfile writes
|
|
|
|
|
system.cpu.icache.replacements 27879 # number of replacements
|
2011-08-07 18:22:18 +02:00
|
|
|
system.cpu.icache.tagsinuse 1824.272942 # Cycle average of tags in use
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.total_refs 12416599 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.sampled_refs 29916 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.avg_refs 415.048770 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-08-07 18:22:18 +02:00
|
|
|
system.cpu.icache.occ_blocks::0 1824.272942 # Average occupied blocks per context
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.occ_percent::0 0.890758 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits 12416599 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits 12416599 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits 12416599 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses 31020 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses 31020 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses 31020 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 368970500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency 368970500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency 368970500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 12447619 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses 12447619 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses 12447619 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.002492 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.002492 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.002492 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 11894.600258 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 11894.600258 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 11894.600258 # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits 1093 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 1093 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 1093 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 29927 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 29927 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 29927 # number of overall MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 251359000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 251359000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 251359000 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.002404 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.002404 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.002404 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 8399.071073 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 8399.071073 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 8399.071073 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-08-07 18:22:18 +02:00
|
|
|
system.cpu.dcache.replacements 157559 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 4075.605702 # Cycle average of tags in use
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.total_refs 45320510 # Total number of references to valid blocks.
|
2011-08-07 18:22:18 +02:00
|
|
|
system.cpu.dcache.sampled_refs 161655 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 280.353283 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.warmup_cycle 305781000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.occ_blocks::0 4075.605702 # Average occupied blocks per context
|
|
|
|
|
system.cpu.dcache.occ_percent::0 0.995021 # Average percentage of cache occupancy
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_hits 26986553 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits 18297687 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits 18928 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.StoreCondReq_hits 17320 # number of StoreCondReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits 45284240 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits 45284240 # number of overall hits
|
2011-08-07 18:22:18 +02:00
|
|
|
system.cpu.dcache.ReadReq_misses 104970 # number of ReadReq misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.WriteReq_misses 1552214 # number of WriteReq misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_misses 31 # number of LoadLockedReq misses
|
2011-08-07 18:22:18 +02:00
|
|
|
system.cpu.dcache.demand_misses 1657184 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses 1657184 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 2340452000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency 51751426000 # number of WriteReq miss cycles
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency 435500 # number of LoadLockedReq miss cycles
|
2011-08-07 18:22:18 +02:00
|
|
|
system.cpu.dcache.demand_miss_latency 54091878000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 54091878000 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 27091523 # number of ReadReq accesses(hits+misses)
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.WriteReq_accesses 19849901 # number of WriteReq accesses(hits+misses)
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_accesses 18959 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses 17320 # number of StoreCondReq accesses(hits+misses)
|
2011-08-07 18:22:18 +02:00
|
|
|
system.cpu.dcache.demand_accesses 46941424 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses 46941424 # number of overall (read+write) accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.003875 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.078198 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate 0.001635 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate 0.035303 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.035303 # miss rate for overall accesses
|
2011-08-07 18:22:18 +02:00
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 22296.389445 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 33340.393786 # average WriteReq miss latency
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency 14048.387097 # average LoadLockedReq miss latency
|
2011-08-07 18:22:18 +02:00
|
|
|
system.cpu.dcache.demand_avg_miss_latency 32640.840124 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 32640.840124 # average overall miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 165500 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 18388.888889 # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.writebacks 123328 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 50205 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 1445313 # number of WriteReq MSHR hits
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits 31 # number of LoadLockedReq MSHR hits
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.demand_mshr_hits 1495518 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 1495518 # number of overall MSHR hits
|
2011-08-07 18:22:18 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 54765 # number of ReadReq MSHR misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 106901 # number of WriteReq MSHR misses
|
2011-08-07 18:22:18 +02:00
|
|
|
system.cpu.dcache.demand_mshr_misses 161666 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 161666 # number of overall MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-08-07 18:22:18 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 1030429000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 3652589000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 4683018000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 4683018000 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-08-07 18:22:18 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002021 # mshr miss rate for ReadReq accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.005385 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.003444 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.003444 # mshr miss rate for overall accesses
|
2011-08-07 18:22:18 +02:00
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18815.466082 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34167.959140 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 28967.241102 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 28967.241102 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-08-07 18:22:18 +02:00
|
|
|
system.cpu.l2cache.replacements 114936 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 18374.970937 # Cycle average of tags in use
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.total_refs 73734 # Total number of references to valid blocks.
|
2011-08-07 18:22:18 +02:00
|
|
|
system.cpu.l2cache.sampled_refs 133792 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 0.551109 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-08-07 18:22:18 +02:00
|
|
|
system.cpu.l2cache.occ_blocks::0 2397.195703 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 15977.775235 # Average occupied blocks per context
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.occ_percent::0 0.073157 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::1 0.487603 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 51991 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 123328 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_hits 4 # number of UpgradeReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits 4303 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits 56294 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits 56294 # number of overall hits
|
2011-08-07 18:22:18 +02:00
|
|
|
system.cpu.l2cache.ReadReq_misses 32686 # number of ReadReq misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_misses 7 # number of UpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 102588 # number of ReadExReq misses
|
2011-08-07 18:22:18 +02:00
|
|
|
system.cpu.l2cache.demand_misses 135274 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses 135274 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 1117376500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 3525779000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 4643155500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 4643155500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 84677 # number of ReadReq accesses(hits+misses)
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.Writeback_accesses 123328 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses 11 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses 106891 # number of ReadExReq accesses(hits+misses)
|
2011-08-07 18:22:18 +02:00
|
|
|
system.cpu.l2cache.demand_accesses 191568 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses 191568 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.386008 # miss rate for ReadReq accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 0.636364 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.959744 # miss rate for ReadExReq accesses
|
2011-08-07 18:22:18 +02:00
|
|
|
system.cpu.l2cache.demand_miss_rate 0.706141 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.706141 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34185.171021 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34368.337427 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34324.079276 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34324.079276 # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.writebacks 88452 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits 81 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits 81 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 81 # number of overall MSHR hits
|
2011-08-07 18:22:18 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 32605 # number of ReadReq MSHR misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 7 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 102588 # number of ReadExReq MSHR misses
|
2011-08-07 18:22:18 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_misses 135193 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 135193 # number of overall MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-08-07 18:22:18 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 1012653500 # number of ReadReq MSHR miss cycles
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 217000 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 3200382500 # number of ReadExReq MSHR miss cycles
|
2011-08-07 18:22:18 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 4213036000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 4213036000 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-08-07 18:22:18 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.385051 # mshr miss rate for ReadReq accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.636364 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.959744 # mshr miss rate for ReadExReq accesses
|
2011-08-07 18:22:18 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.705718 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.705718 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31058.227266 # average ReadReq mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31196.460600 # average ReadExReq mshr miss latency
|
2011-08-07 18:22:18 +02:00
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31163.122351 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31163.122351 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-01-18 23:30:06 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
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