2011-03-18 01:20:22 +01:00
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---------- Begin Simulation Statistics ----------
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2011-09-13 18:58:09 +02:00
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sim_seconds 2.503588 # Number of seconds simulated
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sim_ticks 2503587516500 # Number of ticks simulated
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2011-03-18 01:20:22 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-09-13 18:58:09 +02:00
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host_inst_rate 84198 # Simulator instruction rate (inst/s)
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host_tick_rate 2745069755 # Simulator tick rate (ticks/s)
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host_mem_usage 385208 # Number of bytes of host memory used
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host_seconds 912.03 # Real time elapsed on the host
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sim_insts 76790714 # Number of instructions simulated
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system.l2c.replacements 119531 # number of replacements
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system.l2c.tagsinuse 25929.939584 # Cycle average of tags in use
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system.l2c.total_refs 1799445 # Total number of references to valid blocks.
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system.l2c.sampled_refs 150368 # Sample count of references to valid blocks.
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system.l2c.avg_refs 11.966941 # Average number of references to valid blocks.
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2011-05-23 17:59:13 +02:00
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system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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2011-09-13 18:58:09 +02:00
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system.l2c.occ_blocks::0 11550.967581 # Average occupied blocks per context
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system.l2c.occ_blocks::1 14378.972003 # Average occupied blocks per context
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system.l2c.occ_percent::0 0.176254 # Average percentage of cache occupancy
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system.l2c.occ_percent::1 0.219406 # Average percentage of cache occupancy
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system.l2c.ReadReq_hits::0 1351962 # number of ReadReq hits
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system.l2c.ReadReq_hits::1 155464 # number of ReadReq hits
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system.l2c.ReadReq_hits::total 1507426 # number of ReadReq hits
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system.l2c.Writeback_hits::0 630774 # number of Writeback hits
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system.l2c.Writeback_hits::total 630774 # number of Writeback hits
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system.l2c.UpgradeReq_hits::0 42 # number of UpgradeReq hits
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system.l2c.UpgradeReq_hits::total 42 # number of UpgradeReq hits
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system.l2c.SCUpgradeReq_hits::0 17 # number of SCUpgradeReq hits
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system.l2c.SCUpgradeReq_hits::total 17 # number of SCUpgradeReq hits
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system.l2c.ReadExReq_hits::0 105933 # number of ReadExReq hits
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system.l2c.ReadExReq_hits::total 105933 # number of ReadExReq hits
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system.l2c.demand_hits::0 1457895 # number of demand (read+write) hits
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system.l2c.demand_hits::1 155464 # number of demand (read+write) hits
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system.l2c.demand_hits::total 1613359 # number of demand (read+write) hits
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system.l2c.overall_hits::0 1457895 # number of overall hits
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system.l2c.overall_hits::1 155464 # number of overall hits
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system.l2c.overall_hits::total 1613359 # number of overall hits
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system.l2c.ReadReq_misses::0 36117 # number of ReadReq misses
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system.l2c.ReadReq_misses::1 148 # number of ReadReq misses
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system.l2c.ReadReq_misses::total 36265 # number of ReadReq misses
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system.l2c.UpgradeReq_misses::0 3244 # number of UpgradeReq misses
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system.l2c.UpgradeReq_misses::total 3244 # number of UpgradeReq misses
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system.l2c.SCUpgradeReq_misses::0 2 # number of SCUpgradeReq misses
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system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
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system.l2c.ReadExReq_misses::0 140419 # number of ReadExReq misses
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system.l2c.ReadExReq_misses::total 140419 # number of ReadExReq misses
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system.l2c.demand_misses::0 176536 # number of demand (read+write) misses
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system.l2c.demand_misses::1 148 # number of demand (read+write) misses
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system.l2c.demand_misses::total 176684 # number of demand (read+write) misses
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system.l2c.overall_misses::0 176536 # number of overall misses
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system.l2c.overall_misses::1 148 # number of overall misses
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system.l2c.overall_misses::total 176684 # number of overall misses
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system.l2c.ReadReq_miss_latency 1896887000 # number of ReadReq miss cycles
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system.l2c.UpgradeReq_miss_latency 953000 # number of UpgradeReq miss cycles
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system.l2c.ReadExReq_miss_latency 7384203500 # number of ReadExReq miss cycles
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system.l2c.demand_miss_latency 9281090500 # number of demand (read+write) miss cycles
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system.l2c.overall_miss_latency 9281090500 # number of overall miss cycles
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system.l2c.ReadReq_accesses::0 1388079 # number of ReadReq accesses(hits+misses)
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system.l2c.ReadReq_accesses::1 155612 # number of ReadReq accesses(hits+misses)
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system.l2c.ReadReq_accesses::total 1543691 # number of ReadReq accesses(hits+misses)
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system.l2c.Writeback_accesses::0 630774 # number of Writeback accesses(hits+misses)
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system.l2c.Writeback_accesses::total 630774 # number of Writeback accesses(hits+misses)
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system.l2c.UpgradeReq_accesses::0 3286 # number of UpgradeReq accesses(hits+misses)
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system.l2c.UpgradeReq_accesses::total 3286 # number of UpgradeReq accesses(hits+misses)
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system.l2c.SCUpgradeReq_accesses::0 19 # number of SCUpgradeReq accesses(hits+misses)
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system.l2c.SCUpgradeReq_accesses::total 19 # number of SCUpgradeReq accesses(hits+misses)
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system.l2c.ReadExReq_accesses::0 246352 # number of ReadExReq accesses(hits+misses)
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system.l2c.ReadExReq_accesses::total 246352 # number of ReadExReq accesses(hits+misses)
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system.l2c.demand_accesses::0 1634431 # number of demand (read+write) accesses
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system.l2c.demand_accesses::1 155612 # number of demand (read+write) accesses
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system.l2c.demand_accesses::total 1790043 # number of demand (read+write) accesses
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system.l2c.overall_accesses::0 1634431 # number of overall (read+write) accesses
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system.l2c.overall_accesses::1 155612 # number of overall (read+write) accesses
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system.l2c.overall_accesses::total 1790043 # number of overall (read+write) accesses
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system.l2c.ReadReq_miss_rate::0 0.026019 # miss rate for ReadReq accesses
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system.l2c.ReadReq_miss_rate::1 0.000951 # miss rate for ReadReq accesses
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system.l2c.ReadReq_miss_rate::total 0.026970 # miss rate for ReadReq accesses
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system.l2c.UpgradeReq_miss_rate::0 0.987219 # miss rate for UpgradeReq accesses
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system.l2c.SCUpgradeReq_miss_rate::0 0.105263 # miss rate for SCUpgradeReq accesses
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system.l2c.ReadExReq_miss_rate::0 0.569993 # miss rate for ReadExReq accesses
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system.l2c.demand_miss_rate::0 0.108011 # miss rate for demand accesses
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system.l2c.demand_miss_rate::1 0.000951 # miss rate for demand accesses
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system.l2c.demand_miss_rate::total 0.108962 # miss rate for demand accesses
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system.l2c.overall_miss_rate::0 0.108011 # miss rate for overall accesses
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system.l2c.overall_miss_rate::1 0.000951 # miss rate for overall accesses
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system.l2c.overall_miss_rate::total 0.108962 # miss rate for overall accesses
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system.l2c.ReadReq_avg_miss_latency::0 52520.613561 # average ReadReq miss latency
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system.l2c.ReadReq_avg_miss_latency::1 12816804.054054 # average ReadReq miss latency
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system.l2c.ReadReq_avg_miss_latency::total 12869324.667616 # average ReadReq miss latency
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system.l2c.UpgradeReq_avg_miss_latency::0 293.773120 # average UpgradeReq miss latency
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2011-05-23 17:59:13 +02:00
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system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
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system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
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2011-09-13 18:58:09 +02:00
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system.l2c.ReadExReq_avg_miss_latency::0 52586.925559 # average ReadExReq miss latency
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2011-05-23 17:59:13 +02:00
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system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
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system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
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2011-09-13 18:58:09 +02:00
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system.l2c.demand_avg_miss_latency::0 52573.358975 # average overall miss latency
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system.l2c.demand_avg_miss_latency::1 62710070.945946 # average overall miss latency
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system.l2c.demand_avg_miss_latency::total 62762644.304921 # average overall miss latency
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system.l2c.overall_avg_miss_latency::0 52573.358975 # average overall miss latency
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system.l2c.overall_avg_miss_latency::1 62710070.945946 # average overall miss latency
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system.l2c.overall_avg_miss_latency::total 62762644.304921 # average overall miss latency
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2011-05-23 17:59:13 +02:00
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system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
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system.l2c.blocked::no_targets 0 # number of cycles access was blocked
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system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.l2c.fast_writes 0 # number of fast writes performed
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system.l2c.cache_copies 0 # number of cache copies performed
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2011-09-13 18:58:09 +02:00
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system.l2c.writebacks 102665 # number of writebacks
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system.l2c.ReadReq_mshr_hits 95 # number of ReadReq MSHR hits
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system.l2c.demand_mshr_hits 95 # number of demand (read+write) MSHR hits
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system.l2c.overall_mshr_hits 95 # number of overall MSHR hits
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system.l2c.ReadReq_mshr_misses 36170 # number of ReadReq MSHR misses
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system.l2c.UpgradeReq_mshr_misses 3244 # number of UpgradeReq MSHR misses
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system.l2c.SCUpgradeReq_mshr_misses 2 # number of SCUpgradeReq MSHR misses
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system.l2c.ReadExReq_mshr_misses 140419 # number of ReadExReq MSHR misses
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system.l2c.demand_mshr_misses 176589 # number of demand (read+write) MSHR misses
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system.l2c.overall_mshr_misses 176589 # number of overall MSHR misses
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2011-05-23 17:59:13 +02:00
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system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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2011-09-13 18:58:09 +02:00
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system.l2c.ReadReq_mshr_miss_latency 1451509500 # number of ReadReq MSHR miss cycles
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system.l2c.UpgradeReq_mshr_miss_latency 130965000 # number of UpgradeReq MSHR miss cycles
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system.l2c.SCUpgradeReq_mshr_miss_latency 80000 # number of SCUpgradeReq MSHR miss cycles
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system.l2c.ReadExReq_mshr_miss_latency 5640198500 # number of ReadExReq MSHR miss cycles
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system.l2c.demand_mshr_miss_latency 7091708000 # number of demand (read+write) MSHR miss cycles
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system.l2c.overall_mshr_miss_latency 7091708000 # number of overall MSHR miss cycles
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system.l2c.ReadReq_mshr_uncacheable_latency 131769561500 # number of ReadReq MSHR uncacheable cycles
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system.l2c.WriteReq_mshr_uncacheable_latency 32342663570 # number of WriteReq MSHR uncacheable cycles
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system.l2c.overall_mshr_uncacheable_latency 164112225070 # number of overall MSHR uncacheable cycles
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system.l2c.ReadReq_mshr_miss_rate::0 0.026058 # mshr miss rate for ReadReq accesses
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system.l2c.ReadReq_mshr_miss_rate::1 0.232437 # mshr miss rate for ReadReq accesses
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system.l2c.ReadReq_mshr_miss_rate::total 0.258495 # mshr miss rate for ReadReq accesses
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system.l2c.UpgradeReq_mshr_miss_rate::0 0.987219 # mshr miss rate for UpgradeReq accesses
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2011-05-23 17:59:13 +02:00
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system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
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system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
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2011-09-13 18:58:09 +02:00
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system.l2c.SCUpgradeReq_mshr_miss_rate::0 0.105263 # mshr miss rate for SCUpgradeReq accesses
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2011-08-19 22:08:08 +02:00
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system.l2c.SCUpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for SCUpgradeReq accesses
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system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses
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2011-09-13 18:58:09 +02:00
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system.l2c.ReadExReq_mshr_miss_rate::0 0.569993 # mshr miss rate for ReadExReq accesses
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2011-05-23 17:59:13 +02:00
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system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
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system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
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2011-09-13 18:58:09 +02:00
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system.l2c.demand_mshr_miss_rate::0 0.108043 # mshr miss rate for demand accesses
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system.l2c.demand_mshr_miss_rate::1 1.134803 # mshr miss rate for demand accesses
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system.l2c.demand_mshr_miss_rate::total 1.242846 # mshr miss rate for demand accesses
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system.l2c.overall_mshr_miss_rate::0 0.108043 # mshr miss rate for overall accesses
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system.l2c.overall_mshr_miss_rate::1 1.134803 # mshr miss rate for overall accesses
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system.l2c.overall_mshr_miss_rate::total 1.242846 # mshr miss rate for overall accesses
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system.l2c.ReadReq_avg_mshr_miss_latency 40130.204589 # average ReadReq mshr miss latency
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system.l2c.UpgradeReq_avg_mshr_miss_latency 40371.454994 # average UpgradeReq mshr miss latency
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2011-08-19 22:08:08 +02:00
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system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40000 # average SCUpgradeReq mshr miss latency
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2011-09-13 18:58:09 +02:00
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system.l2c.ReadExReq_avg_mshr_miss_latency 40166.918295 # average ReadExReq mshr miss latency
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system.l2c.demand_avg_mshr_miss_latency 40159.398377 # average overall mshr miss latency
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system.l2c.overall_avg_mshr_miss_latency 40159.398377 # average overall mshr miss latency
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2011-05-23 17:59:13 +02:00
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system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
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system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
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system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
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system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
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system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
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2011-08-19 22:08:09 +02:00
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system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
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system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
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system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
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system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
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system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
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system.cf0.dma_write_txs 0 # Number of DMA write transactions.
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2011-05-23 17:59:13 +02:00
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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2011-09-13 18:58:09 +02:00
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system.cpu.dtb.read_hits 52225825 # DTB read hits
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system.cpu.dtb.read_misses 89986 # DTB read misses
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system.cpu.dtb.write_hits 11975736 # DTB write hits
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system.cpu.dtb.write_misses 26350 # DTB write misses
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2011-03-18 01:20:22 +01:00
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system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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2011-08-19 22:08:09 +02:00
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system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
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2011-09-13 18:58:09 +02:00
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system.cpu.dtb.flush_entries 4338 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 8018 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 617 # Number of TLB faults due to prefetch
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2011-05-23 17:59:13 +02:00
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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2011-09-13 18:58:09 +02:00
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system.cpu.dtb.perms_faults 2450 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 52315811 # DTB read accesses
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system.cpu.dtb.write_accesses 12002086 # DTB write accesses
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2011-03-18 01:20:22 +01:00
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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2011-09-13 18:58:09 +02:00
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system.cpu.dtb.hits 64201561 # DTB hits
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|
|
|
|
system.cpu.dtb.misses 116336 # DTB misses
|
|
|
|
|
system.cpu.dtb.accesses 64317897 # DTB accesses
|
|
|
|
|
system.cpu.itb.inst_hits 14135631 # ITB inst hits
|
|
|
|
|
system.cpu.itb.inst_misses 11185 # ITB inst misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.itb.flush_entries 2607 # Number of entries that have been flushed from TLB
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
|
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.itb.perms_faults 8440 # Number of TLB faults due to permissions restrictions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.itb.inst_accesses 14146816 # ITB inst accesses
|
|
|
|
|
system.cpu.itb.hits 14135631 # DTB hits
|
|
|
|
|
system.cpu.itb.misses 11185 # DTB misses
|
|
|
|
|
system.cpu.itb.accesses 14146816 # DTB accesses
|
|
|
|
|
system.cpu.numCycles 415920995 # number of cpu cycles simulated
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
|
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.BPredUnit.lookups 16219215 # Number of BP lookups
|
|
|
|
|
system.cpu.BPredUnit.condPredicted 12559944 # Number of conditional branches predicted
|
|
|
|
|
system.cpu.BPredUnit.condIncorrect 1110172 # Number of conditional branches incorrect
|
|
|
|
|
system.cpu.BPredUnit.BTBLookups 13927920 # Number of BTB lookups
|
|
|
|
|
system.cpu.BPredUnit.BTBHits 10224432 # Number of BTB hits
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.BPredUnit.usedRAS 1424516 # Number of times the RAS was used to get a target.
|
|
|
|
|
system.cpu.BPredUnit.RASInCorrect 228409 # Number of incorrect RAS predictions.
|
|
|
|
|
system.cpu.fetch.icacheStallCycles 32955891 # Number of cycles fetch is stalled on an Icache miss
|
|
|
|
|
system.cpu.fetch.Insts 104818490 # Number of instructions fetch has processed
|
|
|
|
|
system.cpu.fetch.Branches 16219215 # Number of branches that fetch encountered
|
|
|
|
|
system.cpu.fetch.predictedBranches 11648948 # Number of branches that fetch has predicted taken
|
|
|
|
|
system.cpu.fetch.Cycles 24471055 # Number of cycles fetch has run and was not squashing or blocked
|
|
|
|
|
system.cpu.fetch.SquashCycles 7079806 # Number of cycles fetch has spent squashing
|
|
|
|
|
system.cpu.fetch.TlbCycles 137198 # Number of cycles fetch has spent waiting for tlb
|
|
|
|
|
system.cpu.fetch.BlockedCycles 92799321 # Number of cycles fetch has spent blocked
|
|
|
|
|
system.cpu.fetch.MiscStallCycles 1248 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
|
|
|
system.cpu.fetch.PendingTrapStallCycles 151217 # Number of stall cycles due to pending traps
|
|
|
|
|
system.cpu.fetch.PendingQuiesceStallCycles 217200 # Number of stall cycles due to pending quiesce instructions
|
|
|
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 351 # Number of stall cycles due to full MSHR
|
|
|
|
|
system.cpu.fetch.CacheLines 14126420 # Number of cache lines fetched
|
|
|
|
|
system.cpu.fetch.IcacheSquashes 1047323 # Number of outstanding Icache misses that were squashed
|
|
|
|
|
system.cpu.fetch.ItlbSquashes 6165 # Number of outstanding ITLB misses that were squashed
|
|
|
|
|
system.cpu.fetch.rateDist::samples 155547085 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::mean 0.838560 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::stdev 2.184344 # Number of instructions fetched each cycle (Total)
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.fetch.rateDist::0 131101786 84.28% 84.28% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::1 1736791 1.12% 85.40% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::2 2601051 1.67% 87.07% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::3 3653656 2.35% 89.42% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::4 2169863 1.39% 90.82% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::5 1434892 0.92% 91.74% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::6 2627328 1.69% 93.43% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::7 855909 0.55% 93.98% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::8 9365809 6.02% 100.00% # Number of instructions fetched each cycle (Total)
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.fetch.rateDist::total 155547085 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.branchRate 0.038996 # Number of branch fetches per cycle
|
|
|
|
|
system.cpu.fetch.rate 0.252015 # Number of inst fetches per cycle
|
|
|
|
|
system.cpu.decode.IdleCycles 35186802 # Number of cycles decode is idle
|
|
|
|
|
system.cpu.decode.BlockedCycles 92649693 # Number of cycles decode is blocked
|
|
|
|
|
system.cpu.decode.RunCycles 21977926 # Number of cycles decode is running
|
|
|
|
|
system.cpu.decode.UnblockCycles 1094000 # Number of cycles decode is unblocking
|
|
|
|
|
system.cpu.decode.SquashCycles 4638664 # Number of cycles decode is squashing
|
|
|
|
|
system.cpu.decode.BranchResolved 2316854 # Number of times decode resolved a branch
|
|
|
|
|
system.cpu.decode.BranchMispred 177884 # Number of times decode detected a branch misprediction
|
|
|
|
|
system.cpu.decode.DecodedInsts 122073457 # Number of instructions handled by decode
|
|
|
|
|
system.cpu.decode.SquashedInsts 575981 # Number of squashed instructions handled by decode
|
|
|
|
|
system.cpu.rename.SquashCycles 4638664 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.IdleCycles 37340555 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.BlockCycles 36816085 # Number of cycles rename is blocking
|
|
|
|
|
system.cpu.rename.serializeStallCycles 49864787 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.RunCycles 20912628 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.UnblockCycles 5974366 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.RenamedInsts 113922984 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.ROBFullEvents 4414 # Number of times rename has blocked due to ROB full
|
|
|
|
|
system.cpu.rename.IQFullEvents 914987 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu.rename.LSQFullEvents 3980816 # Number of times rename has blocked due to LSQ full
|
|
|
|
|
system.cpu.rename.FullRegisterEvents 42327 # Number of times there has been no free registers
|
|
|
|
|
system.cpu.rename.RenamedOperands 118460665 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RenameLookups 523781573 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.int_rename_lookups 523685374 # Number of integer rename lookups
|
|
|
|
|
system.cpu.rename.fp_rename_lookups 96199 # Number of floating rename lookups
|
|
|
|
|
system.cpu.rename.CommittedMaps 77493785 # Number of HB maps that are committed
|
|
|
|
|
system.cpu.rename.UndoneMaps 40966879 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.serializingInsts 1201529 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.tempSerializingInsts 1095575 # count of temporary serializing insts renamed
|
|
|
|
|
system.cpu.rename.skidInsts 12285551 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu.memDep0.insertedLoads 22000628 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.insertedStores 14180796 # Number of stores inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.conflictingLoads 1905529 # Number of conflicting loads.
|
|
|
|
|
system.cpu.memDep0.conflictingStores 2295702 # Number of conflicting stores.
|
|
|
|
|
system.cpu.iq.iqInstsAdded 102943309 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 1872075 # Number of non-speculative instructions added to the IQ
|
|
|
|
|
system.cpu.iq.iqInstsIssued 126931651 # Number of instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 252428 # Number of squashed instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedInstsExamined 27053062 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 73124308 # Number of squashed operands that are examined and possibly removed from graph
|
|
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 373806 # Number of squashed non-spec instructions that were removed
|
|
|
|
|
system.cpu.iq.issued_per_cycle::samples 155547085 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::mean 0.816034 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::stdev 1.505599 # Number of insts issued each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::0 108904431 70.01% 70.01% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::1 15118772 9.72% 79.73% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::2 7542016 4.85% 84.58% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::3 6525767 4.20% 88.78% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::4 12768009 8.21% 96.99% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::5 2736654 1.76% 98.75% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::6 1396269 0.90% 99.64% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::7 422710 0.27% 99.91% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::8 132457 0.09% 100.00% # Number of insts issued each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::total 155547085 # Number of insts issued each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iq.fu_full::IntAlu 45562 0.51% 0.51% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IntMult 5 0.00% 0.51% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.51% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.51% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.51% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.51% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 0.51% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.51% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.51% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.51% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.51% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.51% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.51% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.51% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.51% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 0.51% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.51% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.51% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.51% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.51% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.51% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.51% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.51% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.51% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.51% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.51% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.51% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.51% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.51% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemRead 8415938 94.58% 95.09% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemWrite 436851 4.91% 100.00% # attempts to use FU when none available
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.iq.FU_type_0::No_OpClass 106530 0.08% 0.08% # Type of FU issued
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iq.FU_type_0::IntAlu 60109955 47.36% 47.44% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntMult 96551 0.08% 47.52% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.52% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.52% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.52% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.52% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.52% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.52% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.52% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.52% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.52% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.52% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 1 0.00% 47.52% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.52% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 3 0.00% 47.52% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.52% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.52% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.52% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 3 0.00% 47.52% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.52% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.52% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.52% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.52% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.52% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.52% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 2253 0.00% 47.52% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.52% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 47.52% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.52% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemRead 53954328 42.51% 90.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 12662017 9.98% 100.00% # Type of FU issued
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iq.FU_type_0::total 126931651 # Type of FU issued
|
|
|
|
|
system.cpu.iq.rate 0.305182 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 8898356 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.070104 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 418652883 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 131886553 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 87334534 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 23945 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 13416 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 10473 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_alu_accesses 135710724 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 12753 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 616189 # Number of loads that had data forwarded from stores
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 6319666 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 11234 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 32604 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 2401616 # Number of stores squashed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 34061863 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 1153574 # Number of times an access to memory failed due to the cache being blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 4638664 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 28343669 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 418971 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 105030898 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 476967 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 22000628 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 14180796 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 1225085 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 85041 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 7449 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 32604 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 851635 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 257956 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 1109591 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 123477395 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 52923959 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 3454256 # Number of squashed instructions skipped in execute
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.exec_nop 215514 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_refs 65415175 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 11714146 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 12491216 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 0.296877 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 121817988 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 87345007 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 47064551 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 86684992 # num instructions consuming a value
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.wb_rate 0.210004 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.542938 # average fanout of values written-back
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.commitCommittedInsts 76941095 # The number of committed instructions
|
|
|
|
|
system.cpu.commit.commitSquashedInsts 27854412 # The number of squashed insts skipped by commit
|
|
|
|
|
system.cpu.commit.commitNonSpecStalls 1498269 # The number of times commit has been forced to stall to communicate backwards
|
|
|
|
|
system.cpu.commit.branchMispredicts 978817 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 150990773 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 0.509575 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 1.459429 # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::0 122133629 80.89% 80.89% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 14849154 9.83% 90.72% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 4108732 2.72% 93.44% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 2181203 1.44% 94.89% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 1788420 1.18% 96.07% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 1359682 0.90% 96.97% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 1260703 0.83% 97.81% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 659440 0.44% 98.25% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 2649810 1.75% 100.00% # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::total 150990773 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.count 76941095 # Number of instructions committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.refs 27460142 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads 15680962 # Number of loads committed
|
|
|
|
|
system.cpu.commit.membars 413062 # Number of memory barriers committed
|
|
|
|
|
system.cpu.commit.branches 9891108 # Number of branches committed
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.int_insts 68494112 # Number of committed integer instructions.
|
|
|
|
|
system.cpu.commit.function_calls 995603 # Number of function calls committed.
|
|
|
|
|
system.cpu.commit.bw_lim_events 2649810 # number cycles where commit BW limit reached
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.rob.rob_reads 251379971 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 214361160 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 1877573 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 260373910 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.committedInsts 76790714 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 76790714 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.cpi 5.416293 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 5.416293 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 0.184628 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 0.184628 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 559837261 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 89743570 # number of integer regfile writes
|
|
|
|
|
system.cpu.fp_regfile_reads 8283 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 2809 # number of floating regfile writes
|
|
|
|
|
system.cpu.misc_regfile_reads 137364406 # number of misc regfile reads
|
|
|
|
|
system.cpu.misc_regfile_writes 912286 # number of misc regfile writes
|
|
|
|
|
system.cpu.icache.replacements 993006 # number of replacements
|
|
|
|
|
system.cpu.icache.tagsinuse 511.614815 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 13045370 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.sampled_refs 993518 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.avg_refs 13.130482 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.warmup_cycle 6445921000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.occ_blocks::0 511.614815 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.occ_percent::0 0.999248 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits::0 13045370 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_hits::total 13045370 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits::0 13045370 # number of demand (read+write) hits
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.demand_hits::total 13045370 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits::0 13045370 # number of overall hits
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_hits::1 0 # number of overall hits
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.overall_hits::total 13045370 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses::0 1080929 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_misses::total 1080929 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses::0 1080929 # number of demand (read+write) misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.demand_misses::total 1080929 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses::0 1080929 # number of overall misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_misses::1 0 # number of overall misses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.overall_misses::total 1080929 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 15935046488 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency 15935046488 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency 15935046488 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::0 14126299 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::total 14126299 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses::0 14126299 # number of demand (read+write) accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.demand_accesses::total 14126299 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::0 14126299 # number of overall (read+write) accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.overall_accesses::total 14126299 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::0 0.076519 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::0 0.076519 # miss rate for demand accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.overall_miss_rate::0 0.076519 # miss rate for overall accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::0 14741.991831 # average ReadReq miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.demand_avg_miss_latency::0 14741.991831 # average overall miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.overall_avg_miss_latency::0 14741.991831 # average overall miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 2385493 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.blocked::no_mshrs 357 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 6682.053221 # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.writebacks 57770 # number of writebacks
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits 87373 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 87373 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 87373 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 993556 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 993556 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 993556 # number of overall MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 11874405493 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 11874405493 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 11874405493 # number of overall MSHR miss cycles
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_uncacheable_latency 6359500 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 6359500 # number of overall MSHR uncacheable cycles
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::0 0.070334 # mshr miss rate for ReadReq accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.demand_mshr_miss_rate::0 0.070334 # mshr miss rate for demand accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.overall_mshr_miss_rate::0 0.070334 # mshr miss rate for overall accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11951.420446 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 11951.420446 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 11951.420446 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.replacements 644346 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 511.991681 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 22273031 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 644858 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 34.539435 # Average number of references to valid blocks.
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.dcache.warmup_cycle 48663000 # Cycle when the warmup percentage was hit.
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.occ_blocks::0 511.991681 # Average occupied blocks per context
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.dcache.occ_percent::0 0.999984 # Average percentage of cache occupancy
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_hits::0 14419247 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::total 14419247 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::0 7264920 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::total 7264920 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits::0 299971 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits::total 299971 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.StoreCondReq_hits::0 285485 # number of StoreCondReq hits
|
|
|
|
|
system.cpu.dcache.StoreCondReq_hits::total 285485 # number of StoreCondReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits::0 21684167 # number of demand (read+write) hits
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.demand_hits::total 21684167 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits::0 21684167 # number of overall hits
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_hits::1 0 # number of overall hits
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.overall_hits::total 21684167 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::0 724263 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::total 724263 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::0 2966438 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::total 2966438 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_misses::0 13488 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_misses::total 13488 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu.dcache.StoreCondReq_misses::0 19 # number of StoreCondReq misses
|
|
|
|
|
system.cpu.dcache.StoreCondReq_misses::total 19 # number of StoreCondReq misses
|
|
|
|
|
system.cpu.dcache.demand_misses::0 3690701 # number of demand (read+write) misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.demand_misses::total 3690701 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses::0 3690701 # number of overall misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_misses::1 0 # number of overall misses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.overall_misses::total 3690701 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 10889184500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency 110353624242 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency 218944000 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu.dcache.StoreCondReq_miss_latency 357000 # number of StoreCondReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency 121242808742 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 121242808742 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::0 15143510 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::total 15143510 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::0 10231358 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::total 10231358 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_accesses::0 313459 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 313459 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses::0 285504 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses::total 285504 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.demand_accesses::0 25374868 # number of demand (read+write) accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.demand_accesses::total 25374868 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::0 25374868 # number of overall (read+write) accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.overall_accesses::total 25374868 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::0 0.047827 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::0 0.289936 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::0 0.043030 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.StoreCondReq_miss_rate::0 0.000067 # miss rate for StoreCondReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::0 0.145447 # miss rate for demand accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.overall_miss_rate::0 0.145447 # miss rate for overall accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::0 15034.848529 # average ReadReq miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::0 37200.718249 # average WriteReq miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 16232.502966 # average LoadLockedReq miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::0 18789.473684 # average StoreCondReq miss latency
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
|
|
|
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.demand_avg_miss_latency::0 32850.888962 # average overall miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.overall_avg_miss_latency::0 32850.888962 # average overall miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 16719933 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 7529000 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_mshrs 2957 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 277 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 5654.356781 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 27180.505415 # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.writebacks 573004 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 337704 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 2716896 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits 1445 # number of LoadLockedReq MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits 3054600 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 3054600 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 386559 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 249542 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses 12043 # number of LoadLockedReq MSHR misses
|
|
|
|
|
system.cpu.dcache.StoreCondReq_mshr_misses 19 # number of StoreCondReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses 636101 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 636101 # number of overall MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 5253783500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 8925189433 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 161542500 # number of LoadLockedReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency 293500 # number of StoreCondReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 14178972933 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 14178972933 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency 147158793000 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency 42258212210 # number of WriteReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 189417005210 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.025526 # mshr miss rate for ReadReq accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.024390 # mshr miss rate for WriteReq accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.038420 # mshr miss rate for LoadLockedReq accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000067 # mshr miss rate for StoreCondReq accesses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
|
|
|
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::0 0.025068 # mshr miss rate for demand accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::0 0.025068 # mshr miss rate for overall accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13591.155555 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35766.281560 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 13413.808852 # average LoadLockedReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 15447.368421 # average StoreCondReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 22290.442765 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 22290.442765 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.iocache.replacements 0 # number of replacements
|
|
|
|
|
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
|
|
|
|
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
|
|
|
|
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
2011-03-18 01:20:22 +01:00
|
|
|
system.iocache.avg_refs no_value # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-03-18 01:20:22 +01:00
|
|
|
system.iocache.demand_hits::0 0 # number of demand (read+write) hits
|
|
|
|
|
system.iocache.demand_hits::1 0 # number of demand (read+write) hits
|
|
|
|
|
system.iocache.demand_hits::total 0 # number of demand (read+write) hits
|
2011-05-23 17:59:13 +02:00
|
|
|
system.iocache.overall_hits::0 0 # number of overall hits
|
|
|
|
|
system.iocache.overall_hits::1 0 # number of overall hits
|
|
|
|
|
system.iocache.overall_hits::total 0 # number of overall hits
|
2011-03-18 01:20:22 +01:00
|
|
|
system.iocache.demand_misses::0 0 # number of demand (read+write) misses
|
|
|
|
|
system.iocache.demand_misses::1 0 # number of demand (read+write) misses
|
|
|
|
|
system.iocache.demand_misses::total 0 # number of demand (read+write) misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.iocache.overall_misses::0 0 # number of overall misses
|
|
|
|
|
system.iocache.overall_misses::1 0 # number of overall misses
|
|
|
|
|
system.iocache.overall_misses::total 0 # number of overall misses
|
|
|
|
|
system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
|
|
|
|
system.iocache.overall_miss_latency 0 # number of overall miss cycles
|
|
|
|
|
system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
|
|
|
|
|
system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses
|
|
|
|
|
system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
|
|
|
|
|
system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses
|
|
|
|
|
system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
|
|
|
|
|
system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
|
|
|
|
system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
|
|
|
|
|
system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
|
|
|
|
system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
|
|
|
|
|
system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency
|
|
|
|
|
system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
|
|
|
|
|
system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
|
|
|
|
|
system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency
|
|
|
|
|
system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
|
|
|
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.iocache.writebacks 0 # number of writebacks
|
|
|
|
|
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2011-03-18 01:20:22 +01:00
|
|
|
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
|
2011-05-23 17:59:13 +02:00
|
|
|
system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
|
|
|
|
|
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
|
2011-03-18 01:20:22 +01:00
|
|
|
system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
|
2011-09-13 18:58:09 +02:00
|
|
|
system.iocache.ReadReq_mshr_uncacheable_latency 1307895610037 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.iocache.overall_mshr_uncacheable_latency 1307895610037 # number of overall MSHR uncacheable cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
|
|
|
|
|
system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
|
|
|
|
|
system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
|
|
|
|
|
system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
|
|
|
|
|
system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
|
|
|
|
system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
2011-08-19 22:08:09 +02:00
|
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
|
|
|
|
system.iocache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-03-18 01:20:22 +01:00
|
|
|
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.kern.inst.quiesce 87985 # number of quiesce instructions executed
|
2011-03-18 01:20:22 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
