gem5/src/sim/SConscript

# -*- mode:python -*-

# Copyright (c) 2006 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Nathan Binkert

Import('*')

SimObject('BaseTLB.py')
SimObject('Root.py')
SimObject('InstTracer.py')

Source('async.cc')
Source('core.cc')
Source('debug.cc')
Source('eventq.cc')
Source('init.cc')
Source('main.cc', bin_only=True)
Source('root.cc')
Source('serialize.cc')
Source('sim_events.cc')
Source('sim_object.cc')
Source('simulate.cc')
Source('stat_control.cc')

if env['TARGET_ISA'] != 'no':
    SimObject('System.py')
    Source('faults.cc')
    Source('pseudo_inst.cc')
    Source('system.cc')

if env['FULL_SYSTEM']:
    Source('arguments.cc')
elif env['TARGET_ISA'] != 'no':
    Source('tlb.cc')
    SimObject('Process.py')

    Source('process.cc')
    Source('syscall_emul.cc')

TraceFlag('Checkpoint')
TraceFlag('Config')
TraceFlag('Event')
TraceFlag('Fault')
TraceFlag('Flow')
TraceFlag('IPI')
TraceFlag('IPR')
TraceFlag('Interrupt')
TraceFlag('Loader')
TraceFlag('Stack')
TraceFlag('SyscallVerbose')
TraceFlag('TLB')
TraceFlag('Thread')
TraceFlag('Timer')
TraceFlag('VtoPhys')