2009-10-27 17:24:40 +01:00
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---------- Begin Simulation Statistics ----------
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2010-06-07 00:39:10 +02:00
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host_inst_rate 82571 # Simulator instruction rate (inst/s)
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host_mem_usage 202992 # Number of bytes of host memory used
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host_seconds 0.07 # Real time elapsed on the host
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host_tick_rate 168278845 # Simulator tick rate (ticks/s)
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2009-10-27 17:24:40 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 5800 # Number of instructions simulated
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sim_seconds 0.000012 # Number of seconds simulated
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2010-05-14 05:45:59 +02:00
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sim_ticks 11864500 # Number of ticks simulated
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2009-10-27 17:24:40 +01:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2010-05-14 05:45:59 +02:00
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system.cpu.BPredUnit.BTBHits 687 # Number of BTB hits
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system.cpu.BPredUnit.BTBLookups 1888 # Number of BTB lookups
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2009-10-27 17:24:40 +01:00
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system.cpu.BPredUnit.RASInCorrect 31 # Number of incorrect RAS predictions.
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2010-05-14 05:45:59 +02:00
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system.cpu.BPredUnit.condIncorrect 387 # Number of conditional branches incorrect
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system.cpu.BPredUnit.condPredicted 1757 # Number of conditional branches predicted
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system.cpu.BPredUnit.lookups 2100 # Number of BP lookups
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system.cpu.BPredUnit.usedRAS 189 # Number of times the RAS was used to get a target.
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2009-10-27 17:24:40 +01:00
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system.cpu.commit.COM:branches 1038 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 51 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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2010-05-14 05:45:59 +02:00
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system.cpu.commit.COM:committed_per_cycle::samples 10785 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::mean 0.537784 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::stdev 1.251292 # Number of insts commited each cycle
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2009-10-27 17:24:40 +01:00
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system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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2010-06-07 00:39:10 +02:00
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system.cpu.commit.COM:committed_per_cycle::0 8225 76.26% 76.26% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::1 1129 10.47% 86.73% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::2 673 6.24% 92.97% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::3 258 2.39% 95.36% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::4 226 2.10% 97.46% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::5 120 1.11% 98.57% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::6 82 0.76% 99.33% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::7 21 0.19% 99.53% # Number of insts commited each cycle
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2009-10-27 17:24:40 +01:00
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system.cpu.commit.COM:committed_per_cycle::8 51 0.47% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
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2010-05-14 05:45:59 +02:00
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system.cpu.commit.COM:committed_per_cycle::total 10785 # Number of insts commited each cycle
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2009-10-27 17:24:40 +01:00
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system.cpu.commit.COM:count 5800 # Number of instructions committed
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system.cpu.commit.COM:loads 962 # Number of loads committed
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system.cpu.commit.COM:membars 7 # Number of memory barriers committed
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system.cpu.commit.COM:refs 2008 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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2010-05-14 05:45:59 +02:00
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system.cpu.commit.branchMispredicts 240 # The number of times a branch was mispredicted
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2009-10-27 17:24:40 +01:00
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system.cpu.commit.commitCommittedInsts 5800 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards
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2010-05-14 05:45:59 +02:00
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system.cpu.commit.commitSquashedInsts 3389 # The number of squashed insts skipped by commit
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2009-10-27 17:24:40 +01:00
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system.cpu.committedInsts 5800 # Number of Instructions Simulated
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system.cpu.committedInsts_total 5800 # Number of Instructions Simulated
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2010-05-14 05:45:59 +02:00
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system.cpu.cpi 4.091379 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 4.091379 # CPI: Total CPI of All Threads
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system.cpu.dcache.ReadReq_accesses 1444 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 33612.359551 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34464.285714 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 1355 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 2991500 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.061634 # miss rate for ReadReq accesses
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2009-10-27 17:24:40 +01:00
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system.cpu.dcache.ReadReq_misses 89 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 33 # number of ReadReq MSHR hits
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2010-05-14 05:45:59 +02:00
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system.cpu.dcache.ReadReq_mshr_miss_latency 1930000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.038781 # mshr miss rate for ReadReq accesses
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2009-10-27 17:24:40 +01:00
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system.cpu.dcache.ReadReq_mshr_misses 56 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 1046 # number of WriteReq accesses(hits+misses)
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2010-05-14 05:45:59 +02:00
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system.cpu.dcache.WriteReq_avg_miss_latency 33542.735043 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36053.846154 # average WriteReq mshr miss latency
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2009-10-27 17:24:40 +01:00
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system.cpu.dcache.WriteReq_hits 695 # number of WriteReq hits
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2010-05-14 05:45:59 +02:00
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system.cpu.dcache.WriteReq_miss_latency 11773500 # number of WriteReq miss cycles
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2009-10-27 17:24:40 +01:00
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system.cpu.dcache.WriteReq_miss_rate 0.335564 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 351 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 286 # number of WriteReq MSHR hits
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2010-05-14 05:45:59 +02:00
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system.cpu.dcache.WriteReq_mshr_miss_latency 2343500 # number of WriteReq MSHR miss cycles
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2009-10-27 17:24:40 +01:00
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.062141 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 65 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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2010-05-14 05:45:59 +02:00
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system.cpu.dcache.avg_refs 20.125000 # Average number of references to valid blocks.
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2009-10-27 17:24:40 +01:00
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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2010-05-14 05:45:59 +02:00
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system.cpu.dcache.demand_accesses 2490 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 33556.818182 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 35318.181818 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 2050 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 14765000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.176707 # miss rate for demand accesses
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2009-10-27 17:24:40 +01:00
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system.cpu.dcache.demand_misses 440 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 319 # number of demand (read+write) MSHR hits
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2010-05-14 05:45:59 +02:00
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system.cpu.dcache.demand_mshr_miss_latency 4273500 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.048594 # mshr miss rate for demand accesses
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2009-10-27 17:24:40 +01:00
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system.cpu.dcache.demand_mshr_misses 121 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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2010-05-14 05:45:59 +02:00
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system.cpu.dcache.occ_%::0 0.016240 # Average percentage of cache occupancy
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system.cpu.dcache.occ_blocks::0 66.517345 # Average occupied blocks per context
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system.cpu.dcache.overall_accesses 2490 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 33556.818182 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 35318.181818 # average overall mshr miss latency
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2009-10-27 17:24:40 +01:00
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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2010-05-14 05:45:59 +02:00
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system.cpu.dcache.overall_hits 2050 # number of overall hits
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system.cpu.dcache.overall_miss_latency 14765000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.176707 # miss rate for overall accesses
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2009-10-27 17:24:40 +01:00
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system.cpu.dcache.overall_misses 440 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 319 # number of overall MSHR hits
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2010-05-14 05:45:59 +02:00
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system.cpu.dcache.overall_mshr_miss_latency 4273500 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.048594 # mshr miss rate for overall accesses
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2009-10-27 17:24:40 +01:00
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system.cpu.dcache.overall_mshr_misses 121 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 0 # number of replacements
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system.cpu.dcache.sampled_refs 104 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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2010-05-14 05:45:59 +02:00
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system.cpu.dcache.tagsinuse 66.517345 # Cycle average of tags in use
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system.cpu.dcache.total_refs 2093 # Total number of references to valid blocks.
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2009-10-27 17:24:40 +01:00
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 0 # number of writebacks
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2010-05-14 05:45:59 +02:00
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system.cpu.decode.DECODE:BlockedCycles 1153 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 150 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 267 # Number of times decode resolved a branch
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system.cpu.decode.DECODE:DecodedInsts 10406 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 7618 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 1941 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 570 # Number of cycles decode is squashing
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2009-10-27 17:24:40 +01:00
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system.cpu.decode.DECODE:SquashedInsts 416 # Number of squashed instructions handled by decode
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2010-05-14 05:45:59 +02:00
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system.cpu.decode.DECODE:UnblockCycles 73 # Number of cycles decode is unblocking
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2009-10-27 17:24:40 +01:00
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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2010-05-14 05:45:59 +02:00
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system.cpu.fetch.Branches 2100 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 1490 # Number of cache lines fetched
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system.cpu.fetch.Cycles 3561 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 225 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 11687 # Number of instructions fetch has processed
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system.cpu.fetch.SquashCycles 410 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.088496 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 1490 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 876 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 0.492499 # Number of inst fetches per cycle
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system.cpu.fetch.rateDist::samples 11355 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 1.029238 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.423250 # Number of instructions fetched each cycle (Total)
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2009-10-27 17:24:40 +01:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2010-06-07 00:39:10 +02:00
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system.cpu.fetch.rateDist::0 9285 81.77% 81.77% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 161 1.42% 83.19% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 189 1.66% 84.85% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 155 1.37% 86.22% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 202 1.78% 88.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 136 1.20% 89.19% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 272 2.40% 91.59% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 77 0.68% 92.27% # Number of instructions fetched each cycle (Total)
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2010-05-14 05:45:59 +02:00
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system.cpu.fetch.rateDist::8 878 7.73% 100.00% # Number of instructions fetched each cycle (Total)
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2009-10-27 17:24:40 +01:00
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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2010-05-14 05:45:59 +02:00
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system.cpu.fetch.rateDist::total 11355 # Number of instructions fetched each cycle (Total)
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system.cpu.icache.ReadReq_accesses 1490 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 36423.575130 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 34778.614458 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 1104 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 14059500 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.259060 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 386 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_hits 54 # number of ReadReq MSHR hits
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system.cpu.icache.ReadReq_mshr_miss_latency 11546500 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.222819 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 332 # number of ReadReq MSHR misses
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2009-10-27 17:24:40 +01:00
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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2010-05-14 05:45:59 +02:00
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system.cpu.icache.avg_refs 3.325301 # Average number of references to valid blocks.
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2009-10-27 17:24:40 +01:00
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.icache.demand_accesses 1490 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 36423.575130 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 34778.614458 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_hits 1104 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_miss_latency 14059500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.259060 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_misses 386 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 54 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 11546500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.222819 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 332 # number of demand (read+write) MSHR misses
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.icache.occ_%::0 0.078771 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.occ_blocks::0 161.323458 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.overall_accesses 1490 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 36423.575130 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 34778.614458 # average overall mshr miss latency
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.icache.overall_hits 1104 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_miss_latency 14059500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.259060 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_misses 386 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 54 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 11546500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.222819 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 332 # number of overall MSHR misses
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.icache.replacements 0 # number of replacements
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.icache.sampled_refs 332 # Sample count of references to valid blocks.
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.icache.tagsinuse 161.323458 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 1104 # Total number of references to valid blocks.
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.idleCycles 12375 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.iew.EXEC:branches 1261 # Number of branches executed
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.iew.EXEC:nop 0 # number of nop insts executed
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iew.EXEC:rate 0.328319 # Inst execution rate
|
|
|
|
|
system.cpu.iew.EXEC:refs 2813 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.EXEC:stores 1315 # Number of stores executed
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iew.WB:consumers 5889 # num instructions consuming a value
|
|
|
|
|
system.cpu.iew.WB:count 7582 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.WB:fanout 0.646290 # average fanout of values written-back
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iew.WB:producers 3806 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.WB:rate 0.319511 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.WB:sent 7642 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.branchMispredicts 277 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewBlockCycles 117 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 1681 # Number of dispatched load instructions
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.iew.iewDispNonSpecInsts 14 # Number of dispatched non-speculative instructions
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iew.iewDispSquashedInsts 97 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 1450 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 9185 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 1498 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 298 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 7791 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 570 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
|
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.forwLoads 30 # Number of loads that had data forwarded from stores
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 42 # Number of memory ordering violations
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 719 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedStores 404 # Number of stores squashed
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 42 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 201 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 76 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.ipc 0.244416 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 0.244416 # IPC: Total IPC of All Threads
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IntAlu 5126 63.37% 63.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 63.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 63.37% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 63.39% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 63.39% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 63.39% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 63.39% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 63.39% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 63.39% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::MemRead 1593 19.69% 83.09% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::MemWrite 1368 16.91% 100.00% # Type of FU issued
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::total 8089 # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 153 # FU busy when requested
|
|
|
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.018915 # FU busy rate (busy events/executed inst)
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_full::IntAlu 11 7.19% 7.19% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 7.19% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 7.19% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 7.19% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 7.19% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 7.19% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 7.19% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 7.19% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 7.19% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::MemRead 73 47.71% 54.90% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::MemWrite 69 45.10% 100.00% # attempts to use FU when none available
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::samples 11355 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.712373 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.391316 # Number of insts issued each cycle
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
2010-06-07 00:39:10 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::0 8066 71.03% 71.03% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::1 1182 10.41% 81.44% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::2 820 7.22% 88.67% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::3 507 4.46% 93.13% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::4 388 3.42% 96.55% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::5 218 1.92% 98.47% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::6 121 1.07% 99.53% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::7 46 0.41% 99.94% # Number of insts issued each cycle
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::8 7 0.06% 100.00% # Number of insts issued each cycle
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::total 11355 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:rate 0.340877 # Inst issue rate
|
|
|
|
|
system.cpu.iq.iqInstsAdded 9163 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqInstsIssued 8089 # Number of instructions issued
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iq.iqSquashedInstsExamined 2985 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 14 # Number of squashed instructions issued
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 2761 # Number of squashed operands that are examined and possibly removed from graph
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
|
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
|
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
|
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses 48 # number of ReadExReq accesses(hits+misses)
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34927.083333 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31750 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 1676500 # number of ReadExReq miss cycles
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 48 # number of ReadExReq misses
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1524000 # number of ReadExReq MSHR miss cycles
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 48 # number of ReadExReq MSHR misses
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.ReadReq_accesses 388 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34327.631579 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31150 # average ReadReq mshr miss latency
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.l2cache.ReadReq_hits 8 # number of ReadReq hits
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 13044500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.979381 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 380 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 11837000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.979381 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 380 # number of ReadReq MSHR misses
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.l2cache.UpgradeReq_accesses 17 # number of UpgradeReq accesses(hits+misses)
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34264.705882 # average UpgradeReq miss latency
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31176.470588 # average UpgradeReq mshr miss latency
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_miss_latency 582500 # number of UpgradeReq miss cycles
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses 17 # number of UpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 530000 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 17 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.avg_refs 0.022039 # Average number of references to valid blocks.
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.demand_accesses 436 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34394.859813 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31217.289720 # average overall mshr miss latency
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.l2cache.demand_hits 8 # number of demand (read+write) hits
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.demand_miss_latency 14721000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.981651 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_misses 428 # number of demand (read+write) misses
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 13361000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.981651 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 428 # number of demand (read+write) MSHR misses
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.occ_%::0 0.005582 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_blocks::0 182.925254 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.overall_accesses 436 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34394.859813 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31217.289720 # average overall mshr miss latency
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.overall_hits 8 # number of overall hits
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.overall_miss_latency 14721000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.981651 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_misses 428 # number of overall misses
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 13361000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.981651 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 428 # number of overall MSHR misses
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.sampled_refs 363 # Sample count of references to valid blocks.
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 182.925254 # Cycle average of tags in use
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.l2cache.total_refs 8 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
|
|
|
|
system.cpu.memDep0.conflictingLoads 67 # Number of conflicting loads.
|
|
|
|
|
system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores.
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.memDep0.insertedLoads 1681 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.insertedStores 1450 # Number of stores inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.numCycles 23730 # number of cpu cycles simulated
|
|
|
|
|
system.cpu.rename.RENAME:BlockCycles 323 # Number of cycles rename is blocking
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.rename.RENAME:CommittedMaps 5007 # Number of HB maps that are committed
|
|
|
|
|
system.cpu.rename.RENAME:IQFullEvents 7 # Number of times rename has blocked due to IQ full
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.rename.RENAME:IdleCycles 7801 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.RENAME:LSQFullEvents 213 # Number of times rename has blocked due to LSQ full
|
|
|
|
|
system.cpu.rename.RENAME:RenameLookups 16232 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.RENAME:RenamedInsts 9925 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.RENAME:RenamedOperands 8708 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RENAME:RunCycles 1823 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.RENAME:SquashCycles 570 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.RENAME:UnblockCycles 263 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.RENAME:UndoneMaps 3701 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.RENAME:serializeStallCycles 575 # count of cycles rename stalled for serializing inst
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.rename.RENAME:serializingInsts 22 # count of serializing insts renamed
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.rename.RENAME:skidInsts 494 # count of insts added to the skid buffer
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.rename.RENAME:tempSerializingInsts 22 # count of temporary serializing insts renamed
|
|
|
|
|
system.cpu.timesIdled 231 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.workload.PROG:num_syscalls 9 # Number of system calls
|
|
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
