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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt

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tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
---------- Begin Simulation Statistics ----------
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
sim_seconds 2.541289 # Number of seconds simulated
sim_ticks 2541288973500 # Number of ticks simulated
final_tick 2541288973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
host_inst_rate 61532 # Simulator instruction rate (inst/s)
host_op_rate 79175 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2592785663 # Simulator tick rate (ticks/s)
host_mem_usage 411940 # Number of bytes of host memory used
host_seconds 980.14 # Real time elapsed on the host
sim_insts 60309889 # Number of instructions simulated
sim_ops 77602313 # Number of ops (including micro ops) simulated
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.bytes_read::cpu0.dtb.walker 1600 # Number of bytes read from this memory
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.bytes_read::cpu0.inst 501184 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 4156432 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 768 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 298496 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 4937244 # Number of bytes read from this memory
system.physmem.bytes_read::total 131006380 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 501184 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 298496 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 799680 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3784960 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 1345340 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 1670772 # Number of bytes written to this memory
system.physmem.bytes_written::total 6801072 # Number of bytes written to this memory
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.num_reads::cpu0.dtb.walker 25 # Number of read requests responded to by this memory
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.num_reads::cpu0.inst 7831 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 64978 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 12 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 4664 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 77151 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15293479 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 59140 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 336335 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 417693 # Number of write requests responded to by this memory
system.physmem.num_writes::total 813168 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 47657126 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 630 # Total read bandwidth from this memory (bytes/s)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s)
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.bw_read::cpu0.inst 197216 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 1635561 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 302 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 117459 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 1942811 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 51551154 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 197216 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 117459 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 314675 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1489386 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 529393 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 657451 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2676229 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1489386 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 47657126 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 630 # Total bandwidth to/from this memory (bytes/s)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.bw_total::cpu0.inst 197216 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 2164953 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 302 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 117459 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 2600262 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 54227384 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 15293479 # Total number of read requests seen
system.physmem.writeReqs 813168 # Total number of write requests seen
system.physmem.cpureqs 218447 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 978782656 # Total number of bytes read from memory
system.physmem.bytesWritten 52042752 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 131006380 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 6801072 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 10 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 4687 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 956234 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 955730 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 955668 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 956486 # Track reads on a per bank basis
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.physmem.perBankRdReqs::4 956267 # Track reads on a per bank basis
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.perBankRdReqs::5 955440 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 955563 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 956167 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 956088 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 955610 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 955526 # Track reads on a per bank basis
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.physmem.perBankRdReqs::11 955926 # Track reads on a per bank basis
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.perBankRdReqs::12 956037 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 955427 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 955317 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 955983 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 50835 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 50411 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 50432 # Track writes on a per bank basis
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.physmem.perBankWrReqs::3 51159 # Track writes on a per bank basis
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.perBankWrReqs::4 50913 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 50185 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 50283 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 50857 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 51358 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 50902 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 50806 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 51187 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 51249 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 50729 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 50629 # Track writes on a per bank basis
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.physmem.perBankWrReqs::15 51233 # Track writes on a per bank basis
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.numWrRetry 1856346 # Number of times wr buffer was full causing retry
system.physmem.totGap 2541287786000 # Total gap between requests
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.readPktSize::2 43 # Categorize read packet sizes
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.readPktSize::3 15138816 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.readPktSize::6 154620 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 754028 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 59140 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 1054883 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 992061 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 961934 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 3604876 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2718031 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2722784 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 2698984 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 60219 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 59460 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 109990 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 160408 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 109908 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 10058 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 9982 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 11017 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 8826 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 27 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 14 # What read queue length does an incoming req see
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.wrQLenPdf::0 2744 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 2844 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 2877 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 2926 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 2926 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 2922 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 2925 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 2922 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 2918 # What write queue length does an incoming req see
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.physmem.wrQLenPdf::9 35382 # What write queue length does an incoming req see
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.wrQLenPdf::10 35370 # What write queue length does an incoming req see
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.physmem.wrQLenPdf::11 35358 # What write queue length does an incoming req see
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.wrQLenPdf::12 35348 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 35328 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 35317 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 35298 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 35287 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 35277 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 35255 # What write queue length does an incoming req see
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.physmem.wrQLenPdf::19 35243 # What write queue length does an incoming req see
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.wrQLenPdf::20 35235 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 35232 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 35218 # What write queue length does an incoming req see
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.physmem.wrQLenPdf::23 32761 # What write queue length does an incoming req see
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.wrQLenPdf::24 32641 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 32596 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 32531 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 32518 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 32510 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 32497 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 32486 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 32476 # What write queue length does an incoming req see
system.physmem.totQLat 346721486500 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 439895947750 # Sum of mem lat for all requests
system.physmem.totBusLat 76467345000 # Total cycles spent in databus access
system.physmem.totBankLat 16707116250 # Total cycles spent in bank access
system.physmem.avgQLat 22671.21 # Average queueing delay per request
system.physmem.avgBankLat 1092.43 # Average bank access latency per request
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per request
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.avgMemAccLat 28763.65 # Average memory access latency
system.physmem.avgRdBW 385.15 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 20.48 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 51.55 # Average consumed read bandwidth in MB/s
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 3.17 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.17 # Average read queue length over time
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.avgWrQLen 1.13 # Average write queue length over time
system.physmem.readRowHits 15218362 # Number of row buffer hits during reads
system.physmem.writeRowHits 794635 # Number of row buffer hits during writes
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.readRowHitRate 99.51 # Row buffer hit rate for reads
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.writeRowHitRate 97.72 # Row buffer hit rate for writes
system.physmem.avgGap 157778.82 # Average gap between requests
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.replacements 64388 # number of replacements
system.l2c.tagsinuse 51386.157207 # Cycle average of tags in use
system.l2c.total_refs 1906213 # Total number of references to valid blocks.
system.l2c.sampled_refs 129781 # Sample count of references to valid blocks.
system.l2c.avg_refs 14.687920 # Average number of references to valid blocks.
system.l2c.warmup_cycle 2505304860500 # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks 36943.345859 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.dtb.walker 11.980136 # Average occupied blocks per requestor
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.occ_blocks::cpu0.itb.walker 0.000349 # Average occupied blocks per requestor
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.occ_blocks::cpu0.inst 5122.722111 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data 3272.415541 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.dtb.walker 10.482410 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst 3080.689127 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data 2944.521672 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.563711 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.dtb.walker 0.000183 # Average percentage of cache occupancy
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.occ_percent::cpu0.inst 0.078167 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data 0.049933 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.dtb.walker 0.000160 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst 0.047008 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data 0.044930 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.784091 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker 32856 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 7561 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 491369 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 213716 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 30962 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 7078 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 479886 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 173939 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1437367 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 608382 # number of Writeback hits
system.l2c.Writeback_hits::total 608382 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 20 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 18 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 38 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 5 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 4 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 57851 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 55061 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 112912 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 32856 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 7561 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 491369 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 271567 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 30962 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 7078 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 479886 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 229000 # number of demand (read+write) hits
system.l2c.demand_hits::total 1550279 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 32856 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 7561 # number of overall hits
system.l2c.overall_hits::cpu0.inst 491369 # number of overall hits
system.l2c.overall_hits::cpu0.data 271567 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 30962 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 7078 # number of overall hits
system.l2c.overall_hits::cpu1.inst 479886 # number of overall hits
system.l2c.overall_hits::cpu1.data 229000 # number of overall hits
system.l2c.overall_hits::total 1550279 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 25 # number of ReadReq misses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.ReadReq_misses::cpu0.inst 7722 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 6085 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 12 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 4670 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 4619 # number of ReadReq misses
system.l2c.ReadReq_misses::total 23135 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 1541 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 1365 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 2906 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 59871 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 73351 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 133222 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker 25 # number of demand (read+write) misses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.demand_misses::cpu0.inst 7722 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 65956 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 12 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 4670 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 77970 # number of demand (read+write) misses
system.l2c.demand_misses::total 156357 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 25 # number of overall misses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.overall_misses::cpu0.inst 7722 # number of overall misses
system.l2c.overall_misses::cpu0.data 65956 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 12 # number of overall misses
system.l2c.overall_misses::cpu1.inst 4670 # number of overall misses
system.l2c.overall_misses::cpu1.data 77970 # number of overall misses
system.l2c.overall_misses::total 156357 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1696500 # number of ReadReq miss cycles
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 118000 # number of ReadReq miss cycles
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.ReadReq_miss_latency::cpu0.inst 425410000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 344277000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 826500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 270381000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 269029500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 1311738500 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 205000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 205500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 410500 # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 3130049500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 3648768000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 6778817500 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 1696500 # number of demand (read+write) miss cycles
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.demand_miss_latency::cpu0.itb.walker 118000 # number of demand (read+write) miss cycles
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.demand_miss_latency::cpu0.inst 425410000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 3474326500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 826500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 270381000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 3917797500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 8090556000 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 1696500 # number of overall miss cycles
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.overall_miss_latency::cpu0.itb.walker 118000 # number of overall miss cycles
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.overall_miss_latency::cpu0.inst 425410000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 3474326500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 826500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 270381000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 3917797500 # number of overall miss cycles
system.l2c.overall_miss_latency::total 8090556000 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 32881 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 7563 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 499091 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 219801 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 30974 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 7078 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 484556 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 178558 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 1460502 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 608382 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 608382 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 1561 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 1383 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 2944 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 5 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 4 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 9 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 117722 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 128412 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 246134 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 32881 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 7563 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 499091 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 337523 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 30974 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 7078 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 484556 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 306970 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 1706636 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 32881 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 7563 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 499091 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 337523 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 30974 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 7078 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 484556 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 306970 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 1706636 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000760 # miss rate for ReadReq accesses
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000264 # miss rate for ReadReq accesses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.ReadReq_miss_rate::cpu0.inst 0.015472 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.027684 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000387 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.009638 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.025868 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.015840 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.987188 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.986985 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.987092 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.508580 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.571216 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.541258 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000760 # miss rate for demand accesses
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.l2c.demand_miss_rate::cpu0.itb.walker 0.000264 # miss rate for demand accesses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.demand_miss_rate::cpu0.inst 0.015472 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.195412 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000387 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.009638 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.253999 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.091617 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000760 # miss rate for overall accesses
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.l2c.overall_miss_rate::cpu0.itb.walker 0.000264 # miss rate for overall accesses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.overall_miss_rate::cpu0.inst 0.015472 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.195412 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000387 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.009638 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.253999 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.091617 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 67860 # average ReadReq miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 59000 # average ReadReq miss latency
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 55090.650091 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 56577.978636 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 68875 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 57897.430407 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 58244.100455 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 56699.308407 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 133.030500 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 150.549451 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 141.259463 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52279.893438 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 49743.943505 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 50883.619072 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 67860 # average overall miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 59000 # average overall miss latency
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.demand_avg_miss_latency::cpu0.inst 55090.650091 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 52676.428225 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 68875 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 57897.430407 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 50247.499038 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 51744.124024 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 67860 # average overall miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 59000 # average overall miss latency
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.overall_avg_miss_latency::cpu0.inst 55090.650091 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 52676.428225 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 68875 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 57897.430407 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 50247.499038 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 51744.124024 # average overall miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.writebacks::writebacks 59140 # number of writebacks
system.l2c.writebacks::total 59140 # number of writebacks
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.l2c.ReadReq_mshr_hits::cpu0.inst 10 # number of ReadReq MSHR hits
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.ReadReq_mshr_hits::cpu0.data 39 # number of ReadReq MSHR hits
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.l2c.ReadReq_mshr_hits::cpu1.inst 6 # number of ReadReq MSHR hits
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.ReadReq_mshr_hits::cpu1.data 20 # number of ReadReq MSHR hits
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.l2c.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst 10 # number of demand (read+write) MSHR hits
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.demand_mshr_hits::cpu0.data 39 # number of demand (read+write) MSHR hits
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.l2c.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.demand_mshr_hits::cpu1.data 20 # number of demand (read+write) MSHR hits
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.l2c.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst 10 # number of overall MSHR hits
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.overall_mshr_hits::cpu0.data 39 # number of overall MSHR hits
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.l2c.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.overall_mshr_hits::cpu1.data 20 # number of overall MSHR hits
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.l2c.overall_mshr_hits::total 75 # number of overall MSHR hits
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 25 # number of ReadReq MSHR misses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.ReadReq_mshr_misses::cpu0.inst 7712 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data 6046 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 12 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst 4664 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 4599 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 23060 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 1541 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 1365 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 2906 # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 59871 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 73351 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 133222 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker 25 # number of demand (read+write) MSHR misses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.demand_mshr_misses::cpu0.inst 7712 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 65917 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 12 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 4664 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 77950 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 156282 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker 25 # number of overall MSHR misses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.overall_mshr_misses::cpu0.inst 7712 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 65917 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 12 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 4664 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 77950 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 156282 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 1386024 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 93251 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 329024705 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 267448944 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 675012 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 211941612 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 210372572 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 1020942120 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 15411541 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 13749804 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 29161345 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2383249825 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2735103931 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 5118353756 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1386024 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 93251 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 329024705 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 2650698769 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 675012 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 211941612 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 2945476503 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 6139295876 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1386024 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 93251 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 329024705 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 2650698769 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 675012 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 211941612 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 2945476503 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 6139295876 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5050830 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 84200622267 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82767168504 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 166972841601 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 10453604329 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 13166783666 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 23620387995 # number of WriteReq MSHR uncacheable cycles
system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 76253 # number of LoadLockedReq MSHR uncacheable cycles
system.l2c.LoadLockedReq_mshr_uncacheable_latency::total 76253 # number of LoadLockedReq MSHR uncacheable cycles
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data 30003 # number of StoreCondReq MSHR uncacheable cycles
system.l2c.StoreCondReq_mshr_uncacheable_latency::total 30003 # number of StoreCondReq MSHR uncacheable cycles
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5050830 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 94654226596 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 95933952170 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 190593229596 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000760 # mshr miss rate for ReadReq accesses
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000264 # mshr miss rate for ReadReq accesses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015452 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.027507 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000387 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009625 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.025756 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.015789 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.987188 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.986985 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.987092 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.508580 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.571216 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.541258 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000760 # mshr miss rate for demand accesses
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000264 # mshr miss rate for demand accesses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015452 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.195296 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000387 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009625 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.253934 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.091573 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000760 # mshr miss rate for overall accesses
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000264 # mshr miss rate for overall accesses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015452 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.195296 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000387 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009625 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.253934 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.091573 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 55440.960000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42663.991831 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44235.683758 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 45442.026587 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45743.111981 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 44273.292281 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10073.116484 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10034.874398 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 39806.414207 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 37287.888795 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 38419.733648 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 55440.960000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42663.991831 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40212.673043 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 45442.026587 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37786.741539 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 39283.448356 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 55440.960000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42663.991831 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40212.673043 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 45442.026587 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37786.741539 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 39283.448356 # average overall mshr miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency
system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency
system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency
system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.branchPred.lookups 7614306 # Number of BP lookups
system.cpu0.branchPred.condPredicted 6072650 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 380012 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 4955572 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 4051897 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.branchPred.BTBHitPct 81.764466 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 730604 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 39458 # Number of incorrect RAS predictions.
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.dtb.read_hits 26054511 # DTB read hits
system.cpu0.dtb.read_misses 40169 # DTB read misses
system.cpu0.dtb.write_hits 5887052 # DTB write hits
system.cpu0.dtb.write_misses 9355 # DTB write misses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu0.dtb.flush_tlb_mva_asid 771 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.dtb.flush_entries 5627 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 1395 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 274 # Number of TLB faults due to prefetch
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.dtb.perms_faults 638 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 26094680 # DTB read accesses
system.cpu0.dtb.write_accesses 5896407 # DTB write accesses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.dtb.hits 31941563 # DTB hits
system.cpu0.dtb.misses 49524 # DTB misses
system.cpu0.dtb.accesses 31991087 # DTB accesses
system.cpu0.itb.inst_hits 6108612 # ITB inst hits
system.cpu0.itb.inst_misses 7590 # ITB inst misses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.itb.flush_tlb 257 # Number of times complete TLB was flushed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu0.itb.flush_tlb_mva_asid 771 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.itb.flush_entries 2632 # Number of entries that have been flushed from TLB
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.itb.perms_faults 1574 # Number of TLB faults due to permissions restrictions
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.itb.inst_accesses 6116202 # ITB inst accesses
system.cpu0.itb.hits 6108612 # DTB hits
system.cpu0.itb.misses 7590 # DTB misses
system.cpu0.itb.accesses 6116202 # DTB accesses
system.cpu0.numCycles 239083473 # number of cpu cycles simulated
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.fetch.icacheStallCycles 15485568 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 47808985 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 7614306 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 4782501 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 10601732 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 2558486 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 88790 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.BlockedCycles 49524477 # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles 1650 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingDrainCycles 2036 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu0.fetch.PendingTrapStallCycles 49879 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 101149 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 238 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 6106475 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 397023 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 3536 # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples 77625046 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 0.761902 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 2.119269 # Number of instructions fetched each cycle (Total)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.fetch.rateDist::0 67030834 86.35% 86.35% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 688188 0.89% 87.24% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 885369 1.14% 88.38% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 1227712 1.58% 89.96% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4 1142460 1.47% 91.43% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5 576598 0.74% 92.18% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6 1323002 1.70% 93.88% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7 397300 0.51% 94.39% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8 4353583 5.61% 100.00% # Number of instructions fetched each cycle (Total)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.fetch.rateDist::total 77625046 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.031848 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.199968 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 16533020 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 49254882 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 9604301 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 549145 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 1681530 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 1023916 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 90477 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 56278023 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 301850 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 1681530 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 17466172 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 18987810 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 27019642 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 9149380 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 3318436 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 53462165 # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents 13485 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 622165 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents 2153440 # Number of times rename has blocked due to LSQ full
system.cpu0.rename.FullRegisterEvents 547 # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands 55626962 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 243359254 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 243311426 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 47828 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 40393377 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 15233585 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 429285 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 381212 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 6745205 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 10341737 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 6773194 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 1063883 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 1311451 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 49606690 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 1043899 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 63171257 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 95885 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 10502922 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 26495317 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 267486 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 77625046 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.813800 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.519198 # Number of insts issued each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.iq.issued_per_cycle::0 54791410 70.58% 70.58% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 7205110 9.28% 79.87% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 3690427 4.75% 84.62% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 3148985 4.06% 88.68% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 6276259 8.09% 96.76% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 1405987 1.81% 98.57% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 810578 1.04% 99.62% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 230421 0.30% 99.92% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 65869 0.08% 100.00% # Number of insts issued each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.iq.issued_per_cycle::total 77625046 # Number of insts issued each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.iq.fu_full::IntAlu 29841 0.67% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 2 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.67% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 4229016 94.75% 95.42% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 204408 4.58% 100.00% # attempts to use FU when none available
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.iq.FU_type_0::No_OpClass 195533 0.31% 0.31% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 29939610 47.39% 47.70% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 46892 0.07% 47.78% # Type of FU issued
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.78% # Type of FU issued
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 47.78% # Type of FU issued
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 47.78% # Type of FU issued
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.78% # Type of FU issued
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.78% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.78% # Type of FU issued
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.iq.FU_type_0::SimdFloatMisc 1207 0.00% 47.78% # Type of FU issued
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.78% # Type of FU issued
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.78% # Type of FU issued
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.78% # Type of FU issued
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.iq.FU_type_0::MemRead 26772486 42.38% 90.16% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 6215505 9.84% 100.00% # Type of FU issued
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.iq.FU_type_0::total 63171257 # Type of FU issued
system.cpu0.iq.rate 0.264223 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 4463267 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.070653 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 208563844 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 61162491 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 44139446 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 12207 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 6555 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 5480 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 67432539 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 6452 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 322060 # Number of loads that had data forwarded from stores
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.iew.lsq.thread0.squashedLoads 2267012 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 3473 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 16117 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 886206 # Number of stores squashed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.iew.lsq.thread0.rescheduledLoads 17168110 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 367587 # Number of times an access to memory failed due to the cache being blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.iew.iewSquashCycles 1681530 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 14225625 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 233605 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 50767973 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 106118 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 10341737 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 6773194 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 742853 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 56514 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 3354 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 16117 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 186814 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 146956 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 333770 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 62000418 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 26414197 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 1170839 # Number of squashed instructions skipped in execute
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iew.exec_swp 0 # number of swp insts executed
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.iew.exec_nop 117384 # number of nop insts executed
system.cpu0.iew.exec_refs 32572588 # number of memory reference insts executed
system.cpu0.iew.exec_branches 6026978 # Number of branches executed
system.cpu0.iew.exec_stores 6158391 # Number of stores executed
system.cpu0.iew.exec_rate 0.259325 # Inst execution rate
system.cpu0.iew.wb_sent 61472286 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 44144926 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 24307807 # num instructions producing a value
system.cpu0.iew.wb_consumers 44674584 # num instructions consuming a value
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.iew.wb_rate 0.184642 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.544108 # average fanout of values written-back
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.commit.commitSquashedInsts 10350620 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 776413 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 290797 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 75943516 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.525572 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.508217 # Number of insts commited each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.commit.committed_per_cycle::0 61731521 81.29% 81.29% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 6903711 9.09% 90.38% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 2039504 2.69% 93.06% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 1132941 1.49% 94.55% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 1032773 1.36% 95.91% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 549051 0.72% 96.64% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 702703 0.93% 97.56% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 370837 0.49% 98.05% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 1480475 1.95% 100.00% # Number of insts commited each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.commit.committed_per_cycle::total 75943516 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 31268406 # Number of instructions committed
system.cpu0.commit.committedOps 39913766 # Number of ops (including micro ops) committed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.commit.refs 13961713 # Number of memory references committed
system.cpu0.commit.loads 8074725 # Number of loads committed
system.cpu0.commit.membars 212370 # Number of memory barriers committed
system.cpu0.commit.branches 5203416 # Number of branches committed
system.cpu0.commit.fp_insts 5433 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 35263906 # Number of committed integer instructions.
system.cpu0.commit.function_calls 513958 # Number of function calls committed.
system.cpu0.commit.bw_lim_events 1480475 # number cycles where commit BW limit reached
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.rob.rob_reads 123750130 # The number of ROB reads
system.cpu0.rob.rob_writes 102252787 # The number of ROB writes
system.cpu0.timesIdled 884124 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 161458427 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 2289647904 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 31189179 # Number of Instructions Simulated
system.cpu0.committedOps 39834539 # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total 31189179 # Number of Instructions Simulated
system.cpu0.cpi 7.665590 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 7.665590 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.130453 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.130453 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 280633966 # number of integer regfile reads
system.cpu0.int_regfile_writes 45420954 # number of integer regfile writes
system.cpu0.fp_regfile_reads 22760 # number of floating regfile reads
system.cpu0.fp_regfile_writes 19830 # number of floating regfile writes
system.cpu0.misc_regfile_reads 15480243 # number of misc regfile reads
system.cpu0.misc_regfile_writes 429707 # number of misc regfile writes
system.cpu0.icache.replacements 984233 # number of replacements
system.cpu0.icache.tagsinuse 511.604349 # Cycle average of tags in use
system.cpu0.icache.total_refs 11036411 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 984745 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 11.207380 # Average number of references to valid blocks.
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu0.icache.warmup_cycle 6522889000 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.icache.occ_blocks::cpu0.inst 356.507188 # Average occupied blocks per requestor
system.cpu0.icache.occ_blocks::cpu1.inst 155.097161 # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst 0.696303 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::cpu1.inst 0.302924 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total 0.999227 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 5565457 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 5470954 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 11036411 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 5565457 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 5470954 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 11036411 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 5565457 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 5470954 # number of overall hits
system.cpu0.icache.overall_hits::total 11036411 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 540893 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 524443 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 1065336 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 540893 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 524443 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 1065336 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 540893 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 524443 # number of overall misses
system.cpu0.icache.overall_misses::total 1065336 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7322738992 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6974356493 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 14297095485 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 7322738992 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 6974356493 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 14297095485 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 7322738992 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 6974356493 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 14297095485 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 6106350 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 5995397 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 12101747 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 6106350 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 5995397 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 12101747 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 6106350 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 5995397 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 12101747 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.088579 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.087474 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.088032 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.088579 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.087474 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.088032 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.088579 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.087474 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.088032 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13538.239526 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13298.597737 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13420.268803 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13538.239526 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13298.597737 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13420.268803 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13538.239526 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13298.597737 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13420.268803 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 4718 # number of cycles access was blocked
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.icache.blocked::no_mshrs 353 # number of cycles access was blocked
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.365439 # average number of cycles each access was blocked
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 41212 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 39352 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 80564 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 41212 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu1.inst 39352 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 80564 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 41212 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu1.inst 39352 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 80564 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 499681 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 485091 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 984772 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 499681 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 485091 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 984772 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 499681 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 485091 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 984772 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5972321992 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5682978994 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 11655300986 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5972321992 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5682978994 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 11655300986 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5972321992 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5682978994 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 11655300986 # number of overall MSHR miss cycles
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7526000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7526000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7526000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 7526000 # number of overall MSHR uncacheable cycles
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.081830 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.080911 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.081374 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.081830 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.080911 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.081374 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.081830 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.080911 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.081374 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11952.269532 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11715.284336 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11835.532475 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11952.269532 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11715.284336 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11835.532475 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11952.269532 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11715.284336 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11835.532475 # average overall mshr miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.dcache.replacements 643981 # number of replacements
system.cpu0.dcache.tagsinuse 511.992715 # Cycle average of tags in use
system.cpu0.dcache.total_refs 21533340 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 644493 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 33.411286 # Average number of references to valid blocks.
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu0.dcache.warmup_cycle 43205000 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.dcache.occ_blocks::cpu0.data 320.784691 # Average occupied blocks per requestor
system.cpu0.dcache.occ_blocks::cpu1.data 191.208024 # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data 0.626533 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::cpu1.data 0.373453 # Average percentage of cache occupancy
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.dcache.ReadReq_hits::cpu0.data 7106515 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 6670987 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 13777502 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 3768669 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 3492995 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 7261664 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 125802 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 117658 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 243460 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 127804 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 119816 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 247620 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 10875184 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 10163982 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 21039166 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 10875184 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 10163982 # number of overall hits
system.cpu0.dcache.overall_hits::total 21039166 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 435450 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 315528 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 750978 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 1386539 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 1574618 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 2961157 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6834 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6765 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 13599 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data 4 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 9 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 1821989 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 1890146 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 3712135 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 1821989 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 1890146 # number of overall misses
system.cpu0.dcache.overall_misses::total 3712135 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6465601500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 4868577500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 11334179000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 52482898858 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 61975315789 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 114458214647 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 92223500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 94082500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 186306000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 65000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 52000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 117000 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 58948500358 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 66843893289 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 125792393647 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 58948500358 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 66843893289 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 125792393647 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 7541965 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 6986515 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 14528480 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5155208 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 5067613 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 10222821 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 132636 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 124423 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 257059 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 127809 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 119820 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 247629 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 12697173 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 12054128 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 24751301 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 12697173 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 12054128 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 24751301 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.057737 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.045162 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.051690 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.268959 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.310722 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.289661 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.051524 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054371 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052902 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000039 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000033 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000036 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.143496 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.156805 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.149977 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.143496 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.156805 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.149977 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14848.091629 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15429.938072 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15092.557971 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 37851.729276 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39358.952958 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 38653.207056 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13494.805385 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13907.243163 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13699.977940 # average LoadLockedReq miss latency
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 13000 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13000 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32353.927690 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35364.407453 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 33886.804668 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32353.927690 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35364.407453 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 33886.804668 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 35336 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 15995 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 3561 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 266 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.923055 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 60.131579 # average number of cycles each access was blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.dcache.writebacks::writebacks 608382 # number of writebacks
system.cpu0.dcache.writebacks::total 608382 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 221746 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 143011 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 364757 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1267305 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1444859 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 2712164 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 688 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 688 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1376 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1489051 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data 1587870 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 3076921 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1489051 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data 1587870 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 3076921 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 213704 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 172517 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 386221 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 119234 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 129759 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 248993 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6146 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 6077 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12223 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 4 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 9 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 332938 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 302276 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 635214 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 332938 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 302276 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 635214 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2899504500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2321074000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5220578500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3969032491 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4493255436 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8462287927 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 71687000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 73644500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 145331500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 55000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 44000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 99000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6868536991 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6814329436 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 13682866427 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6868536991 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6814329436 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 13682866427 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91958825500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90402409000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182361234500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 14888911816 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 18625662995 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 33514574811 # number of WriteReq MSHR uncacheable cycles
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 118000 # number of LoadLockedReq MSHR uncacheable cycles
system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 118000 # number of LoadLockedReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106847737316 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 109028071995 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215875809311 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028335 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024693 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026584 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023129 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025606 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024357 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046337 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048841 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047549 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000039 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000033 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000036 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026221 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025077 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.025664 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026221 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025077 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.025664 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13567.853199 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13454.175531 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13517.075716 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33287.757611 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34627.697778 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33986.047507 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11664.009112 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12118.561790 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11890.002454 # average LoadLockedReq mshr miss latency
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20630.078246 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22543.402175 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21540.561806 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20630.078246 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22543.402175 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21540.561806 # average overall mshr miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency
system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency
system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.branchPred.lookups 7038093 # Number of BP lookups
system.cpu1.branchPred.condPredicted 5643597 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 344397 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 4629014 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 3810883 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.branchPred.BTBHitPct 82.326020 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 671158 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 34749 # Number of incorrect RAS predictions.
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.dtb.read_hits 25308103 # DTB read hits
system.cpu1.dtb.read_misses 36468 # DTB read misses
system.cpu1.dtb.write_hits 5825949 # DTB write hits
system.cpu1.dtb.write_misses 9352 # DTB write misses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.flush_tlb 254 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu1.dtb.flush_tlb_mva_asid 668 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.dtb.flush_entries 5514 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 1257 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 236 # Number of TLB faults due to prefetch
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.dtb.perms_faults 652 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 25344571 # DTB read accesses
system.cpu1.dtb.write_accesses 5835301 # DTB write accesses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.dtb.hits 31134052 # DTB hits
system.cpu1.dtb.misses 45820 # DTB misses
system.cpu1.dtb.accesses 31179872 # DTB accesses
system.cpu1.itb.inst_hits 5997509 # ITB inst hits
system.cpu1.itb.inst_misses 6989 # ITB inst misses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 254 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu1.itb.flush_tlb_mva_asid 668 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.itb.flush_entries 2597 # Number of entries that have been flushed from TLB
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.itb.perms_faults 1435 # Number of TLB faults due to permissions restrictions
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.itb.inst_accesses 6004498 # ITB inst accesses
system.cpu1.itb.hits 5997509 # DTB hits
system.cpu1.itb.misses 6989 # DTB misses
system.cpu1.itb.accesses 6004498 # DTB accesses
system.cpu1.numCycles 234155519 # number of cpu cycles simulated
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.fetch.icacheStallCycles 15142136 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 46597306 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 7038093 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 4482041 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 10279188 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 2613913 # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles 81086 # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.BlockedCycles 47501023 # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles 1008 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingDrainCycles 2061 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu1.fetch.PendingTrapStallCycles 42896 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 94668 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 141 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 5995399 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 442650 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes 3270 # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples 74933804 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 0.773237 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 2.138568 # Number of instructions fetched each cycle (Total)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.fetch.rateDist::0 64662280 86.29% 86.29% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 620375 0.83% 87.12% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 831799 1.11% 88.23% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 1204715 1.61% 89.84% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4 1045196 1.39% 91.23% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5 534648 0.71% 91.95% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6 1368616 1.83% 93.77% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7 351624 0.47% 94.24% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8 4314551 5.76% 100.00% # Number of instructions fetched each cycle (Total)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.fetch.rateDist::total 74933804 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.030057 # Number of branch fetches per cycle
system.cpu1.fetch.rate 0.199002 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 16155094 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 47289878 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 9321974 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 458622 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 1706108 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 946431 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 86032 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 54867135 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 286067 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 1706108 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 17091509 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 18549403 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 25716073 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 8765190 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 3103459 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 51703267 # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents 7138 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 482463 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents 2122538 # Number of times rename has blocked due to LSQ full
system.cpu1.rename.FullRegisterEvents 91 # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands 53752733 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 237374868 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 237332026 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 42842 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 37999603 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 15753129 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 403463 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 357307 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 6254395 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 9847442 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 6700780 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 890369 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 1126759 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 47663057 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 942444 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 60816475 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 81421 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 10551432 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 27971257 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 236318 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 74933804 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.811603 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.521433 # Number of insts issued each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.iq.issued_per_cycle::0 53188932 70.98% 70.98% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 6663266 8.89% 79.87% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 3530113 4.71% 84.58% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 2889463 3.86% 88.44% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 6218055 8.30% 96.74% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 1440706 1.92% 98.66% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 733706 0.98% 99.64% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 209896 0.28% 99.92% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 59667 0.08% 100.00% # Number of insts issued each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.iq.issued_per_cycle::total 74933804 # Number of insts issued each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.iq.fu_full::IntAlu 24001 0.55% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 1 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 4142238 94.88% 95.43% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 199692 4.57% 100.00% # attempts to use FU when none available
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.iq.FU_type_0::No_OpClass 168133 0.28% 0.28% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 28440656 46.76% 47.04% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 46730 0.08% 47.12% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.12% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.12% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.12% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.12% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.12% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.12% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 47.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 904 0.00% 47.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.12% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.12% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 26040768 42.82% 89.94% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 6119264 10.06% 100.00% # Type of FU issued
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.iq.FU_type_0::total 60816475 # Type of FU issued
system.cpu1.iq.rate 0.259727 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 4365932 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.071789 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 201049061 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 59165079 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 41785793 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 10680 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 5951 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 4814 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 65008639 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 5635 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 303573 # Number of loads that had data forwarded from stores
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.iew.lsq.thread0.squashedLoads 2266828 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 3041 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 14605 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 855166 # Number of stores squashed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.iew.lsq.thread0.rescheduledLoads 16935844 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 457097 # Number of times an access to memory failed due to the cache being blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.iew.iewSquashCycles 1706108 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 13962333 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 229984 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 48711452 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 98533 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 9847442 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 6700780 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 669329 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 49837 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 3707 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 14605 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 166001 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 133612 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 299613 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 59448141 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 25635797 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 1368334 # Number of squashed instructions skipped in execute
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iew.exec_swp 0 # number of swp insts executed
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.iew.exec_nop 105951 # number of nop insts executed
system.cpu1.iew.exec_refs 31702689 # number of memory reference insts executed
system.cpu1.iew.exec_branches 5524822 # Number of branches executed
system.cpu1.iew.exec_stores 6066892 # Number of stores executed
system.cpu1.iew.exec_rate 0.253883 # Inst execution rate
system.cpu1.iew.wb_sent 58868959 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 41790607 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 22765083 # num instructions producing a value
system.cpu1.iew.wb_consumers 41748877 # num instructions consuming a value
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.iew.wb_rate 0.178474 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.545286 # average fanout of values written-back
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.commit.commitSquashedInsts 10475750 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 706126 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 259614 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 73227696 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.516730 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.497193 # Number of insts commited each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.commit.committed_per_cycle::0 59700930 81.53% 81.53% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 6668134 9.11% 90.63% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 1908648 2.61% 93.24% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 1011673 1.38% 94.62% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 958934 1.31% 95.93% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 524760 0.72% 96.65% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 701730 0.96% 97.61% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 374533 0.51% 98.12% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 1378354 1.88% 100.00% # Number of insts commited each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.commit.committed_per_cycle::total 73227696 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 29191864 # Number of instructions committed
system.cpu1.commit.committedOps 37838928 # Number of ops (including micro ops) committed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.commit.refs 13426228 # Number of memory references committed
system.cpu1.commit.loads 7580614 # Number of loads committed
system.cpu1.commit.membars 191280 # Number of memory barriers committed
system.cpu1.commit.branches 4758264 # Number of branches committed
system.cpu1.commit.fp_insts 4779 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 33593707 # Number of committed integer instructions.
system.cpu1.commit.function_calls 477362 # Number of function calls committed.
system.cpu1.commit.bw_lim_events 1378354 # number cycles where commit BW limit reached
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.rob.rob_reads 119292034 # The number of ROB reads
system.cpu1.rob.rob_writes 98387822 # The number of ROB writes
system.cpu1.timesIdled 873010 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 159221715 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 2285865988 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 29120710 # Number of Instructions Simulated
system.cpu1.committedOps 37767774 # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total 29120710 # Number of Instructions Simulated
system.cpu1.cpi 8.040859 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 8.040859 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.124365 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.124365 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 269346342 # number of integer regfile reads
system.cpu1.int_regfile_writes 42878504 # number of integer regfile writes
system.cpu1.fp_regfile_reads 22102 # number of floating regfile reads
system.cpu1.fp_regfile_writes 19714 # number of floating regfile writes
system.cpu1.misc_regfile_reads 14810651 # number of misc regfile reads
system.cpu1.misc_regfile_writes 402789 # number of misc regfile writes
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.avg_refs nan # Average number of references to valid blocks.
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192717579972 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1192717579972 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192717579972 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1192717579972 # number of overall MSHR uncacheable cycles
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.kern.inst.quiesce 83049 # number of quiesce instructions executed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink