2010-07-27 07:03:44 +02:00
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---------- Begin Simulation Statistics ----------
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2011-03-18 01:20:22 +01:00
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sim_seconds 0.054241 # Number of seconds simulated
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sim_ticks 54240666000 # Number of ticks simulated
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2012-01-25 18:19:50 +01:00
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final_tick 54240666000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 2777644 # Simulator instruction rate (inst/s)
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host_tick_rate 1651027932 # Simulator tick rate (ticks/s)
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host_mem_usage 342980 # Number of bytes of host memory used
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host_seconds 32.85 # Real time elapsed on the host
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sim_insts 91252969 # Number of instructions simulated
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system.physmem.bytes_read 521339715 # Number of bytes read from this memory
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system.physmem.bytes_inst_read 431323116 # Number of instructions bytes read from this memory
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system.physmem.bytes_written 18908138 # Number of bytes written to this memory
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system.physmem.num_reads 130384074 # Number of read requests responded to by this memory
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system.physmem.num_writes 4738868 # Number of write requests responded to by this memory
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system.physmem.num_other 0 # Number of other requests responded to by this memory
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system.physmem.bw_read 9611602391 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read 7952024704 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write 348597084 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total 9960199475 # Total bandwidth to/from this memory (bytes/s)
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2010-11-08 20:58:25 +01:00
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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2010-07-27 07:03:44 +02:00
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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2012-01-25 18:19:50 +01:00
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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2010-11-08 20:58:25 +01:00
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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2010-07-27 07:03:44 +02:00
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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2012-01-25 18:19:50 +01:00
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 442 # Number of system calls
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2011-03-18 01:20:22 +01:00
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system.cpu.numCycles 108481333 # number of cpu cycles simulated
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2011-02-08 04:23:13 +01:00
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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2012-01-25 18:19:50 +01:00
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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2011-03-18 01:20:22 +01:00
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system.cpu.num_insts 91252969 # Number of instructions executed
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system.cpu.num_int_alu_accesses 72525682 # Number of integer alu accesses
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2012-01-25 18:19:50 +01:00
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system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
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system.cpu.num_func_calls 96832 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 15127614 # number of instructions that are conditional controls
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2011-03-18 01:20:22 +01:00
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system.cpu.num_int_insts 72525682 # number of integer instructions
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2012-01-25 18:19:50 +01:00
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system.cpu.num_fp_insts 48 # number of float instructions
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2011-05-14 00:29:27 +02:00
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system.cpu.num_int_register_reads 396912516 # number of times the integer registers were read
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system.cpu.num_int_register_writes 106840370 # number of times the integer registers were written
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2012-01-25 18:19:50 +01:00
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system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 30 # number of times the floating registers were written
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2011-03-18 01:20:22 +01:00
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system.cpu.num_mem_refs 27318811 # number of memory refs
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2012-01-25 18:19:50 +01:00
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system.cpu.num_load_insts 22573967 # Number of load instructions
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2011-02-08 04:23:13 +01:00
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system.cpu.num_store_insts 4744844 # Number of store instructions
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2012-01-25 18:19:50 +01:00
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 108481333 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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2010-07-27 07:03:44 +02:00
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---------- End Simulation Statistics ----------
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