2011-01-18 23:30:06 +01:00
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---------- Begin Simulation Statistics ----------
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2011-08-19 22:08:06 +02:00
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sim_seconds 0.298074 # Number of seconds simulated
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sim_ticks 298073533000 # Number of ticks simulated
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2011-01-18 23:30:06 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-08-19 22:08:06 +02:00
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host_inst_rate 55166 # Simulator instruction rate (inst/s)
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host_tick_rate 28679876 # Simulator tick rate (ticks/s)
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host_mem_usage 269720 # Number of bytes of host memory used
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host_seconds 10393.12 # Real time elapsed on the host
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sim_insts 573342447 # Number of instructions simulated
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2011-01-18 23:30:06 +01:00
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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2011-05-23 17:59:13 +02:00
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 548 # Number of system calls
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2011-08-19 22:08:06 +02:00
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system.cpu.numCycles 596147067 # number of cpu cycles simulated
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2011-05-23 17:59:13 +02:00
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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2011-08-19 22:08:06 +02:00
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system.cpu.BPredUnit.lookups 233829808 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 186147170 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 18448610 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 196945817 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 163449853 # Number of BTB hits
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2011-05-23 17:59:13 +02:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2011-08-19 22:08:06 +02:00
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system.cpu.BPredUnit.usedRAS 12453913 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 2627969 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 162380426 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 1034385613 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 233829808 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 175903766 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 266887423 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 82201728 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 101000880 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 4224 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 119559 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 149451578 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 4693812 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 591651753 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.074862 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.819629 # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2011-08-19 22:08:06 +02:00
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system.cpu.fetch.rateDist::0 324776586 54.89% 54.89% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 24968353 4.22% 59.11% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 42079547 7.11% 66.23% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 41036258 6.94% 73.16% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 43058687 7.28% 80.44% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 15845137 2.68% 83.12% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 19209353 3.25% 86.36% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 16779568 2.84% 89.20% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 63898264 10.80% 100.00% # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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2011-08-19 22:08:06 +02:00
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system.cpu.fetch.rateDist::total 591651753 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.392235 # Number of branch fetches per cycle
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system.cpu.fetch.rate 1.735118 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 182259766 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 93638385 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 246087836 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 8499427 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 61166339 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 34309417 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 95729 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 1169323827 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 222317 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 61166339 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 199917017 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 12999514 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 52654373 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 236541446 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 28373064 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 1103035585 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 553 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 9425467 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 15260638 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.FullRegisterEvents 2023 # Number of times there has been no free registers
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system.cpu.rename.RenamedOperands 1222978410 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 4879529633 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 4879526297 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 3336 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 672201352 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 550777016 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 2758214 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 2758162 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 72689740 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 205506720 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 126653600 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 67829085 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 74819363 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 969401999 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 4509720 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 756022991 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 1531556 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 398123182 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 1180507714 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 631817 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 591651753 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 1.277818 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.523431 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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2011-08-19 22:08:06 +02:00
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system.cpu.iq.issued_per_cycle::0 262870171 44.43% 44.43% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 115951413 19.60% 64.03% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 93032822 15.72% 79.75% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 60874777 10.29% 90.04% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 37273328 6.30% 96.34% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 12385550 2.09% 98.43% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 5290297 0.89% 99.33% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 3168401 0.54% 99.86% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 804994 0.14% 100.00% # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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2011-08-19 22:08:06 +02:00
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system.cpu.iq.issued_per_cycle::total 591651753 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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2011-08-19 22:08:06 +02:00
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system.cpu.iq.fu_full::IntAlu 275664 3.50% 3.50% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 0 0.00% 3.50% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 3.50% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.50% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.50% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.50% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 3.50% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.50% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.50% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.50% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.50% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.50% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.50% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.50% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.50% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 3.50% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.50% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 3.50% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.50% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.50% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.50% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.50% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.50% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.50% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.50% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.50% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.50% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.50% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.50% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 5340824 67.91% 71.41% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 2248514 28.59% 100.00% # attempts to use FU when none available
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
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2011-08-19 22:08:06 +02:00
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system.cpu.iq.FU_type_0::IntAlu 517172409 68.41% 68.41% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 381200 0.05% 68.46% # Type of FU issued
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system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.46% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatAdd 134 0.00% 68.46% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.46% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.46% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.46% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.46% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.46% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.46% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.46% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.46% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.46% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.46% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.46% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.46% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.46% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.46% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.46% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.46% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.46% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.46% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.46% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.46% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.46% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 68.46% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.46% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.46% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.46% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemRead 168107388 22.24% 90.69% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 70361857 9.31% 100.00% # Type of FU issued
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.iq.FU_type_0::total 756022991 # Type of FU issued
|
|
|
|
|
system.cpu.iq.rate 1.268182 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 7865002 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.010403 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 2113093981 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 1372453088 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 706634766 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 304 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 520 # Number of floating instruction queue writes
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.iq.int_alu_accesses 763887839 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 154 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 6326745 # Number of loads that had data forwarded from stores
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 78733524 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 32052 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 425394 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 69049484 # Number of stores squashed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 27275 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 239 # Number of times an access to memory failed due to the cache being blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 61166339 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 3065417 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 178437 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 983562638 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 12157762 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 205506720 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 126653600 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 2737845 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 99480 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 4232 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 425394 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 18747710 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 6190012 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 24937722 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 730148660 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 160105072 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 25874323 # Number of squashed instructions skipped in execute
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.iew.exec_nop 9650919 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_refs 226764096 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 149136596 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 66659024 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 1.224779 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 718776639 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 706634782 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 402647843 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 726069262 # num instructions consuming a value
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.iew.wb_rate 1.185336 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.554558 # average fanout of values written-back
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.commit.commitCommittedInsts 574686331 # The number of committed instructions
|
|
|
|
|
system.cpu.commit.commitSquashedInsts 408895774 # The number of squashed insts skipped by commit
|
|
|
|
|
system.cpu.commit.commitNonSpecStalls 3877903 # The number of times commit has been forced to stall to communicate backwards
|
|
|
|
|
system.cpu.commit.branchMispredicts 20690983 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 530485415 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 1.083322 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 1.748938 # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::0 277701641 52.35% 52.35% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 135265417 25.50% 77.85% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 46444883 8.76% 86.60% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 21050080 3.97% 90.57% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 18829655 3.55% 94.12% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 7074631 1.33% 95.45% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 8453874 1.59% 97.05% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 3355983 0.63% 97.68% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 12309251 2.32% 100.00% # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::total 530485415 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.count 574686331 # Number of instructions committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.commit.refs 184377295 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads 126773187 # Number of loads committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.membars 1488542 # Number of memory barriers committed
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.commit.branches 120192372 # Number of branches committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.commit.int_insts 473702225 # Number of committed integer instructions.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.function_calls 9757362 # Number of function calls committed.
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.commit.bw_lim_events 12309251 # number cycles where commit BW limit reached
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.rob.rob_reads 1501751131 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 2028662566 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 111416 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 4495314 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.committedInsts 573342447 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 573342447 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.cpi 1.039775 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 1.039775 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 0.961747 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 0.961747 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 3357392406 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 822350092 # number of integer regfile writes
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.misc_regfile_reads 1272268831 # number of misc regfile reads
|
|
|
|
|
system.cpu.misc_regfile_writes 4464346 # number of misc regfile writes
|
|
|
|
|
system.cpu.icache.replacements 14584 # number of replacements
|
|
|
|
|
system.cpu.icache.tagsinuse 1057.611572 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 149431777 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.sampled_refs 16238 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.avg_refs 9202.597426 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.icache.occ_blocks::0 1057.611572 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.occ_percent::0 0.516412 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits 149431999 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits 149431999 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits 149431999 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses 19579 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses 19579 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses 19579 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 272035000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency 272035000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency 272035000 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 149451578 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses 149451578 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses 149451578 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.000131 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.000131 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.000131 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 13894.223403 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 13894.223403 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 13894.223403 # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.icache.writebacks 26 # number of writebacks
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits 1649 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 1649 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 1649 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 17930 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 17930 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 17930 # number of overall MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 181899000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 181899000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 181899000 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000120 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000120 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000120 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 10144.952593 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 10144.952593 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 10144.952593 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.replacements 1208610 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 4059.103651 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 205025542 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 1212706 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 169.064507 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.warmup_cycle 6026143000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.occ_blocks::0 4059.103651 # Average occupied blocks per context
|
|
|
|
|
system.cpu.dcache.occ_percent::0 0.990992 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 147450901 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits 52819924 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits 2519475 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.StoreCondReq_hits 2232172 # number of StoreCondReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits 200270825 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits 200270825 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses 1161160 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 1419382 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_misses 55 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu.dcache.demand_misses 2580542 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses 2580542 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 12492305000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency 23242142500 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency 536000 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency 35734447500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 35734447500 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 148612061 # number of ReadReq accesses(hits+misses)
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.WriteReq_accesses 54239306 # number of WriteReq accesses(hits+misses)
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_accesses 2519530 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses 2232172 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.demand_accesses 202851367 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses 202851367 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.007813 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.026169 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate 0.000022 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate 0.012721 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.012721 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 10758.469978 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 16374.832498 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency 9745.454545 # average LoadLockedReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency 13847.651966 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 13847.651966 # average overall miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 438000 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.blocked::no_targets 58 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 7551.724138 # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.writebacks 1078008 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 287250 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 1078933 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits 55 # number of LoadLockedReq MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits 1366183 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 1366183 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 873910 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 340449 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses 1214359 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 1214359 # number of overall MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 6242148500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 4342773500 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 10584922000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 10584922000 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.005880 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006277 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.005986 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.005986 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7142.781865 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12756.017788 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 8716.468524 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 8716.468524 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.replacements 218841 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 21122.736231 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 1563440 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 239107 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 6.538663 # Average number of references to valid blocks.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.occ_blocks::0 7625.121037 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 13497.615194 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_percent::0 0.232700 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::1 0.411915 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 759429 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 1078034 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_hits 1135 # number of UpgradeReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits 231317 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits 990746 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits 990746 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 130133 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses 466 # number of UpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 107854 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses 237987 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses 237987 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 4450629000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_latency 3872500 # number of UpgradeReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 3694232000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 8144861000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 8144861000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 889562 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 1078034 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses 1601 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses 339171 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses 1228733 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses 1228733 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.146289 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 0.291068 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.317993 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.193685 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.193685 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34200.617829 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 8310.085837 # average UpgradeReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34252.155692 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34223.974419 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34223.974419 # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.writebacks 171107 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits 21 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits 21 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 21 # number of overall MSHR hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 130112 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 466 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 107854 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 237966 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 237966 # number of overall MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 4038190500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14451000 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 3344342000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 7382532500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 7382532500 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.146265 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.291068 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.317993 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.193668 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.193668 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31036.264910 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31010.729614 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31008.047917 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31023.476043 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31023.476043 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-01-18 23:30:06 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
