2006-09-01 23:59:36 +02:00
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---------- Begin Simulation Statistics ----------
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global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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global.BPredUnit.BTBHits 155 # Number of BTB hits
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global.BPredUnit.BTBLookups 711 # Number of BTB lookups
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global.BPredUnit.RASInCorrect 37 # Number of incorrect RAS predictions.
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global.BPredUnit.condIncorrect 222 # Number of conditional branches incorrect
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global.BPredUnit.condPredicted 441 # Number of conditional branches predicted
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global.BPredUnit.lookups 888 # Number of BP lookups
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global.BPredUnit.usedRAS 160 # Number of times the RAS was used to get a target.
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2006-09-05 22:24:47 +02:00
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host_inst_rate 26468 # Simulator instruction rate (inst/s)
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host_mem_usage 159864 # Number of bytes of host memory used
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host_seconds 0.09 # Real time elapsed on the host
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host_tick_rate 31894 # Simulator tick rate (ticks/s)
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2006-09-01 23:59:36 +02:00
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memdepunit.memDep.conflictingLoads 9 # Number of conflicting loads.
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memdepunit.memDep.conflictingStores 7 # Number of conflicting stores.
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memdepunit.memDep.insertedLoads 675 # Number of loads inserted to the mem dependence unit.
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memdepunit.memDep.insertedStores 369 # Number of stores inserted to the mem dependence unit.
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 2387 # Number of instructions simulated
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sim_seconds 0.000000 # Number of seconds simulated
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sim_ticks 2886 # Number of ticks simulated
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system.cpu.commit.COM:branches 396 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 40 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle.samples 2646
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system.cpu.commit.COM:committed_per_cycle.min_value 0
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0 1713 6473.92%
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1 239 903.25%
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2 322 1216.93%
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3 139 525.32%
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4 78 294.78%
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5 67 253.21%
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6 27 102.04%
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7 21 79.37%
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8 40 151.17%
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system.cpu.commit.COM:committed_per_cycle.max_value 8
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system.cpu.commit.COM:committed_per_cycle.end_dist
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system.cpu.commit.COM:count 2576 # Number of instructions committed
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system.cpu.commit.COM:loads 415 # Number of loads committed
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system.cpu.commit.COM:membars 0 # Number of memory barriers committed
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system.cpu.commit.COM:refs 709 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.branchMispredicts 138 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 1258 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 2387 # Number of Instructions Simulated
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system.cpu.committedInsts_total 2387 # Number of Instructions Simulated
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system.cpu.cpi 1.209049 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 1.209049 # CPI: Total CPI of All Threads
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system.cpu.dcache.ReadReq_accesses 535 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 470 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 195 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.121495 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 65 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 4 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 122 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.114019 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 3.017241 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.208333 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 236 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 175 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.197279 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 58 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 34 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 53 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.081633 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 24 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets 1.500000 # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 8.305882 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 2 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 3 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 829 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 3.008130 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 2.058824 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 706 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 370 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.148372 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 123 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 38 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 175 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.102533 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 85 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 829 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 3.008130 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 2.058824 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 706 # number of overall hits
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system.cpu.dcache.overall_miss_latency 370 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.148372 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 123 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 38 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 175 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.102533 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 85 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.dcache.replacements 0 # number of replacements
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system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 54.161413 # Cycle average of tags in use
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system.cpu.dcache.total_refs 706 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 0 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 82 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 90 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 156 # Number of times decode resolved a branch
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system.cpu.decode.DECODE:DecodedInsts 4646 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 1691 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 873 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 240 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:SquashedInsts 315 # Number of squashed instructions handled by decode
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system.cpu.decode.DECODE:UnblockCycles 1 # Number of cycles decode is unblocking
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system.cpu.fetch.Branches 888 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 740 # Number of cache lines fetched
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system.cpu.fetch.Cycles 1663 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 77 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 5518 # Number of instructions fetch has processed
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system.cpu.fetch.SquashCycles 235 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.307586 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 740 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 315 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 1.911327 # Number of inst fetches per cycle
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system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist.samples 2887
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system.cpu.fetch.rateDist.min_value 0
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0 1965 6806.37%
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1 36 124.70%
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2 79 273.64%
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3 66 228.61%
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4 125 432.98%
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5 60 207.83%
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6 40 138.55%
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7 42 145.48%
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8 474 1641.84%
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system.cpu.fetch.rateDist.max_value 8
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system.cpu.fetch.rateDist.end_dist
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system.cpu.icache.ReadReq_accesses 740 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 2.989474 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 550 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 568 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.256757 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 190 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits
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system.cpu.icache.ReadReq_mshr_miss_latency 378 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.255405 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 189 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 2.910053 # Average number of references to valid blocks.
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system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 740 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 2.989474 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency
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system.cpu.icache.demand_hits 550 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 568 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.256757 # miss rate for demand accesses
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system.cpu.icache.demand_misses 190 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 1 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 378 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.255405 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 189 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_accesses 740 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 2.989474 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 550 # number of overall hits
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system.cpu.icache.overall_miss_latency 568 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.256757 # miss rate for overall accesses
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system.cpu.icache.overall_misses 190 # number of overall misses
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system.cpu.icache.overall_mshr_hits 1 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 378 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.255405 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 189 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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|
|
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
|
|
|
system.cpu.icache.replacements 0 # number of replacements
|
|
|
|
|
system.cpu.icache.sampled_refs 189 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.icache.tagsinuse 115.538968 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 550 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
|
|
|
|
system.cpu.iew.EXEC:branches 533 # Number of branches executed
|
|
|
|
|
system.cpu.iew.EXEC:insts 3123 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.EXEC:loads 578 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.EXEC:nop 247 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.EXEC:rate 1.081746 # Inst execution rate
|
|
|
|
|
system.cpu.iew.EXEC:refs 914 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.EXEC:squashedInsts 148 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu.iew.EXEC:stores 336 # Number of stores executed
|
|
|
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
|
|
|
|
system.cpu.iew.WB:consumers 1801 # num instructions consuming a value
|
|
|
|
|
system.cpu.iew.WB:count 3070 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.WB:fanout 0.791227 # average fanout of values written-back
|
|
|
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
|
|
|
system.cpu.iew.WB:producers 1425 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.WB:rate 1.063388 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.WB:sent 3076 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.branchMispredicts 159 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 675 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 7 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 127 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 369 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 3835 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewSquashCycles 240 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
|
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 2 # Number of times an access to memory failed due to the cache being blocked
|
|
|
|
|
system.cpu.iew.lsq.thread.0.forwLoads 30 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 260 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedStores 75 # Number of stores squashed
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 11 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 106 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 53 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.ipc 0.827096 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 0.827096 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue
|
|
|
|
|
system.cpu.iq.IQ:residence:(null).samples 0
|
|
|
|
|
system.cpu.iq.IQ:residence:(null).min_value 0
|
|
|
|
|
0 0
|
|
|
|
|
2 0
|
|
|
|
|
4 0
|
|
|
|
|
6 0
|
|
|
|
|
8 0
|
|
|
|
|
10 0
|
|
|
|
|
12 0
|
|
|
|
|
14 0
|
|
|
|
|
16 0
|
|
|
|
|
18 0
|
|
|
|
|
20 0
|
|
|
|
|
22 0
|
|
|
|
|
24 0
|
|
|
|
|
26 0
|
|
|
|
|
28 0
|
|
|
|
|
30 0
|
|
|
|
|
32 0
|
|
|
|
|
34 0
|
|
|
|
|
36 0
|
|
|
|
|
38 0
|
|
|
|
|
40 0
|
|
|
|
|
42 0
|
|
|
|
|
44 0
|
|
|
|
|
46 0
|
|
|
|
|
48 0
|
|
|
|
|
50 0
|
|
|
|
|
52 0
|
|
|
|
|
54 0
|
|
|
|
|
56 0
|
|
|
|
|
58 0
|
|
|
|
|
60 0
|
|
|
|
|
62 0
|
|
|
|
|
64 0
|
|
|
|
|
66 0
|
|
|
|
|
68 0
|
|
|
|
|
70 0
|
|
|
|
|
72 0
|
|
|
|
|
74 0
|
|
|
|
|
76 0
|
|
|
|
|
78 0
|
|
|
|
|
80 0
|
|
|
|
|
82 0
|
|
|
|
|
84 0
|
|
|
|
|
86 0
|
|
|
|
|
88 0
|
|
|
|
|
90 0
|
|
|
|
|
92 0
|
|
|
|
|
94 0
|
|
|
|
|
96 0
|
|
|
|
|
98 0
|
|
|
|
|
system.cpu.iq.IQ:residence:(null).max_value 0
|
|
|
|
|
system.cpu.iq.IQ:residence:(null).end_dist
|
|
|
|
|
|
|
|
|
|
system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue
|
|
|
|
|
system.cpu.iq.IQ:residence:IntAlu.samples 0
|
|
|
|
|
system.cpu.iq.IQ:residence:IntAlu.min_value 0
|
|
|
|
|
0 0
|
|
|
|
|
2 0
|
|
|
|
|
4 0
|
|
|
|
|
6 0
|
|
|
|
|
8 0
|
|
|
|
|
10 0
|
|
|
|
|
12 0
|
|
|
|
|
14 0
|
|
|
|
|
16 0
|
|
|
|
|
18 0
|
|
|
|
|
20 0
|
|
|
|
|
22 0
|
|
|
|
|
24 0
|
|
|
|
|
26 0
|
|
|
|
|
28 0
|
|
|
|
|
30 0
|
|
|
|
|
32 0
|
|
|
|
|
34 0
|
|
|
|
|
36 0
|
|
|
|
|
38 0
|
|
|
|
|
40 0
|
|
|
|
|
42 0
|
|
|
|
|
44 0
|
|
|
|
|
46 0
|
|
|
|
|
48 0
|
|
|
|
|
50 0
|
|
|
|
|
52 0
|
|
|
|
|
54 0
|
|
|
|
|
56 0
|
|
|
|
|
58 0
|
|
|
|
|
60 0
|
|
|
|
|
62 0
|
|
|
|
|
64 0
|
|
|
|
|
66 0
|
|
|
|
|
68 0
|
|
|
|
|
70 0
|
|
|
|
|
72 0
|
|
|
|
|
74 0
|
|
|
|
|
76 0
|
|
|
|
|
78 0
|
|
|
|
|
80 0
|
|
|
|
|
82 0
|
|
|
|
|
84 0
|
|
|
|
|
86 0
|
|
|
|
|
88 0
|
|
|
|
|
90 0
|
|
|
|
|
92 0
|
|
|
|
|
94 0
|
|
|
|
|
96 0
|
|
|
|
|
98 0
|
|
|
|
|
system.cpu.iq.IQ:residence:IntAlu.max_value 0
|
|
|
|
|
system.cpu.iq.IQ:residence:IntAlu.end_dist
|
|
|
|
|
|
|
|
|
|
system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue
|
|
|
|
|
system.cpu.iq.IQ:residence:IntMult.samples 0
|
|
|
|
|
system.cpu.iq.IQ:residence:IntMult.min_value 0
|
|
|
|
|
0 0
|
|
|
|
|
2 0
|
|
|
|
|
4 0
|
|
|
|
|
6 0
|
|
|
|
|
8 0
|
|
|
|
|
10 0
|
|
|
|
|
12 0
|
|
|
|
|
14 0
|
|
|
|
|
16 0
|
|
|
|
|
18 0
|
|
|
|
|
20 0
|
|
|
|
|
22 0
|
|
|
|
|
24 0
|
|
|
|
|
26 0
|
|
|
|
|
28 0
|
|
|
|
|
30 0
|
|
|
|
|
32 0
|
|
|
|
|
34 0
|
|
|
|
|
36 0
|
|
|
|
|
38 0
|
|
|
|
|
40 0
|
|
|
|
|
42 0
|
|
|
|
|
44 0
|
|
|
|
|
46 0
|
|
|
|
|
48 0
|
|
|
|
|
50 0
|
|
|
|
|
52 0
|
|
|
|
|
54 0
|
|
|
|
|
56 0
|
|
|
|
|
58 0
|
|
|
|
|
60 0
|
|
|
|
|
62 0
|
|
|
|
|
64 0
|
|
|
|
|
66 0
|
|
|
|
|
68 0
|
|
|
|
|
70 0
|
|
|
|
|
72 0
|
|
|
|
|
74 0
|
|
|
|
|
76 0
|
|
|
|
|
78 0
|
|
|
|
|
80 0
|
|
|
|
|
82 0
|
|
|
|
|
84 0
|
|
|
|
|
86 0
|
|
|
|
|
88 0
|
|
|
|
|
90 0
|
|
|
|
|
92 0
|
|
|
|
|
94 0
|
|
|
|
|
96 0
|
|
|
|
|
98 0
|
|
|
|
|
system.cpu.iq.IQ:residence:IntMult.max_value 0
|
|
|
|
|
system.cpu.iq.IQ:residence:IntMult.end_dist
|
|
|
|
|
|
|
|
|
|
system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue
|
|
|
|
|
system.cpu.iq.IQ:residence:IntDiv.samples 0
|
|
|
|
|
system.cpu.iq.IQ:residence:IntDiv.min_value 0
|
|
|
|
|
0 0
|
|
|
|
|
2 0
|
|
|
|
|
4 0
|
|
|
|
|
6 0
|
|
|
|
|
8 0
|
|
|
|
|
10 0
|
|
|
|
|
12 0
|
|
|
|
|
14 0
|
|
|
|
|
16 0
|
|
|
|
|
18 0
|
|
|
|
|
20 0
|
|
|
|
|
22 0
|
|
|
|
|
24 0
|
|
|
|
|
26 0
|
|
|
|
|
28 0
|
|
|
|
|
30 0
|
|
|
|
|
32 0
|
|
|
|
|
34 0
|
|
|
|
|
36 0
|
|
|
|
|
38 0
|
|
|
|
|
40 0
|
|
|
|
|
42 0
|
|
|
|
|
44 0
|
|
|
|
|
46 0
|
|
|
|
|
48 0
|
|
|
|
|
50 0
|
|
|
|
|
52 0
|
|
|
|
|
54 0
|
|
|
|
|
56 0
|
|
|
|
|
58 0
|
|
|
|
|
60 0
|
|
|
|
|
62 0
|
|
|
|
|
64 0
|
|
|
|
|
66 0
|
|
|
|
|
68 0
|
|
|
|
|
70 0
|
|
|
|
|
72 0
|
|
|
|
|
74 0
|
|
|
|
|
76 0
|
|
|
|
|
78 0
|
|
|
|
|
80 0
|
|
|
|
|
82 0
|
|
|
|
|
84 0
|
|
|
|
|
86 0
|
|
|
|
|
88 0
|
|
|
|
|
90 0
|
|
|
|
|
92 0
|
|
|
|
|
94 0
|
|
|
|
|
96 0
|
|
|
|
|
98 0
|
|
|
|
|
system.cpu.iq.IQ:residence:IntDiv.max_value 0
|
|
|
|
|
system.cpu.iq.IQ:residence:IntDiv.end_dist
|
|
|
|
|
|
|
|
|
|
system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue
|
|
|
|
|
system.cpu.iq.IQ:residence:FloatAdd.samples 0
|
|
|
|
|
system.cpu.iq.IQ:residence:FloatAdd.min_value 0
|
|
|
|
|
0 0
|
|
|
|
|
2 0
|
|
|
|
|
4 0
|
|
|
|
|
6 0
|
|
|
|
|
8 0
|
|
|
|
|
10 0
|
|
|
|
|
12 0
|
|
|
|
|
14 0
|
|
|
|
|
16 0
|
|
|
|
|
18 0
|
|
|
|
|
20 0
|
|
|
|
|
22 0
|
|
|
|
|
24 0
|
|
|
|
|
26 0
|
|
|
|
|
28 0
|
|
|
|
|
30 0
|
|
|
|
|
32 0
|
|
|
|
|
34 0
|
|
|
|
|
36 0
|
|
|
|
|
38 0
|
|
|
|
|
40 0
|
|
|
|
|
42 0
|
|
|
|
|
44 0
|
|
|
|
|
46 0
|
|
|
|
|
48 0
|
|
|
|
|
50 0
|
|
|
|
|
52 0
|
|
|
|
|
54 0
|
|
|
|
|
56 0
|
|
|
|
|
58 0
|
|
|
|
|
60 0
|
|
|
|
|
62 0
|
|
|
|
|
64 0
|
|
|
|
|
66 0
|
|
|
|
|
68 0
|
|
|
|
|
70 0
|
|
|
|
|
72 0
|
|
|
|
|
74 0
|
|
|
|
|
76 0
|
|
|
|
|
78 0
|
|
|
|
|
80 0
|
|
|
|
|
82 0
|
|
|
|
|
84 0
|
|
|
|
|
86 0
|
|
|
|
|
88 0
|
|
|
|
|
90 0
|
|
|
|
|
92 0
|
|
|
|
|
94 0
|
|
|
|
|
96 0
|
|
|
|
|
98 0
|
|
|
|
|
system.cpu.iq.IQ:residence:FloatAdd.max_value 0
|
|
|
|
|
system.cpu.iq.IQ:residence:FloatAdd.end_dist
|
|
|
|
|
|
|
|
|
|
system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue
|
|
|
|
|
system.cpu.iq.IQ:residence:FloatCmp.samples 0
|
|
|
|
|
system.cpu.iq.IQ:residence:FloatCmp.min_value 0
|
|
|
|
|
0 0
|
|
|
|
|
2 0
|
|
|
|
|
4 0
|
|
|
|
|
6 0
|
|
|
|
|
8 0
|
|
|
|
|
10 0
|
|
|
|
|
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94 0
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96 0
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98 0
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system.cpu.iq.IQ:residence:FloatCmp.max_value 0
|
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system.cpu.iq.IQ:residence:FloatCmp.end_dist
|
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system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue
|
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|
|
system.cpu.iq.IQ:residence:FloatCvt.samples 0
|
|
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system.cpu.iq.IQ:residence:FloatCvt.min_value 0
|
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0 0
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2 0
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94 0
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96 0
|
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98 0
|
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system.cpu.iq.IQ:residence:FloatCvt.max_value 0
|
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|
system.cpu.iq.IQ:residence:FloatCvt.end_dist
|
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|
system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue
|
|
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|
|
system.cpu.iq.IQ:residence:FloatMult.samples 0
|
|
|
|
|
system.cpu.iq.IQ:residence:FloatMult.min_value 0
|
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0 0
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2 0
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4 0
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82 0
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86 0
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94 0
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96 0
|
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98 0
|
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|
system.cpu.iq.IQ:residence:FloatMult.max_value 0
|
|
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|
|
system.cpu.iq.IQ:residence:FloatMult.end_dist
|
|
|
|
|
|
|
|
|
|
system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue
|
|
|
|
|
system.cpu.iq.IQ:residence:FloatDiv.samples 0
|
|
|
|
|
system.cpu.iq.IQ:residence:FloatDiv.min_value 0
|
|
|
|
|
0 0
|
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2 0
|
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4 0
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6 0
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12 0
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48 0
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50 0
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54 0
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56 0
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58 0
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60 0
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62 0
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66 0
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68 0
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70 0
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72 0
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74 0
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76 0
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78 0
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80 0
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82 0
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84 0
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86 0
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88 0
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92 0
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94 0
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96 0
|
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98 0
|
|
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|
system.cpu.iq.IQ:residence:FloatDiv.max_value 0
|
|
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|
|
system.cpu.iq.IQ:residence:FloatDiv.end_dist
|
|
|
|
|
|
|
|
|
|
system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue
|
|
|
|
|
system.cpu.iq.IQ:residence:FloatSqrt.samples 0
|
|
|
|
|
system.cpu.iq.IQ:residence:FloatSqrt.min_value 0
|
|
|
|
|
0 0
|
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2 0
|
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4 0
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60 0
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62 0
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66 0
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68 0
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70 0
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72 0
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74 0
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76 0
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78 0
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80 0
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82 0
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86 0
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90 0
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92 0
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94 0
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96 0
|
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98 0
|
|
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|
|
system.cpu.iq.IQ:residence:FloatSqrt.max_value 0
|
|
|
|
|
system.cpu.iq.IQ:residence:FloatSqrt.end_dist
|
|
|
|
|
|
|
|
|
|
system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue
|
|
|
|
|
system.cpu.iq.IQ:residence:MemRead.samples 0
|
|
|
|
|
system.cpu.iq.IQ:residence:MemRead.min_value 0
|
|
|
|
|
0 0
|
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2 0
|
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4 0
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6 0
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70 0
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76 0
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78 0
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80 0
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82 0
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94 0
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96 0
|
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98 0
|
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|
|
system.cpu.iq.IQ:residence:MemRead.max_value 0
|
|
|
|
|
system.cpu.iq.IQ:residence:MemRead.end_dist
|
|
|
|
|
|
|
|
|
|
system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue
|
|
|
|
|
system.cpu.iq.IQ:residence:MemWrite.samples 0
|
|
|
|
|
system.cpu.iq.IQ:residence:MemWrite.min_value 0
|
|
|
|
|
0 0
|
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2 0
|
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4 0
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54 0
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56 0
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60 0
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62 0
|
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64 0
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66 0
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68 0
|
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70 0
|
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72 0
|
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74 0
|
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76 0
|
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78 0
|
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80 0
|
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82 0
|
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84 0
|
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86 0
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92 0
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94 0
|
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|
96 0
|
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|
98 0
|
|
|
|
|
system.cpu.iq.IQ:residence:MemWrite.max_value 0
|
|
|
|
|
system.cpu.iq.IQ:residence:MemWrite.end_dist
|
|
|
|
|
|
|
|
|
|
system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue
|
|
|
|
|
system.cpu.iq.IQ:residence:IprAccess.samples 0
|
|
|
|
|
system.cpu.iq.IQ:residence:IprAccess.min_value 0
|
|
|
|
|
0 0
|
|
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|
2 0
|
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4 0
|
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6 0
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12 0
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14 0
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16 0
|
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18 0
|
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20 0
|
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22 0
|
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24 0
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26 0
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28 0
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system.cpu.iq.IQ:residence:IprAccess.max_value 0
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system.cpu.iq.IQ:residence:IprAccess.end_dist
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system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue
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system.cpu.iq.IQ:residence:InstPrefetch.samples 0
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system.cpu.iq.IQ:residence:InstPrefetch.min_value 0
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system.cpu.iq.IQ:residence:InstPrefetch.max_value 0
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system.cpu.iq.IQ:residence:InstPrefetch.end_dist
|
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system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue
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system.cpu.iq.ISSUE:(null)_delay.samples 0
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system.cpu.iq.ISSUE:(null)_delay.min_value 0
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system.cpu.iq.ISSUE:(null)_delay.max_value 0
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system.cpu.iq.ISSUE:(null)_delay.end_dist
|
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system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue
|
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system.cpu.iq.ISSUE:IntAlu_delay.samples 0
|
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system.cpu.iq.ISSUE:IntAlu_delay.min_value 0
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0 0
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98 0
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system.cpu.iq.ISSUE:IntAlu_delay.max_value 0
|
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|
system.cpu.iq.ISSUE:IntAlu_delay.end_dist
|
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system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue
|
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|
system.cpu.iq.ISSUE:IntMult_delay.samples 0
|
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system.cpu.iq.ISSUE:IntMult_delay.min_value 0
|
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0 0
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2 0
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96 0
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98 0
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system.cpu.iq.ISSUE:IntMult_delay.max_value 0
|
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|
|
system.cpu.iq.ISSUE:IntMult_delay.end_dist
|
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|
|
system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue
|
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|
|
system.cpu.iq.ISSUE:IntDiv_delay.samples 0
|
|
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|
system.cpu.iq.ISSUE:IntDiv_delay.min_value 0
|
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0 0
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2 0
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94 0
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96 0
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98 0
|
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|
system.cpu.iq.ISSUE:IntDiv_delay.max_value 0
|
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|
|
|
system.cpu.iq.ISSUE:IntDiv_delay.end_dist
|
|
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|
|
system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue
|
|
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|
|
system.cpu.iq.ISSUE:FloatAdd_delay.samples 0
|
|
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|
|
system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0
|
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0 0
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2 0
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96 0
|
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98 0
|
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|
system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0
|
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|
|
system.cpu.iq.ISSUE:FloatAdd_delay.end_dist
|
|
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|
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|
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|
|
system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue
|
|
|
|
|
system.cpu.iq.ISSUE:FloatCmp_delay.samples 0
|
|
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|
|
system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0
|
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0 0
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system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0
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system.cpu.iq.ISSUE:FloatCmp_delay.end_dist
|
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system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue
|
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system.cpu.iq.ISSUE:FloatCvt_delay.samples 0
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system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0
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system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0
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system.cpu.iq.ISSUE:FloatCvt_delay.end_dist
|
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system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue
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system.cpu.iq.ISSUE:FloatMult_delay.samples 0
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system.cpu.iq.ISSUE:FloatMult_delay.min_value 0
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system.cpu.iq.ISSUE:FloatMult_delay.max_value 0
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system.cpu.iq.ISSUE:FloatMult_delay.end_dist
|
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system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue
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system.cpu.iq.ISSUE:FloatDiv_delay.samples 0
|
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system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0
|
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0 0
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system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0
|
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|
system.cpu.iq.ISSUE:FloatDiv_delay.end_dist
|
|
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|
system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue
|
|
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|
|
system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0
|
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system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0
|
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0 0
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system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0
|
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|
system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist
|
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|
system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue
|
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|
|
system.cpu.iq.ISSUE:MemRead_delay.samples 0
|
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|
system.cpu.iq.ISSUE:MemRead_delay.min_value 0
|
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0 0
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2 0
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96 0
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98 0
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system.cpu.iq.ISSUE:MemRead_delay.max_value 0
|
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|
|
system.cpu.iq.ISSUE:MemRead_delay.end_dist
|
|
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|
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|
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|
|
system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue
|
|
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|
|
system.cpu.iq.ISSUE:MemWrite_delay.samples 0
|
|
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|
|
system.cpu.iq.ISSUE:MemWrite_delay.min_value 0
|
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0 0
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2 0
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96 0
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98 0
|
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|
system.cpu.iq.ISSUE:MemWrite_delay.max_value 0
|
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|
|
system.cpu.iq.ISSUE:MemWrite_delay.end_dist
|
|
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|
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|
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|
|
system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue
|
|
|
|
|
system.cpu.iq.ISSUE:IprAccess_delay.samples 0
|
|
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|
|
system.cpu.iq.ISSUE:IprAccess_delay.min_value 0
|
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0 0
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64 0
|
|
|
|
|
66 0
|
|
|
|
|
68 0
|
|
|
|
|
70 0
|
|
|
|
|
72 0
|
|
|
|
|
74 0
|
|
|
|
|
76 0
|
|
|
|
|
78 0
|
|
|
|
|
80 0
|
|
|
|
|
82 0
|
|
|
|
|
84 0
|
|
|
|
|
86 0
|
|
|
|
|
88 0
|
|
|
|
|
90 0
|
|
|
|
|
92 0
|
|
|
|
|
94 0
|
|
|
|
|
96 0
|
|
|
|
|
98 0
|
|
|
|
|
system.cpu.iq.ISSUE:IprAccess_delay.max_value 0
|
|
|
|
|
system.cpu.iq.ISSUE:IprAccess_delay.end_dist
|
|
|
|
|
|
|
|
|
|
system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue
|
|
|
|
|
system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0
|
|
|
|
|
system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0
|
|
|
|
|
0 0
|
|
|
|
|
2 0
|
|
|
|
|
4 0
|
|
|
|
|
6 0
|
|
|
|
|
8 0
|
|
|
|
|
10 0
|
|
|
|
|
12 0
|
|
|
|
|
14 0
|
|
|
|
|
16 0
|
|
|
|
|
18 0
|
|
|
|
|
20 0
|
|
|
|
|
22 0
|
|
|
|
|
24 0
|
|
|
|
|
26 0
|
|
|
|
|
28 0
|
|
|
|
|
30 0
|
|
|
|
|
32 0
|
|
|
|
|
34 0
|
|
|
|
|
36 0
|
|
|
|
|
38 0
|
|
|
|
|
40 0
|
|
|
|
|
42 0
|
|
|
|
|
44 0
|
|
|
|
|
46 0
|
|
|
|
|
48 0
|
|
|
|
|
50 0
|
|
|
|
|
52 0
|
|
|
|
|
54 0
|
|
|
|
|
56 0
|
|
|
|
|
58 0
|
|
|
|
|
60 0
|
|
|
|
|
62 0
|
|
|
|
|
64 0
|
|
|
|
|
66 0
|
|
|
|
|
68 0
|
|
|
|
|
70 0
|
|
|
|
|
72 0
|
|
|
|
|
74 0
|
|
|
|
|
76 0
|
|
|
|
|
78 0
|
|
|
|
|
80 0
|
|
|
|
|
82 0
|
|
|
|
|
84 0
|
|
|
|
|
86 0
|
|
|
|
|
88 0
|
|
|
|
|
90 0
|
|
|
|
|
92 0
|
|
|
|
|
94 0
|
|
|
|
|
96 0
|
|
|
|
|
98 0
|
|
|
|
|
system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0
|
|
|
|
|
system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist
|
|
|
|
|
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0 3271 # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
|
|
|
|
(null) 0 0.00% # Type of FU issued
|
|
|
|
|
IntAlu 2317 70.83% # Type of FU issued
|
|
|
|
|
IntMult 1 0.03% # Type of FU issued
|
|
|
|
|
IntDiv 0 0.00% # Type of FU issued
|
|
|
|
|
FloatAdd 0 0.00% # Type of FU issued
|
|
|
|
|
FloatCmp 0 0.00% # Type of FU issued
|
|
|
|
|
FloatCvt 0 0.00% # Type of FU issued
|
|
|
|
|
FloatMult 0 0.00% # Type of FU issued
|
|
|
|
|
FloatDiv 0 0.00% # Type of FU issued
|
|
|
|
|
FloatSqrt 0 0.00% # Type of FU issued
|
|
|
|
|
MemRead 609 18.62% # Type of FU issued
|
|
|
|
|
MemWrite 344 10.52% # Type of FU issued
|
|
|
|
|
IprAccess 0 0.00% # Type of FU issued
|
|
|
|
|
InstPrefetch 0 0.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
|
|
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 40 # FU busy when requested
|
|
|
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.012229 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full.start_dist
|
|
|
|
|
(null) 0 0.00% # attempts to use FU when none available
|
|
|
|
|
IntAlu 5 12.50% # attempts to use FU when none available
|
|
|
|
|
IntMult 0 0.00% # attempts to use FU when none available
|
|
|
|
|
IntDiv 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatAdd 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatCmp 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatCvt 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatMult 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatDiv 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatSqrt 0 0.00% # attempts to use FU when none available
|
|
|
|
|
MemRead 12 30.00% # attempts to use FU when none available
|
|
|
|
|
MemWrite 23 57.50% # attempts to use FU when none available
|
|
|
|
|
IprAccess 0 0.00% # attempts to use FU when none available
|
|
|
|
|
InstPrefetch 0 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full.end_dist
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.samples 2887
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
|
|
|
|
0 1603 5552.48%
|
|
|
|
|
1 434 1503.29%
|
|
|
|
|
2 301 1042.60%
|
|
|
|
|
3 220 762.04%
|
|
|
|
|
4 167 578.46%
|
|
|
|
|
5 94 325.60%
|
|
|
|
|
6 46 159.33%
|
|
|
|
|
7 15 51.96%
|
|
|
|
|
8 7 24.25%
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
|
|
|
|
|
|
|
|
|
system.cpu.iq.ISSUE:rate 1.133010 # Inst issue rate
|
|
|
|
|
system.cpu.iq.iqInstsAdded 3581 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqInstsIssued 3271 # Number of instructions issued
|
|
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 7 # Number of non-speculative instructions added to the IQ
|
|
|
|
|
system.cpu.iq.iqSquashedInstsExamined 1067 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed
|
|
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 477 # Number of squashed operands that are examined and possibly removed from graph
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 274 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 2.018248 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 553 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 274 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 274 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 274 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.l2cache.demand_accesses 274 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 2.018248 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 553 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_misses 274 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 274 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 274 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.l2cache.overall_accesses 274 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 2.018248 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.overall_hits 0 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 553 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_misses 274 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 274 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 274 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
|
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
|
|
|
system.cpu.l2cache.sampled_refs 274 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.l2cache.tagsinuse 169.795289 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
|
|
|
|
system.cpu.numCycles 2887 # number of cpu cycles simulated
|
|
|
|
|
system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed
|
|
|
|
|
system.cpu.rename.RENAME:IdleCycles 1780 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.RENAME:LSQFullEvents 2 # Number of times rename has blocked due to LSQ full
|
|
|
|
|
system.cpu.rename.RENAME:RenameLookups 4975 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.RENAME:RenamedInsts 4400 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.RENAME:RenamedOperands 3144 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RENAME:RunCycles 785 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.RENAME:SquashCycles 240 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.RENAME:UnblockCycles 8 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.RENAME:UndoneMaps 1376 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.RENAME:serializeStallCycles 74 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.RENAME:serializingInsts 10 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.RENAME:skidInsts 62 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu.rename.RENAME:tempSerializingInsts 8 # count of temporary serializing insts renamed
|
|
|
|
|
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
|
|
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
