2006-09-01 23:59:36 +02:00
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---------- Begin Simulation Statistics ----------
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global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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global.BPredUnit.BTBHits 542 # Number of BTB hits
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global.BPredUnit.BTBLookups 1938 # Number of BTB lookups
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global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions.
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global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect
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global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted
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global.BPredUnit.lookups 2256 # Number of BP lookups
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global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target.
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2006-09-05 22:24:47 +02:00
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host_inst_rate 41797 # Simulator instruction rate (inst/s)
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host_mem_usage 160344 # Number of bytes of host memory used
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host_seconds 0.13 # Real time elapsed on the host
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host_tick_rate 50948 # Simulator tick rate (ticks/s)
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2006-09-01 23:59:36 +02:00
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memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads.
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memdepunit.memDep.conflictingStores 259 # Number of conflicting stores.
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memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit.
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memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit.
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 5623 # Number of instructions simulated
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sim_seconds 0.000000 # Number of seconds simulated
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sim_ticks 6870 # Number of ticks simulated
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system.cpu.commit.COM:branches 862 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle.samples 6116
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system.cpu.commit.COM:committed_per_cycle.min_value 0
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0 3908 6389.80%
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1 1064 1739.70%
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2 389 636.04%
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3 210 343.36%
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4 153 250.16%
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5 93 152.06%
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6 76 124.26%
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7 149 243.62%
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8 74 120.99%
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system.cpu.commit.COM:committed_per_cycle.max_value 8
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system.cpu.commit.COM:committed_per_cycle.end_dist
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system.cpu.commit.COM:count 5640 # Number of instructions committed
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system.cpu.commit.COM:loads 979 # Number of loads committed
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system.cpu.commit.COM:membars 0 # Number of memory barriers committed
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system.cpu.commit.COM:refs 1791 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 5623 # Number of Instructions Simulated
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system.cpu.committedInsts_total 5623 # Number of Instructions Simulated
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system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads
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system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 2048 # number of overall hits
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system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 311 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.dcache.replacements 0 # number of replacements
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system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use
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system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 0 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch
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system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode
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system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking
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system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched
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system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed
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system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle
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system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist.samples 6871
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system.cpu.fetch.rateDist.min_value 0
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0 4549 6620.58%
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1 174 253.24%
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2 186 270.70%
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3 157 228.50%
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4 211 307.09%
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5 153 222.68%
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6 171 248.87%
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7 105 152.82%
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8 1165 1695.53%
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system.cpu.fetch.rateDist.max_value 8
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system.cpu.fetch.rateDist.end_dist
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system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits
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system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses
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2006-09-05 22:24:47 +02:00
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system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
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2006-09-01 23:59:36 +02:00
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system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks.
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system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
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system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses
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system.cpu.icache.demand_misses 327 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 1255 # number of overall hits
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system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses
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system.cpu.icache.overall_misses 327 # number of overall misses
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system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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|
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
|
|
|
system.cpu.icache.replacements 0 # number of replacements
|
|
|
|
|
system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 1255 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
|
|
|
|
system.cpu.iew.EXEC:branches 1206 # Number of branches executed
|
|
|
|
|
system.cpu.iew.EXEC:insts 7969 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.EXEC:nop 37 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate
|
|
|
|
|
system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu.iew.EXEC:stores 989 # Number of stores executed
|
|
|
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
|
|
|
|
system.cpu.iew.WB:consumers 5438 # num instructions consuming a value
|
|
|
|
|
system.cpu.iew.WB:count 7722 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back
|
|
|
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
|
|
|
system.cpu.iew.WB:producers 4049 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding
|
|
|
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked
|
|
|
|
|
system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue
|
|
|
|
|
system.cpu.iq.IQ:residence:(null).samples 0
|
|
|
|
|
system.cpu.iq.IQ:residence:(null).min_value 0
|
|
|
|
|
0 0
|
|
|
|
|
2 0
|
|
|
|
|
4 0
|
|
|
|
|
6 0
|
|
|
|
|
8 0
|
|
|
|
|
10 0
|
|
|
|
|
12 0
|
|
|
|
|
14 0
|
|
|
|
|
16 0
|
|
|
|
|
18 0
|
|
|
|
|
20 0
|
|
|
|
|
22 0
|
|
|
|
|
24 0
|
|
|
|
|
26 0
|
|
|
|
|
28 0
|
|
|
|
|
30 0
|
|
|
|
|
32 0
|
|
|
|
|
34 0
|
|
|
|
|
36 0
|
|
|
|
|
38 0
|
|
|
|
|
40 0
|
|
|
|
|
42 0
|
|
|
|
|
44 0
|
|
|
|
|
46 0
|
|
|
|
|
48 0
|
|
|
|
|
50 0
|
|
|
|
|
52 0
|
|
|
|
|
54 0
|
|
|
|
|
56 0
|
|
|
|
|
58 0
|
|
|
|
|
60 0
|
|
|
|
|
62 0
|
|
|
|
|
64 0
|
|
|
|
|
66 0
|
|
|
|
|
68 0
|
|
|
|
|
70 0
|
|
|
|
|
72 0
|
|
|
|
|
74 0
|
|
|
|
|
76 0
|
|
|
|
|
78 0
|
|
|
|
|
80 0
|
|
|
|
|
82 0
|
|
|
|
|
84 0
|
|
|
|
|
86 0
|
|
|
|
|
88 0
|
|
|
|
|
90 0
|
|
|
|
|
92 0
|
|
|
|
|
94 0
|
|
|
|
|
96 0
|
|
|
|
|
98 0
|
|
|
|
|
system.cpu.iq.IQ:residence:(null).max_value 0
|
|
|
|
|
system.cpu.iq.IQ:residence:(null).end_dist
|
|
|
|
|
|
|
|
|
|
system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue
|
|
|
|
|
system.cpu.iq.IQ:residence:IntAlu.samples 0
|
|
|
|
|
system.cpu.iq.IQ:residence:IntAlu.min_value 0
|
|
|
|
|
0 0
|
|
|
|
|
2 0
|
|
|
|
|
4 0
|
|
|
|
|
6 0
|
|
|
|
|
8 0
|
|
|
|
|
10 0
|
|
|
|
|
12 0
|
|
|
|
|
14 0
|
|
|
|
|
16 0
|
|
|
|
|
18 0
|
|
|
|
|
20 0
|
|
|
|
|
22 0
|
|
|
|
|
24 0
|
|
|
|
|
26 0
|
|
|
|
|
28 0
|
|
|
|
|
30 0
|
|
|
|
|
32 0
|
|
|
|
|
34 0
|
|
|
|
|
36 0
|
|
|
|
|
38 0
|
|
|
|
|
40 0
|
|
|
|
|
42 0
|
|
|
|
|
44 0
|
|
|
|
|
46 0
|
|
|
|
|
48 0
|
|
|
|
|
50 0
|
|
|
|
|
52 0
|
|
|
|
|
54 0
|
|
|
|
|
56 0
|
|
|
|
|
58 0
|
|
|
|
|
60 0
|
|
|
|
|
62 0
|
|
|
|
|
64 0
|
|
|
|
|
66 0
|
|
|
|
|
68 0
|
|
|
|
|
70 0
|
|
|
|
|
72 0
|
|
|
|
|
74 0
|
|
|
|
|
76 0
|
|
|
|
|
78 0
|
|
|
|
|
80 0
|
|
|
|
|
82 0
|
|
|
|
|
84 0
|
|
|
|
|
86 0
|
|
|
|
|
88 0
|
|
|
|
|
90 0
|
|
|
|
|
92 0
|
|
|
|
|
94 0
|
|
|
|
|
96 0
|
|
|
|
|
98 0
|
|
|
|
|
system.cpu.iq.IQ:residence:IntAlu.max_value 0
|
|
|
|
|
system.cpu.iq.IQ:residence:IntAlu.end_dist
|
|
|
|
|
|
|
|
|
|
system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue
|
|
|
|
|
system.cpu.iq.IQ:residence:IntMult.samples 0
|
|
|
|
|
system.cpu.iq.IQ:residence:IntMult.min_value 0
|
|
|
|
|
0 0
|
|
|
|
|
2 0
|
|
|
|
|
4 0
|
|
|
|
|
6 0
|
|
|
|
|
8 0
|
|
|
|
|
10 0
|
|
|
|
|
12 0
|
|
|
|
|
14 0
|
|
|
|
|
16 0
|
|
|
|
|
18 0
|
|
|
|
|
20 0
|
|
|
|
|
22 0
|
|
|
|
|
24 0
|
|
|
|
|
26 0
|
|
|
|
|
28 0
|
|
|
|
|
30 0
|
|
|
|
|
32 0
|
|
|
|
|
34 0
|
|
|
|
|
36 0
|
|
|
|
|
38 0
|
|
|
|
|
40 0
|
|
|
|
|
42 0
|
|
|
|
|
44 0
|
|
|
|
|
46 0
|
|
|
|
|
48 0
|
|
|
|
|
50 0
|
|
|
|
|
52 0
|
|
|
|
|
54 0
|
|
|
|
|
56 0
|
|
|
|
|
58 0
|
|
|
|
|
60 0
|
|
|
|
|
62 0
|
|
|
|
|
64 0
|
|
|
|
|
66 0
|
|
|
|
|
68 0
|
|
|
|
|
70 0
|
|
|
|
|
72 0
|
|
|
|
|
74 0
|
|
|
|
|
76 0
|
|
|
|
|
78 0
|
|
|
|
|
80 0
|
|
|
|
|
82 0
|
|
|
|
|
84 0
|
|
|
|
|
86 0
|
|
|
|
|
88 0
|
|
|
|
|
90 0
|
|
|
|
|
92 0
|
|
|
|
|
94 0
|
|
|
|
|
96 0
|
|
|
|
|
98 0
|
|
|
|
|
system.cpu.iq.IQ:residence:IntMult.max_value 0
|
|
|
|
|
system.cpu.iq.IQ:residence:IntMult.end_dist
|
|
|
|
|
|
|
|
|
|
system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue
|
|
|
|
|
system.cpu.iq.IQ:residence:IntDiv.samples 0
|
|
|
|
|
system.cpu.iq.IQ:residence:IntDiv.min_value 0
|
|
|
|
|
0 0
|
|
|
|
|
2 0
|
|
|
|
|
4 0
|
|
|
|
|
6 0
|
|
|
|
|
8 0
|
|
|
|
|
10 0
|
|
|
|
|
12 0
|
|
|
|
|
14 0
|
|
|
|
|
16 0
|
|
|
|
|
18 0
|
|
|
|
|
20 0
|
|
|
|
|
22 0
|
|
|
|
|
24 0
|
|
|
|
|
26 0
|
|
|
|
|
28 0
|
|
|
|
|
30 0
|
|
|
|
|
32 0
|
|
|
|
|
34 0
|
|
|
|
|
36 0
|
|
|
|
|
38 0
|
|
|
|
|
40 0
|
|
|
|
|
42 0
|
|
|
|
|
44 0
|
|
|
|
|
46 0
|
|
|
|
|
48 0
|
|
|
|
|
50 0
|
|
|
|
|
52 0
|
|
|
|
|
54 0
|
|
|
|
|
56 0
|
|
|
|
|
58 0
|
|
|
|
|
60 0
|
|
|
|
|
62 0
|
|
|
|
|
64 0
|
|
|
|
|
66 0
|
|
|
|
|
68 0
|
|
|
|
|
70 0
|
|
|
|
|
72 0
|
|
|
|
|
74 0
|
|
|
|
|
76 0
|
|
|
|
|
78 0
|
|
|
|
|
80 0
|
|
|
|
|
82 0
|
|
|
|
|
84 0
|
|
|
|
|
86 0
|
|
|
|
|
88 0
|
|
|
|
|
90 0
|
|
|
|
|
92 0
|
|
|
|
|
94 0
|
|
|
|
|
96 0
|
|
|
|
|
98 0
|
|
|
|
|
system.cpu.iq.IQ:residence:IntDiv.max_value 0
|
|
|
|
|
system.cpu.iq.IQ:residence:IntDiv.end_dist
|
|
|
|
|
|
|
|
|
|
system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue
|
|
|
|
|
system.cpu.iq.IQ:residence:FloatAdd.samples 0
|
|
|
|
|
system.cpu.iq.IQ:residence:FloatAdd.min_value 0
|
|
|
|
|
0 0
|
|
|
|
|
2 0
|
|
|
|
|
4 0
|
|
|
|
|
6 0
|
|
|
|
|
8 0
|
|
|
|
|
10 0
|
|
|
|
|
12 0
|
|
|
|
|
14 0
|
|
|
|
|
16 0
|
|
|
|
|
18 0
|
|
|
|
|
20 0
|
|
|
|
|
22 0
|
|
|
|
|
24 0
|
|
|
|
|
26 0
|
|
|
|
|
28 0
|
|
|
|
|
30 0
|
|
|
|
|
32 0
|
|
|
|
|
34 0
|
|
|
|
|
36 0
|
|
|
|
|
38 0
|
|
|
|
|
40 0
|
|
|
|
|
42 0
|
|
|
|
|
44 0
|
|
|
|
|
46 0
|
|
|
|
|
48 0
|
|
|
|
|
50 0
|
|
|
|
|
52 0
|
|
|
|
|
54 0
|
|
|
|
|
56 0
|
|
|
|
|
58 0
|
|
|
|
|
60 0
|
|
|
|
|
62 0
|
|
|
|
|
64 0
|
|
|
|
|
66 0
|
|
|
|
|
68 0
|
|
|
|
|
70 0
|
|
|
|
|
72 0
|
|
|
|
|
74 0
|
|
|
|
|
76 0
|
|
|
|
|
78 0
|
|
|
|
|
80 0
|
|
|
|
|
82 0
|
|
|
|
|
84 0
|
|
|
|
|
86 0
|
|
|
|
|
88 0
|
|
|
|
|
90 0
|
|
|
|
|
92 0
|
|
|
|
|
94 0
|
|
|
|
|
96 0
|
|
|
|
|
98 0
|
|
|
|
|
system.cpu.iq.IQ:residence:FloatAdd.max_value 0
|
|
|
|
|
system.cpu.iq.IQ:residence:FloatAdd.end_dist
|
|
|
|
|
|
|
|
|
|
system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue
|
|
|
|
|
system.cpu.iq.IQ:residence:FloatCmp.samples 0
|
|
|
|
|
system.cpu.iq.IQ:residence:FloatCmp.min_value 0
|
|
|
|
|
0 0
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92 0
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94 0
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96 0
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98 0
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system.cpu.iq.IQ:residence:FloatCmp.max_value 0
|
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|
system.cpu.iq.IQ:residence:FloatCmp.end_dist
|
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system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue
|
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|
|
system.cpu.iq.IQ:residence:FloatCvt.samples 0
|
|
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|
system.cpu.iq.IQ:residence:FloatCvt.min_value 0
|
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0 0
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2 0
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4 0
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92 0
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94 0
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96 0
|
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98 0
|
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system.cpu.iq.IQ:residence:FloatCvt.max_value 0
|
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|
system.cpu.iq.IQ:residence:FloatCvt.end_dist
|
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|
system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue
|
|
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|
|
system.cpu.iq.IQ:residence:FloatMult.samples 0
|
|
|
|
|
system.cpu.iq.IQ:residence:FloatMult.min_value 0
|
|
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|
0 0
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2 0
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4 0
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6 0
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76 0
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78 0
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80 0
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82 0
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84 0
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86 0
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88 0
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90 0
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92 0
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94 0
|
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96 0
|
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98 0
|
|
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|
system.cpu.iq.IQ:residence:FloatMult.max_value 0
|
|
|
|
|
system.cpu.iq.IQ:residence:FloatMult.end_dist
|
|
|
|
|
|
|
|
|
|
system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue
|
|
|
|
|
system.cpu.iq.IQ:residence:FloatDiv.samples 0
|
|
|
|
|
system.cpu.iq.IQ:residence:FloatDiv.min_value 0
|
|
|
|
|
0 0
|
|
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2 0
|
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4 0
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6 0
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8 0
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10 0
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12 0
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14 0
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42 0
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44 0
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46 0
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48 0
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50 0
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52 0
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54 0
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56 0
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58 0
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60 0
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62 0
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64 0
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66 0
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68 0
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70 0
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72 0
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74 0
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76 0
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78 0
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80 0
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82 0
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84 0
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86 0
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88 0
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90 0
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92 0
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94 0
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96 0
|
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98 0
|
|
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|
|
system.cpu.iq.IQ:residence:FloatDiv.max_value 0
|
|
|
|
|
system.cpu.iq.IQ:residence:FloatDiv.end_dist
|
|
|
|
|
|
|
|
|
|
system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue
|
|
|
|
|
system.cpu.iq.IQ:residence:FloatSqrt.samples 0
|
|
|
|
|
system.cpu.iq.IQ:residence:FloatSqrt.min_value 0
|
|
|
|
|
0 0
|
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2 0
|
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4 0
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6 0
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48 0
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50 0
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52 0
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54 0
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56 0
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58 0
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60 0
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62 0
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64 0
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66 0
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68 0
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70 0
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72 0
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74 0
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76 0
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78 0
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80 0
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82 0
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84 0
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86 0
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88 0
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90 0
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92 0
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94 0
|
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|
96 0
|
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|
98 0
|
|
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|
|
system.cpu.iq.IQ:residence:FloatSqrt.max_value 0
|
|
|
|
|
system.cpu.iq.IQ:residence:FloatSqrt.end_dist
|
|
|
|
|
|
|
|
|
|
system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue
|
|
|
|
|
system.cpu.iq.IQ:residence:MemRead.samples 0
|
|
|
|
|
system.cpu.iq.IQ:residence:MemRead.min_value 0
|
|
|
|
|
0 0
|
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2 0
|
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4 0
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6 0
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8 0
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12 0
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62 0
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66 0
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68 0
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70 0
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72 0
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74 0
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76 0
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78 0
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80 0
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82 0
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84 0
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86 0
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88 0
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90 0
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92 0
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94 0
|
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|
96 0
|
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|
98 0
|
|
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|
|
system.cpu.iq.IQ:residence:MemRead.max_value 0
|
|
|
|
|
system.cpu.iq.IQ:residence:MemRead.end_dist
|
|
|
|
|
|
|
|
|
|
system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue
|
|
|
|
|
system.cpu.iq.IQ:residence:MemWrite.samples 0
|
|
|
|
|
system.cpu.iq.IQ:residence:MemWrite.min_value 0
|
|
|
|
|
0 0
|
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2 0
|
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4 0
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6 0
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10 0
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12 0
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14 0
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16 0
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18 0
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44 0
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48 0
|
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50 0
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52 0
|
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54 0
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56 0
|
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58 0
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60 0
|
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62 0
|
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64 0
|
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66 0
|
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68 0
|
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70 0
|
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72 0
|
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74 0
|
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76 0
|
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78 0
|
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80 0
|
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82 0
|
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84 0
|
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86 0
|
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88 0
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90 0
|
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92 0
|
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|
94 0
|
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|
|
96 0
|
|
|
|
|
98 0
|
|
|
|
|
system.cpu.iq.IQ:residence:MemWrite.max_value 0
|
|
|
|
|
system.cpu.iq.IQ:residence:MemWrite.end_dist
|
|
|
|
|
|
|
|
|
|
system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue
|
|
|
|
|
system.cpu.iq.IQ:residence:IprAccess.samples 0
|
|
|
|
|
system.cpu.iq.IQ:residence:IprAccess.min_value 0
|
|
|
|
|
0 0
|
|
|
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|
2 0
|
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|
4 0
|
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6 0
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8 0
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10 0
|
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12 0
|
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14 0
|
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|
16 0
|
|
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|
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system.cpu.iq.IQ:residence:IprAccess.max_value 0
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system.cpu.iq.IQ:residence:IprAccess.end_dist
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system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue
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system.cpu.iq.IQ:residence:InstPrefetch.samples 0
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system.cpu.iq.IQ:residence:InstPrefetch.min_value 0
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system.cpu.iq.IQ:residence:InstPrefetch.max_value 0
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system.cpu.iq.IQ:residence:InstPrefetch.end_dist
|
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system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue
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system.cpu.iq.ISSUE:(null)_delay.samples 0
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system.cpu.iq.ISSUE:(null)_delay.min_value 0
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system.cpu.iq.ISSUE:(null)_delay.max_value 0
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system.cpu.iq.ISSUE:(null)_delay.end_dist
|
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system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue
|
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|
system.cpu.iq.ISSUE:IntAlu_delay.samples 0
|
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system.cpu.iq.ISSUE:IntAlu_delay.min_value 0
|
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0 0
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2 0
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96 0
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98 0
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system.cpu.iq.ISSUE:IntAlu_delay.max_value 0
|
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|
system.cpu.iq.ISSUE:IntAlu_delay.end_dist
|
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system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue
|
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|
system.cpu.iq.ISSUE:IntMult_delay.samples 0
|
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system.cpu.iq.ISSUE:IntMult_delay.min_value 0
|
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0 0
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2 0
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94 0
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96 0
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98 0
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system.cpu.iq.ISSUE:IntMult_delay.max_value 0
|
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|
|
system.cpu.iq.ISSUE:IntMult_delay.end_dist
|
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|
|
system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue
|
|
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|
|
system.cpu.iq.ISSUE:IntDiv_delay.samples 0
|
|
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|
|
system.cpu.iq.ISSUE:IntDiv_delay.min_value 0
|
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0 0
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2 0
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94 0
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96 0
|
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98 0
|
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|
system.cpu.iq.ISSUE:IntDiv_delay.max_value 0
|
|
|
|
|
system.cpu.iq.ISSUE:IntDiv_delay.end_dist
|
|
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|
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|
|
system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue
|
|
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|
|
system.cpu.iq.ISSUE:FloatAdd_delay.samples 0
|
|
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|
|
system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0
|
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0 0
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2 0
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4 0
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94 0
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96 0
|
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98 0
|
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|
|
system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0
|
|
|
|
|
system.cpu.iq.ISSUE:FloatAdd_delay.end_dist
|
|
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|
|
|
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|
|
system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue
|
|
|
|
|
system.cpu.iq.ISSUE:FloatCmp_delay.samples 0
|
|
|
|
|
system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0
|
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0 0
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2 0
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34 0
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system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0
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system.cpu.iq.ISSUE:FloatCmp_delay.end_dist
|
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system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue
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system.cpu.iq.ISSUE:FloatCvt_delay.samples 0
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system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0
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system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0
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system.cpu.iq.ISSUE:FloatCvt_delay.end_dist
|
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system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue
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system.cpu.iq.ISSUE:FloatMult_delay.samples 0
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system.cpu.iq.ISSUE:FloatMult_delay.min_value 0
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system.cpu.iq.ISSUE:FloatMult_delay.max_value 0
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system.cpu.iq.ISSUE:FloatMult_delay.end_dist
|
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system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue
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system.cpu.iq.ISSUE:FloatDiv_delay.samples 0
|
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system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0
|
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0 0
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system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0
|
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system.cpu.iq.ISSUE:FloatDiv_delay.end_dist
|
|
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system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue
|
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|
system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0
|
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system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0
|
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0 0
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98 0
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system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0
|
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|
system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist
|
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|
system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue
|
|
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|
|
system.cpu.iq.ISSUE:MemRead_delay.samples 0
|
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|
system.cpu.iq.ISSUE:MemRead_delay.min_value 0
|
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0 0
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2 0
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96 0
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98 0
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system.cpu.iq.ISSUE:MemRead_delay.max_value 0
|
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|
|
system.cpu.iq.ISSUE:MemRead_delay.end_dist
|
|
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|
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|
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|
|
system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue
|
|
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|
|
system.cpu.iq.ISSUE:MemWrite_delay.samples 0
|
|
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|
|
system.cpu.iq.ISSUE:MemWrite_delay.min_value 0
|
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0 0
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2 0
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96 0
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98 0
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|
system.cpu.iq.ISSUE:MemWrite_delay.max_value 0
|
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|
|
system.cpu.iq.ISSUE:MemWrite_delay.end_dist
|
|
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|
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|
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|
|
system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue
|
|
|
|
|
system.cpu.iq.ISSUE:IprAccess_delay.samples 0
|
|
|
|
|
system.cpu.iq.ISSUE:IprAccess_delay.min_value 0
|
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0 0
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52 0
|
|
|
|
|
54 0
|
|
|
|
|
56 0
|
|
|
|
|
58 0
|
|
|
|
|
60 0
|
|
|
|
|
62 0
|
|
|
|
|
64 0
|
|
|
|
|
66 0
|
|
|
|
|
68 0
|
|
|
|
|
70 0
|
|
|
|
|
72 0
|
|
|
|
|
74 0
|
|
|
|
|
76 0
|
|
|
|
|
78 0
|
|
|
|
|
80 0
|
|
|
|
|
82 0
|
|
|
|
|
84 0
|
|
|
|
|
86 0
|
|
|
|
|
88 0
|
|
|
|
|
90 0
|
|
|
|
|
92 0
|
|
|
|
|
94 0
|
|
|
|
|
96 0
|
|
|
|
|
98 0
|
|
|
|
|
system.cpu.iq.ISSUE:IprAccess_delay.max_value 0
|
|
|
|
|
system.cpu.iq.ISSUE:IprAccess_delay.end_dist
|
|
|
|
|
|
|
|
|
|
system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue
|
|
|
|
|
system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0
|
|
|
|
|
system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0
|
|
|
|
|
0 0
|
|
|
|
|
2 0
|
|
|
|
|
4 0
|
|
|
|
|
6 0
|
|
|
|
|
8 0
|
|
|
|
|
10 0
|
|
|
|
|
12 0
|
|
|
|
|
14 0
|
|
|
|
|
16 0
|
|
|
|
|
18 0
|
|
|
|
|
20 0
|
|
|
|
|
22 0
|
|
|
|
|
24 0
|
|
|
|
|
26 0
|
|
|
|
|
28 0
|
|
|
|
|
30 0
|
|
|
|
|
32 0
|
|
|
|
|
34 0
|
|
|
|
|
36 0
|
|
|
|
|
38 0
|
|
|
|
|
40 0
|
|
|
|
|
42 0
|
|
|
|
|
44 0
|
|
|
|
|
46 0
|
|
|
|
|
48 0
|
|
|
|
|
50 0
|
|
|
|
|
52 0
|
|
|
|
|
54 0
|
|
|
|
|
56 0
|
|
|
|
|
58 0
|
|
|
|
|
60 0
|
|
|
|
|
62 0
|
|
|
|
|
64 0
|
|
|
|
|
66 0
|
|
|
|
|
68 0
|
|
|
|
|
70 0
|
|
|
|
|
72 0
|
|
|
|
|
74 0
|
|
|
|
|
76 0
|
|
|
|
|
78 0
|
|
|
|
|
80 0
|
|
|
|
|
82 0
|
|
|
|
|
84 0
|
|
|
|
|
86 0
|
|
|
|
|
88 0
|
|
|
|
|
90 0
|
|
|
|
|
92 0
|
|
|
|
|
94 0
|
|
|
|
|
96 0
|
|
|
|
|
98 0
|
|
|
|
|
system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0
|
|
|
|
|
system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist
|
|
|
|
|
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
|
|
|
|
(null) 2 0.02% # Type of FU issued
|
|
|
|
|
IntAlu 5594 66.69% # Type of FU issued
|
|
|
|
|
IntMult 1 0.01% # Type of FU issued
|
|
|
|
|
IntDiv 0 0.00% # Type of FU issued
|
|
|
|
|
FloatAdd 2 0.02% # Type of FU issued
|
|
|
|
|
FloatCmp 0 0.00% # Type of FU issued
|
|
|
|
|
FloatCvt 0 0.00% # Type of FU issued
|
|
|
|
|
FloatMult 0 0.00% # Type of FU issued
|
|
|
|
|
FloatDiv 0 0.00% # Type of FU issued
|
|
|
|
|
FloatSqrt 0 0.00% # Type of FU issued
|
|
|
|
|
MemRead 1757 20.95% # Type of FU issued
|
|
|
|
|
MemWrite 1032 12.30% # Type of FU issued
|
|
|
|
|
IprAccess 0 0.00% # Type of FU issued
|
|
|
|
|
InstPrefetch 0 0.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
|
|
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested
|
|
|
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full.start_dist
|
|
|
|
|
(null) 0 0.00% # attempts to use FU when none available
|
|
|
|
|
IntAlu 1 0.87% # attempts to use FU when none available
|
|
|
|
|
IntMult 0 0.00% # attempts to use FU when none available
|
|
|
|
|
IntDiv 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatAdd 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatCmp 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatCvt 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatMult 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatDiv 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatSqrt 0 0.00% # attempts to use FU when none available
|
|
|
|
|
MemRead 76 66.09% # attempts to use FU when none available
|
|
|
|
|
MemWrite 38 33.04% # attempts to use FU when none available
|
|
|
|
|
IprAccess 0 0.00% # attempts to use FU when none available
|
|
|
|
|
InstPrefetch 0 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full.end_dist
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.samples 6871
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
|
|
|
|
0 3753 5462.09%
|
|
|
|
|
1 894 1301.12%
|
|
|
|
|
2 723 1052.25%
|
|
|
|
|
3 614 893.61%
|
|
|
|
|
4 451 656.38%
|
|
|
|
|
5 279 406.05%
|
|
|
|
|
6 104 151.36%
|
|
|
|
|
7 41 59.67%
|
|
|
|
|
8 12 17.46%
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
|
|
|
|
|
|
|
|
|
system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate
|
|
|
|
|
system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued
|
|
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ
|
|
|
|
|
system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed
|
|
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.overall_hits 2 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_misses 497 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
|
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
|
|
|
system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
|
|
|
|
system.cpu.numCycles 6871 # number of cpu cycles simulated
|
|
|
|
|
system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking
|
|
|
|
|
system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed
|
|
|
|
|
system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full
|
|
|
|
|
system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed
|
|
|
|
|
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
|
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
