2006-10-12 21:04:14 +02:00
|
|
|
|
|
|
|
|
---------- Begin Simulation Statistics ----------
|
|
|
|
|
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
2007-08-13 01:43:55 +02:00
|
|
|
global.BPredUnit.BTBHits 7542290 # Number of BTB hits
|
|
|
|
|
global.BPredUnit.BTBLookups 13308941 # Number of BTB lookups
|
|
|
|
|
global.BPredUnit.RASInCorrect 34250 # Number of incorrect RAS predictions.
|
|
|
|
|
global.BPredUnit.condIncorrect 454073 # Number of conditional branches incorrect
|
|
|
|
|
global.BPredUnit.condPredicted 9847799 # Number of conditional branches predicted
|
|
|
|
|
global.BPredUnit.lookups 15155323 # Number of BP lookups
|
|
|
|
|
global.BPredUnit.usedRAS 1795531 # Number of times the RAS was used to get a target.
|
|
|
|
|
host_inst_rate 196409 # Simulator instruction rate (inst/s)
|
|
|
|
|
host_mem_usage 211144 # Number of bytes of host memory used
|
|
|
|
|
host_seconds 405.24 # Real time elapsed on the host
|
|
|
|
|
host_tick_rate 57107000 # Simulator tick rate (ticks/s)
|
|
|
|
|
memdepunit.memDep.conflictingLoads 11563356 # Number of conflicting loads.
|
|
|
|
|
memdepunit.memDep.conflictingStores 10718994 # Number of conflicting stores.
|
|
|
|
|
memdepunit.memDep.insertedLoads 21578903 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
memdepunit.memDep.insertedStores 15738647 # Number of stores inserted to the mem dependence unit.
|
2006-10-12 21:04:14 +02:00
|
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
2007-02-14 19:05:20 +01:00
|
|
|
sim_insts 79591756 # Number of instructions simulated
|
2007-08-13 01:43:55 +02:00
|
|
|
sim_seconds 0.023142 # Number of seconds simulated
|
|
|
|
|
sim_ticks 23141799000 # Number of ticks simulated
|
2007-02-14 19:05:20 +01:00
|
|
|
system.cpu.commit.COM:branches 13754477 # Number of branches committed
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.commit.COM:bw_lim_events 3510282 # number cycles where commit BW limit reached
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
|
|
|
|
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle.samples 45393667
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle.min_value 0
|
2007-08-13 01:43:55 +02:00
|
|
|
0 16854505 3712.96%
|
|
|
|
|
1 10816662 2382.86%
|
|
|
|
|
2 5010201 1103.72%
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|
|
|
|
3 3353080 738.67%
|
|
|
|
|
4 2515867 554.23%
|
|
|
|
|
5 1511689 333.02%
|
|
|
|
|
6 1009468 222.38%
|
|
|
|
|
7 811913 178.86%
|
|
|
|
|
8 3510282 773.30%
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle.max_value 8
|
|
|
|
|
system.cpu.commit.COM:committed_per_cycle.end_dist
|
|
|
|
|
|
2007-02-14 19:05:20 +01:00
|
|
|
system.cpu.commit.COM:count 88340672 # Number of instructions committed
|
|
|
|
|
system.cpu.commit.COM:loads 20379399 # Number of loads committed
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
2007-02-14 19:05:20 +01:00
|
|
|
system.cpu.commit.COM:refs 35224018 # Number of memory references committed
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.commit.branchMispredicts 357583 # The number of times a branch was mispredicted
|
2007-02-14 19:05:20 +01:00
|
|
|
system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions
|
|
|
|
|
system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.commit.commitSquashedInsts 5444219 # The number of squashed insts skipped by commit
|
2007-02-14 19:05:20 +01:00
|
|
|
system.cpu.committedInsts 79591756 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.cpi 0.581499 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 0.581499 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_accesses 43 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits 43 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 19849413 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 15478.106634 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4237.239017 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 19787819 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 953358500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.003103 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses 61594 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 85223 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 260988500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.003103 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 61594 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses 13805554 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 30519.673214 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5295.405245 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_hits 13655731 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency 4572549000 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.010852 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 149823 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 807823 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 793373500 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.010852 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 149823 # number of WriteReq MSHR misses
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.dcache.avg_refs 163.116342 # Average number of references to valid blocks.
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.dcache.demand_accesses 33654967 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency 26137.479484 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 4987.120241 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_hits 33443550 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_miss_latency 5525907500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_rate 0.006282 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_misses 211417 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits 893046 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 1054362000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.006282 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses 211417 # number of demand (read+write) MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.dcache.overall_accesses 33654967 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 26137.479484 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 4987.120241 # average overall mshr miss latency
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.dcache.overall_hits 33443550 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 5525907500 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.006282 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_misses 211417 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 893046 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 1054362000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.006282 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 211417 # number of overall MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.dcache.replacements 200972 # number of replacements
|
|
|
|
|
system.cpu.dcache.sampled_refs 205068 # Sample count of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.dcache.tagsinuse 4079.963353 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 33449942 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.warmup_cycle 119008000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.writebacks 147761 # number of writebacks
|
|
|
|
|
system.cpu.decode.DECODE:BlockedCycles 971695 # Number of cycles decode is blocked
|
|
|
|
|
system.cpu.decode.DECODE:BranchMispred 97371 # Number of times decode detected a branch misprediction
|
|
|
|
|
system.cpu.decode.DECODE:BranchResolved 3417858 # Number of times decode resolved a branch
|
|
|
|
|
system.cpu.decode.DECODE:DecodedInsts 96162354 # Number of instructions handled by decode
|
|
|
|
|
system.cpu.decode.DECODE:IdleCycles 25952342 # Number of cycles decode is idle
|
|
|
|
|
system.cpu.decode.DECODE:RunCycles 18439987 # Number of cycles decode is running
|
|
|
|
|
system.cpu.decode.DECODE:SquashCycles 888885 # Number of cycles decode is squashing
|
|
|
|
|
system.cpu.decode.DECODE:SquashedInsts 288762 # Number of squashed instructions handled by decode
|
|
|
|
|
system.cpu.decode.DECODE:UnblockCycles 29644 # Number of cycles decode is unblocking
|
|
|
|
|
system.cpu.fetch.Branches 15155323 # Number of branches that fetch encountered
|
|
|
|
|
system.cpu.fetch.CacheLines 12535185 # Number of cache lines fetched
|
|
|
|
|
system.cpu.fetch.Cycles 31179449 # Number of cycles fetch has run and was not squashing or blocked
|
|
|
|
|
system.cpu.fetch.IcacheSquashes 131701 # Number of outstanding Icache misses that were squashed
|
|
|
|
|
system.cpu.fetch.Insts 97686537 # Number of instructions fetch has processed
|
|
|
|
|
system.cpu.fetch.SquashCycles 470452 # Number of cycles fetch has spent squashing
|
|
|
|
|
system.cpu.fetch.branchRate 0.327452 # Number of branch fetches per cycle
|
|
|
|
|
system.cpu.fetch.icacheStallCycles 12535185 # Number of cycles fetch is stalled on an Icache miss
|
|
|
|
|
system.cpu.fetch.predictedBranches 9337821 # Number of branches that fetch has predicted taken
|
|
|
|
|
system.cpu.fetch.rate 2.110656 # Number of inst fetches per cycle
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.fetch.rateDist.samples 46282553
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.fetch.rateDist.min_value 0
|
2007-08-13 01:43:55 +02:00
|
|
|
0 27638291 5971.64%
|
|
|
|
|
1 1733920 374.64%
|
|
|
|
|
2 1408099 304.24%
|
|
|
|
|
3 1707036 368.83%
|
|
|
|
|
4 3689148 797.09%
|
|
|
|
|
5 1739866 375.92%
|
|
|
|
|
6 655334 141.59%
|
|
|
|
|
7 1059487 228.92%
|
|
|
|
|
8 6651372 1437.12%
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.fetch.rateDist.max_value 8
|
|
|
|
|
system.cpu.fetch.rateDist.end_dist
|
|
|
|
|
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.icache.ReadReq_accesses 12534294 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 4593.252212 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2552.911039 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_hits 12448414 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 394468500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.006852 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_misses 85880 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits 891 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 219244000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.006852 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 85880 # number of ReadReq MSHR misses
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.icache.avg_refs 144.958009 # Average number of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.icache.demand_accesses 12534294 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 4593.252212 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 2552.911039 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_hits 12448414 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_miss_latency 394468500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.006852 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_misses 85880 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 891 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 219244000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.006852 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 85880 # number of demand (read+write) MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.icache.overall_accesses 12534294 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 4593.252212 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 2552.911039 # average overall mshr miss latency
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.icache.overall_hits 12448414 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_miss_latency 394468500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.006852 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_misses 85880 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 891 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 219244000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.006852 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 85880 # number of overall MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.icache.replacements 83828 # number of replacements
|
|
|
|
|
system.cpu.icache.sampled_refs 85876 # Sample count of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.icache.tagsinuse 1919.939531 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 12448414 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.warmup_cycle 20180672000 # Cycle when the warmup percentage was hit.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.idleCycles 779486 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.iew.EXEC:branches 14215317 # Number of branches executed
|
|
|
|
|
system.cpu.iew.EXEC:nop 9054056 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.EXEC:rate 1.776804 # Inst execution rate
|
|
|
|
|
system.cpu.iew.EXEC:refs 36085022 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.EXEC:stores 15098216 # Number of stores executed
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.iew.WB:consumers 41423091 # num instructions consuming a value
|
|
|
|
|
system.cpu.iew.WB:count 81970056 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.WB:fanout 0.763712 # average fanout of values written-back
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.iew.WB:producers 31635305 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.WB:rate 1.771079 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.WB:sent 82027383 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.branchMispredicts 388269 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewBlockCycles 17461 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 21578903 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 4692 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 341214 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 15738647 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 93782111 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 20986806 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 455724 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 82235016 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 2252 # Number of times the IQ has become full, causing a stall
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.iew.iewLSQFullEvents 122 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewSquashCycles 888885 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 3197 # Number of cycles IEW is unblocking
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
|
|
|
system.cpu.iew.lsq.thread.0.forwLoads 937737 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 950 # Number of memory responses ignored because the instruction is squashed
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 19015 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 1226 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 1199504 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedStores 894028 # Number of stores squashed
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 19015 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 105591 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 282678 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.ipc 1.719692 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.719692 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0 82690740 # Type of FU issued
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
2007-08-13 01:43:55 +02:00
|
|
|
No_OpClass 0 0.00% # Type of FU issued
|
|
|
|
|
IntAlu 46107608 55.76% # Type of FU issued
|
|
|
|
|
IntMult 43061 0.05% # Type of FU issued
|
2006-10-12 21:04:14 +02:00
|
|
|
IntDiv 0 0.00% # Type of FU issued
|
2007-08-13 01:43:55 +02:00
|
|
|
FloatAdd 119602 0.14% # Type of FU issued
|
2007-04-27 20:35:58 +02:00
|
|
|
FloatCmp 87 0.00% # Type of FU issued
|
2007-08-13 01:43:55 +02:00
|
|
|
FloatCvt 120853 0.15% # Type of FU issued
|
2007-04-27 20:35:58 +02:00
|
|
|
FloatMult 50 0.00% # Type of FU issued
|
2007-08-13 01:43:55 +02:00
|
|
|
FloatDiv 37774 0.05% # Type of FU issued
|
2006-10-12 21:04:14 +02:00
|
|
|
FloatSqrt 0 0.00% # Type of FU issued
|
2007-08-13 01:43:55 +02:00
|
|
|
MemRead 21079728 25.49% # Type of FU issued
|
|
|
|
|
MemWrite 15181977 18.36% # Type of FU issued
|
2006-10-12 21:04:14 +02:00
|
|
|
IprAccess 0 0.00% # Type of FU issued
|
|
|
|
|
InstPrefetch 0 0.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 974009 # FU busy when requested
|
|
|
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.011779 # FU busy rate (busy events/executed inst)
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_full.start_dist
|
2007-08-13 01:43:55 +02:00
|
|
|
No_OpClass 0 0.00% # attempts to use FU when none available
|
|
|
|
|
IntAlu 90058 9.25% # attempts to use FU when none available
|
2006-10-12 21:04:14 +02:00
|
|
|
IntMult 0 0.00% # attempts to use FU when none available
|
|
|
|
|
IntDiv 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatAdd 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatCmp 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatCvt 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatMult 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatDiv 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatSqrt 0 0.00% # attempts to use FU when none available
|
2007-08-13 01:43:55 +02:00
|
|
|
MemRead 437339 44.90% # attempts to use FU when none available
|
|
|
|
|
MemWrite 446612 45.85% # attempts to use FU when none available
|
2006-10-12 21:04:14 +02:00
|
|
|
IprAccess 0 0.00% # attempts to use FU when none available
|
|
|
|
|
InstPrefetch 0 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full.end_dist
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.samples 46282553
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
2007-08-13 01:43:55 +02:00
|
|
|
0 12550048 2711.62%
|
|
|
|
|
1 12875827 2782.00%
|
|
|
|
|
2 7785024 1682.06%
|
|
|
|
|
3 4673558 1009.79%
|
|
|
|
|
4 4500672 972.43%
|
|
|
|
|
5 2074677 448.26%
|
|
|
|
|
6 1137561 245.79%
|
|
|
|
|
7 458736 99.12%
|
|
|
|
|
8 226450 48.93%
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
|
|
|
|
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.iq.ISSUE:rate 1.786650 # Inst issue rate
|
|
|
|
|
system.cpu.iq.iqInstsAdded 84723363 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqInstsIssued 82690740 # Number of instructions issued
|
|
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 4692 # Number of non-speculative instructions added to the IQ
|
|
|
|
|
system.cpu.iq.iqSquashedInstsExamined 4940751 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 53730 # Number of squashed instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 109 # Number of squashed non-spec instructions that were removed
|
|
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 3594449 # Number of squashed operands that are examined and possibly removed from graph
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses 143476 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 4086.446514 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2086.446514 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 586307000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 143476 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 299355000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 143476 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 147467 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 4144.894478 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2144.894478 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 98804 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 201703000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.329992 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 48663 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 104377000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.329992 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 48663 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses 6368 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 4226.366206 # average UpgradeReq miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2231.626884 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_latency 26913500 # number of UpgradeReq miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses 6368 # number of UpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14211000 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 6368 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 147761 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
|
|
|
|
|
system.cpu.l2cache.Writeback_misses 147761 # number of Writeback misses
|
|
|
|
|
system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
|
|
|
|
|
system.cpu.l2cache.Writeback_mshr_misses 147761 # number of Writeback MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.l2cache.avg_refs 2.459748 # Average number of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.l2cache.demand_accesses 290943 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 4101.249616 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 2101.249616 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_hits 98804 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 788010000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.660401 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_misses 192139 # number of demand (read+write) misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 403732000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.660401 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 192139 # number of demand (read+write) MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.l2cache.overall_accesses 290943 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 4101.249616 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 2101.249616 # average overall mshr miss latency
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.l2cache.overall_hits 98804 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 788010000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.660401 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_misses 192139 # number of overall misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 403732000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.660401 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 192139 # number of overall MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.l2cache.replacements 25941 # number of replacements
|
|
|
|
|
system.cpu.l2cache.sampled_refs 41849 # Sample count of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 4585.524484 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 102938 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
|
|
|
|
system.cpu.numCycles 46282553 # number of cpu cycles simulated
|
|
|
|
|
system.cpu.rename.RENAME:BlockCycles 249890 # Number of cycles rename is blocking
|
2007-02-14 19:05:20 +01:00
|
|
|
system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.rename.RENAME:IQFullEvents 36341 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu.rename.RENAME:IdleCycles 26244762 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.RENAME:LSQFullEvents 565515 # Number of times rename has blocked due to LSQ full
|
|
|
|
|
system.cpu.rename.RENAME:RenameLookups 115161809 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.RENAME:RenamedInsts 95469817 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.RENAME:RenamedOperands 57208765 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RENAME:RunCycles 18176186 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.RENAME:SquashCycles 888885 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.RENAME:UnblockCycles 649163 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.RENAME:UndoneMaps 4661884 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.RENAME:serializeStallCycles 73667 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.RENAME:serializingInsts 4695 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.RENAME:skidInsts 1420326 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu.rename.RENAME:tempSerializingInsts 4693 # count of temporary serializing insts renamed
|
|
|
|
|
system.cpu.timesIdled 518 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
2007-02-14 19:05:20 +01:00
|
|
|
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
|
2006-10-12 21:04:14 +02:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
