282 lines
10 KiB
C++
282 lines
10 KiB
C++
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/*
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* Copyright (c) 2013-2014 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Andrew Bardsley
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*/
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/**
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* @file
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*
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* The dynamic instruction and instruction/line id (sequence numbers)
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* definition for Minor. A spirited attempt is made here to not carry too
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* much on this structure.
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*/
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#ifndef __CPU_MINOR_DYN_INST_HH__
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#define __CPU_MINOR_DYN_INST_HH__
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#include <iostream>
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#include "base/refcnt.hh"
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#include "cpu/minor/buffers.hh"
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#include "cpu/inst_seq.hh"
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#include "cpu/static_inst.hh"
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#include "cpu/timing_expr.hh"
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#include "sim/faults.hh"
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namespace Minor
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{
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class MinorDynInst;
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/** MinorDynInsts are currently reference counted. */
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typedef RefCountingPtr<MinorDynInst> MinorDynInstPtr;
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/** Id for lines and instructions. This includes all the relevant sequence
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* numbers and thread ids for all stages of execution. */
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class InstId
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{
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public:
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/** First sequence numbers to use in initialisation of the pipeline and
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* to be expected on the first line/instruction issued */
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static const InstSeqNum firstStreamSeqNum = 1;
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static const InstSeqNum firstPredictionSeqNum = 1;
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static const InstSeqNum firstLineSeqNum = 1;
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static const InstSeqNum firstFetchSeqNum = 1;
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static const InstSeqNum firstExecSeqNum = 1;
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public:
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/** The thread to which this line/instruction belongs */
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ThreadID threadId;
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/** The 'stream' this instruction belongs to. Streams are interrupted
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* (and sequence numbers increased) when Execute finds it wants to
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* change the stream of instructions due to a branch. */
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InstSeqNum streamSeqNum;
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/** The predicted qualifier to stream, attached by Fetch2 as a
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* consequence of branch prediction */
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InstSeqNum predictionSeqNum;
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/** Line sequence number. This is the sequence number of the fetched
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* line from which this instruction was fetched */
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InstSeqNum lineSeqNum;
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/** Fetch sequence number. This is 0 for bubbles and an ascending
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* sequence for the stream of all fetched instructions */
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InstSeqNum fetchSeqNum;
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/** 'Execute' sequence number. These are assigned after micro-op
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* decomposition and form an ascending sequence (starting with 1) for
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* post-micro-op decomposed instructions. */
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InstSeqNum execSeqNum;
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public:
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/** Very boring default constructor */
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InstId(
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ThreadID thread_id = 0, InstSeqNum stream_seq_num = 0,
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InstSeqNum prediction_seq_num = 0, InstSeqNum line_seq_num = 0,
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InstSeqNum fetch_seq_num = 0, InstSeqNum exec_seq_num = 0) :
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threadId(thread_id), streamSeqNum(stream_seq_num),
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predictionSeqNum(prediction_seq_num), lineSeqNum(line_seq_num),
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fetchSeqNum(fetch_seq_num), execSeqNum(exec_seq_num)
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{ }
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public:
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/* Equal if the thread and last set sequence number matches */
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bool
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operator== (const InstId &rhs)
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{
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/* If any of fetch and exec sequence number are not set
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* they need to be 0, so a straight comparison is still
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* fine */
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bool ret = (threadId == rhs.threadId &&
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lineSeqNum == rhs.lineSeqNum &&
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fetchSeqNum == rhs.fetchSeqNum &&
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execSeqNum == rhs.execSeqNum);
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/* Stream and prediction *must* match if these are the same id */
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if (ret) {
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assert(streamSeqNum == rhs.streamSeqNum &&
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predictionSeqNum == rhs.predictionSeqNum);
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}
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return ret;
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}
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};
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/** Print this id in the usual slash-separated format expected by
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* MinorTrace */
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std::ostream &operator <<(std::ostream &os, const InstId &id);
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class MinorDynInst;
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/** Print a short reference to this instruction. '-' for a bubble and a
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* series of '/' separated sequence numbers for other instructions. The
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* sequence numbers will be in the order: stream, prediction, line, fetch,
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* exec with exec absent if it is 0. This is used by MinorTrace. */
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std::ostream &operator <<(std::ostream &os, const MinorDynInst &inst);
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/** Dynamic instruction for Minor.
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* MinorDynInst implements the BubbleIF interface
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* Has two separate notions of sequence number for pre/post-micro-op
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* decomposition: fetchSeqNum and execSeqNum */
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class MinorDynInst : public RefCounted
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{
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private:
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/** A prototypical bubble instruction. You must call MinorDynInst::init
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* to initialise this */
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static MinorDynInstPtr bubbleInst;
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public:
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StaticInstPtr staticInst;
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InstId id;
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/** Trace information for this instruction's execution */
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Trace::InstRecord *traceData;
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/** The fetch address of this instruction */
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TheISA::PCState pc;
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/** This is actually a fault masquerading as an instruction */
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Fault fault;
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/** Tried to predict the destination of this inst (if a control
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* instruction or a sys call) */
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bool triedToPredict;
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/** This instruction was predicted to change control flow and
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* the following instructions will have a newer predictionSeqNum */
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bool predictedTaken;
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/** Predicted branch target */
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TheISA::PCState predictedTarget;
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/** Fields only set during execution */
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/** FU this instruction is issued to */
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unsigned int fuIndex;
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/** This instruction is in the LSQ, not a functional unit */
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bool inLSQ;
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/** The instruction has been sent to the store buffer */
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bool inStoreBuffer;
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/** Can this instruction be executed out of order. In this model,
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* this only happens with mem refs that need to be issued early
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* to allow other instructions to fill the fetch delay */
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bool canEarlyIssue;
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/** execSeqNum of the latest inst on which this inst depends.
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* This can be used as a sanity check for dependency ordering
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* where slightly out of order execution is required (notably
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* initiateAcc for memory ops) */
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InstSeqNum instToWaitFor;
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/** Extra delay at the end of the pipeline */
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Cycles extraCommitDelay;
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TimingExpr *extraCommitDelayExpr;
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/** Once issued, extraCommitDelay becomes minimumCommitCycle
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* to account for delay in absolute time */
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Cycles minimumCommitCycle;
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/** Flat register indices so that, when clearing the scoreboard, we
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* have the same register indices as when the instruction was marked
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* up */
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TheISA::RegIndex flatDestRegIdx[TheISA::MaxInstDestRegs];
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/** Effective address as set by ExecContext::setEA */
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Addr ea;
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public:
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MinorDynInst(InstId id_ = InstId(), Fault fault_ = NoFault) :
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staticInst(NULL), id(id_), traceData(NULL),
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pc(TheISA::PCState(0)), fault(fault_),
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triedToPredict(false), predictedTaken(false),
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fuIndex(0), inLSQ(false), inStoreBuffer(false),
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canEarlyIssue(false),
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instToWaitFor(0), extraCommitDelay(Cycles(0)),
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extraCommitDelayExpr(NULL), minimumCommitCycle(Cycles(0)),
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ea(0)
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{ }
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public:
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/** The BubbleIF interface. */
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bool isBubble() const { return id.fetchSeqNum == 0; }
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/** There is a single bubble inst */
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static MinorDynInstPtr bubble() { return bubbleInst; }
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/** Is this a fault rather than instruction */
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bool isFault() const { return fault != NoFault; }
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/** Is this a real instruction */
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bool isInst() const { return !isBubble() && !isFault(); }
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/** Is this a real mem ref instruction */
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bool isMemRef() const { return isInst() && staticInst->isMemRef(); }
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/** Is this an instruction that can be executed `for free' and
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* needn't spend time in an FU */
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bool isNoCostInst() const;
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/** Assuming this is not a fault, is this instruction either
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* a whole instruction or the last microop from a macroop */
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bool isLastOpInInst() const;
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/** Initialise the class */
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static void init();
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/** Print (possibly verbose) instruction information for
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* MinorTrace using the given Named object's name */
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void minorTraceInst(const Named &named_object) const;
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/** ReportIF interface */
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void reportData(std::ostream &os) const;
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~MinorDynInst();
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};
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/** Print a summary of the instruction */
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std::ostream &operator <<(std::ostream &os, const MinorDynInst &inst);
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}
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#endif /* __CPU_MINOR_DYN_INST_HH__ */
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