2014-07-23 23:09:04 +02:00
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/*
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* Copyright (c) 2013-2014 ARM Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Andrew Bardsley
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*/
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#include "cpu/timing_expr.hh"
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2016-11-09 21:27:37 +01:00
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#include "base/intmath.hh"
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2014-09-27 15:08:36 +02:00
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TimingExprEvalContext::TimingExprEvalContext(const StaticInstPtr &inst_,
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2014-07-23 23:09:04 +02:00
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ThreadContext *thread_,
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TimingExprLet *let_) :
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inst(inst_), thread(thread_), let(let_)
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{
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/* Reserve space to hold the results of evaluating the
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* let expressions */
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if (let) {
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unsigned int num_defns = let->defns.size();
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results.resize(num_defns, 0);
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resultAvailable.resize(num_defns, false);
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}
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}
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uint64_t TimingExprSrcReg::eval(TimingExprEvalContext &context)
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{
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return context.inst->srcRegIdx(index);
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}
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uint64_t TimingExprReadIntReg::eval(TimingExprEvalContext &context)
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{
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return context.thread->readIntReg(reg->eval(context));
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}
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uint64_t TimingExprLet::eval(TimingExprEvalContext &context)
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{
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TimingExprEvalContext new_context(context.inst,
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context.thread, this);
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return expr->eval(new_context);
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}
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uint64_t TimingExprRef::eval(TimingExprEvalContext &context)
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{
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/* Lookup the result, evaluating if necessary. @todo, this
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* should have more error checking */
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if (!context.resultAvailable[index]) {
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context.results[index] = context.let->defns[index]->eval(context);
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context.resultAvailable[index] = true;
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}
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return context.results[index];
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}
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uint64_t TimingExprUn::eval(TimingExprEvalContext &context)
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{
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uint64_t arg_value = arg->eval(context);
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uint64_t ret = 0;
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switch (op) {
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case Enums::timingExprSizeInBits:
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if (arg_value == 0)
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ret = 0;
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else
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ret = ceilLog2(arg_value);
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break;
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case Enums::timingExprNot:
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ret = arg_value != 0;
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break;
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case Enums::timingExprInvert:
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ret = ~arg_value;
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break;
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case Enums::timingExprSignExtend32To64:
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ret = static_cast<int64_t>(
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static_cast<int32_t>(arg_value));
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break;
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case Enums::timingExprAbs:
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if (static_cast<int64_t>(arg_value) < 0)
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ret = -arg_value;
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else
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ret = arg_value;
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break;
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default:
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break;
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}
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return ret;
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}
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uint64_t TimingExprBin::eval(TimingExprEvalContext &context)
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{
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uint64_t left_value = left->eval(context);
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uint64_t right_value = right->eval(context);
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uint64_t ret = 0;
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switch (op) {
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case Enums::timingExprAdd:
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ret = left_value + right_value;
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break;
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case Enums::timingExprSub:
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ret = left_value - right_value;
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break;
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case Enums::timingExprUMul:
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ret = left_value * right_value;
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break;
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case Enums::timingExprUDiv:
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if (right_value != 0) {
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ret = left_value / right_value;
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}
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break;
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case Enums::timingExprUCeilDiv:
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if (right_value != 0) {
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ret = (left_value + (right_value - 1)) / right_value;
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}
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break;
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case Enums::timingExprSMul:
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ret = static_cast<int64_t>(left_value) *
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static_cast<int64_t>(right_value);
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break;
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case Enums::timingExprSDiv:
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if (right_value != 0) {
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ret = static_cast<int64_t>(left_value) /
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static_cast<int64_t>(right_value);
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}
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break;
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case Enums::timingExprEqual:
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ret = left_value == right_value;
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break;
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case Enums::timingExprNotEqual:
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ret = left_value != right_value;
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break;
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case Enums::timingExprULessThan:
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ret = left_value < right_value;
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break;
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case Enums::timingExprUGreaterThan:
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ret = left_value > right_value;
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break;
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case Enums::timingExprSLessThan:
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ret = static_cast<int64_t>(left_value) <
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static_cast<int64_t>(right_value);
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break;
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case Enums::timingExprSGreaterThan:
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ret = static_cast<int64_t>(left_value) >
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static_cast<int64_t>(right_value);
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break;
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case Enums::timingExprAnd:
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ret = (left_value != 0) && (right_value != 0);
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break;
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case Enums::timingExprOr:
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ret = (left_value != 0) || (right_value != 0);
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break;
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default:
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break;
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}
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return ret;
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}
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uint64_t TimingExprIf::eval(TimingExprEvalContext &context)
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{
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uint64_t cond_value = cond->eval(context);
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if (cond_value != 0)
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return trueExpr->eval(context);
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else
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return falseExpr->eval(context);
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}
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TimingExprLiteral *
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TimingExprLiteralParams::create()
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{
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return new TimingExprLiteral(this);
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}
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TimingExprSrcReg *
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TimingExprSrcRegParams::create()
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{
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return new TimingExprSrcReg(this);
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}
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TimingExprReadIntReg *
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TimingExprReadIntRegParams::create()
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{
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return new TimingExprReadIntReg(this);
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}
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TimingExprLet *
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TimingExprLetParams::create()
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{
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return new TimingExprLet(this);
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}
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TimingExprRef *
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TimingExprRefParams::create()
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{
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return new TimingExprRef(this);
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}
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TimingExprUn *
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TimingExprUnParams::create()
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{
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return new TimingExprUn(this);
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}
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TimingExprBin *
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TimingExprBinParams::create()
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{
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return new TimingExprBin(this);
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}
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TimingExprIf *
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TimingExprIfParams::create()
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{
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return new TimingExprIf(this);
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}
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