2005-06-05 07:22:21 +02:00
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/*
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2005-06-05 11:16:00 +02:00
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* Copyright (c) 2005 The Regents of The University of Michigan
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2005-06-05 07:22:21 +02:00
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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2006-06-01 01:26:56 +02:00
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*
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* Authors: Ali Saidi
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2005-06-05 07:22:21 +02:00
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*/
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/** @file
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* Defines a 8250 UART
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*/
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2006-04-06 20:57:51 +02:00
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#ifndef __DEV_UART8250_HH__
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#define __DEV_UART8250_HH__
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2005-06-05 07:22:21 +02:00
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#include "dev/io_device.hh"
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#include "dev/uart.hh"
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2007-07-24 06:51:38 +02:00
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#include "params/Uart8250.hh"
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2005-08-15 22:59:58 +02:00
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/* UART8250 Interrupt ID Register
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* bit 0 Interrupt Pending 0 = true, 1 = false
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* bit 2:1 ID of highest priority interrupt
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* bit 7:3 zeroes
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*/
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2006-04-25 01:31:50 +02:00
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const uint8_t IIR_NOPEND = 0x1;
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2005-08-15 22:59:58 +02:00
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// Interrupt IDs
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2006-04-25 01:31:50 +02:00
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const uint8_t IIR_MODEM = 0x00; /* Modem Status (lowest priority) */
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const uint8_t IIR_TXID = 0x02; /* Tx Data */
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const uint8_t IIR_RXID = 0x04; /* Rx Data */
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const uint8_t IIR_LINE = 0x06; /* Rx Line Status (highest priority)*/
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2005-08-15 22:59:58 +02:00
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2007-02-13 21:58:06 +01:00
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const uint8_t UART_IER_RDI = 0x01;
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const uint8_t UART_IER_THRI = 0x02;
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const uint8_t UART_IER_RLSI = 0x04;
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const uint8_t UART_LSR_TEMT = 0x40;
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const uint8_t UART_LSR_THRE = 0x20;
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const uint8_t UART_LSR_DR = 0x01;
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const uint8_t UART_MCR_LOOP = 0x10;
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2008-06-18 05:29:06 +02:00
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class Terminal;
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2005-06-05 07:22:21 +02:00
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class Platform;
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class Uart8250 : public Uart
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{
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protected:
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uint8_t IER, DLAB, LCR, MCR;
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2007-04-30 19:13:03 +02:00
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Tick lastTxInt;
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2005-06-05 07:22:21 +02:00
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class IntrEvent : public Event
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{
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protected:
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Uart8250 *uart;
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int intrBit;
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public:
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IntrEvent(Uart8250 *u, int bit);
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virtual void process();
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2008-02-06 22:32:40 +01:00
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virtual const char *description() const;
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2005-06-05 07:22:21 +02:00
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void scheduleIntr();
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};
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IntrEvent txIntrEvent;
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IntrEvent rxIntrEvent;
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public:
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2007-07-24 06:51:38 +02:00
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typedef Uart8250Params Params;
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const Params *
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params() const
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{
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return dynamic_cast<const Params *>(_params);
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}
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Uart8250(const Params *p);
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2005-06-05 07:22:21 +02:00
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2006-10-20 09:10:12 +02:00
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virtual Tick read(PacketPtr pkt);
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virtual Tick write(PacketPtr pkt);
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2012-07-09 18:35:34 +02:00
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virtual AddrRangeList getAddrRanges() const;
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2005-06-05 07:22:21 +02:00
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/**
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* Inform the uart that there is data available.
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*/
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virtual void dataAvailable();
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/**
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* Return if we have an interrupt pending
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* @return interrupt status
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*/
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virtual bool intStatus() { return status ? true : false; }
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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};
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#endif // __TSUNAMI_UART_HH__
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