gem5/src/mem/ruby/structures/TimerTable.cc

129 lines
3.5 KiB
C++
Raw Normal View History

/*
* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
ruby: move files from ruby/system to ruby/structures The directory ruby/system is crowded and unorganized. Hence, the files the hold actual physical structures, are being moved to the directory ruby/structures. This includes Cache Memory, Directory Memory, Memory Controller, Wire Buffer, TBE Table, Perfect Cache Memory, Timer Table, Bank Array. The directory ruby/systems has the glue code that holds these structures together. --HG-- rename : src/mem/ruby/system/MachineID.hh => src/mem/ruby/common/MachineID.hh rename : src/mem/ruby/buffers/MessageBuffer.cc => src/mem/ruby/network/MessageBuffer.cc rename : src/mem/ruby/buffers/MessageBuffer.hh => src/mem/ruby/network/MessageBuffer.hh rename : src/mem/ruby/buffers/MessageBufferNode.cc => src/mem/ruby/network/MessageBufferNode.cc rename : src/mem/ruby/buffers/MessageBufferNode.hh => src/mem/ruby/network/MessageBufferNode.hh rename : src/mem/ruby/system/AbstractReplacementPolicy.hh => src/mem/ruby/structures/AbstractReplacementPolicy.hh rename : src/mem/ruby/system/BankedArray.cc => src/mem/ruby/structures/BankedArray.cc rename : src/mem/ruby/system/BankedArray.hh => src/mem/ruby/structures/BankedArray.hh rename : src/mem/ruby/system/Cache.py => src/mem/ruby/structures/Cache.py rename : src/mem/ruby/system/CacheMemory.cc => src/mem/ruby/structures/CacheMemory.cc rename : src/mem/ruby/system/CacheMemory.hh => src/mem/ruby/structures/CacheMemory.hh rename : src/mem/ruby/system/DirectoryMemory.cc => src/mem/ruby/structures/DirectoryMemory.cc rename : src/mem/ruby/system/DirectoryMemory.hh => src/mem/ruby/structures/DirectoryMemory.hh rename : src/mem/ruby/system/DirectoryMemory.py => src/mem/ruby/structures/DirectoryMemory.py rename : src/mem/ruby/system/LRUPolicy.hh => src/mem/ruby/structures/LRUPolicy.hh rename : src/mem/ruby/system/MemoryControl.cc => src/mem/ruby/structures/MemoryControl.cc rename : src/mem/ruby/system/MemoryControl.hh => src/mem/ruby/structures/MemoryControl.hh rename : src/mem/ruby/system/MemoryControl.py => src/mem/ruby/structures/MemoryControl.py rename : src/mem/ruby/system/MemoryNode.cc => src/mem/ruby/structures/MemoryNode.cc rename : src/mem/ruby/system/MemoryNode.hh => src/mem/ruby/structures/MemoryNode.hh rename : src/mem/ruby/system/MemoryVector.hh => src/mem/ruby/structures/MemoryVector.hh rename : src/mem/ruby/system/PerfectCacheMemory.hh => src/mem/ruby/structures/PerfectCacheMemory.hh rename : src/mem/ruby/system/PersistentTable.cc => src/mem/ruby/structures/PersistentTable.cc rename : src/mem/ruby/system/PersistentTable.hh => src/mem/ruby/structures/PersistentTable.hh rename : src/mem/ruby/system/PseudoLRUPolicy.hh => src/mem/ruby/structures/PseudoLRUPolicy.hh rename : src/mem/ruby/system/RubyMemoryControl.cc => src/mem/ruby/structures/RubyMemoryControl.cc rename : src/mem/ruby/system/RubyMemoryControl.hh => src/mem/ruby/structures/RubyMemoryControl.hh rename : src/mem/ruby/system/RubyMemoryControl.py => src/mem/ruby/structures/RubyMemoryControl.py rename : src/mem/ruby/system/SparseMemory.cc => src/mem/ruby/structures/SparseMemory.cc rename : src/mem/ruby/system/SparseMemory.hh => src/mem/ruby/structures/SparseMemory.hh rename : src/mem/ruby/system/TBETable.hh => src/mem/ruby/structures/TBETable.hh rename : src/mem/ruby/system/TimerTable.cc => src/mem/ruby/structures/TimerTable.cc rename : src/mem/ruby/system/TimerTable.hh => src/mem/ruby/structures/TimerTable.hh rename : src/mem/ruby/system/WireBuffer.cc => src/mem/ruby/structures/WireBuffer.cc rename : src/mem/ruby/system/WireBuffer.hh => src/mem/ruby/structures/WireBuffer.hh rename : src/mem/ruby/system/WireBuffer.py => src/mem/ruby/structures/WireBuffer.py rename : src/mem/ruby/recorder/CacheRecorder.cc => src/mem/ruby/system/CacheRecorder.cc rename : src/mem/ruby/recorder/CacheRecorder.hh => src/mem/ruby/system/CacheRecorder.hh
2014-09-01 23:55:40 +02:00
#include "mem/ruby/structures/TimerTable.hh"
#include "mem/ruby/system/System.hh"
TimerTable::TimerTable()
: m_next_time(0)
{
2010-03-23 02:43:53 +01:00
m_consumer_ptr = NULL;
m_clockobj_ptr = NULL;
2010-03-23 02:43:53 +01:00
m_next_valid = false;
m_next_address = 0;
}
2010-03-23 02:43:53 +01:00
bool
TimerTable::isReady() const
{
2010-06-11 08:17:07 +02:00
if (m_map.empty())
2010-03-23 02:43:53 +01:00
return false;
2010-03-23 02:43:53 +01:00
if (!m_next_valid) {
updateNext();
}
assert(m_next_valid);
return (m_clockobj_ptr->curCycle() >= m_next_time);
}
Addr
2010-03-23 02:43:53 +01:00
TimerTable::readyAddress() const
{
2010-03-23 02:43:53 +01:00
assert(isReady());
2010-03-23 02:43:53 +01:00
if (!m_next_valid) {
updateNext();
}
assert(m_next_valid);
return m_next_address;
}
2010-03-23 02:43:53 +01:00
void
TimerTable::set(Addr address, Cycles relative_latency)
{
assert(address == makeLineAddress(address));
2010-03-23 02:43:53 +01:00
assert(relative_latency > 0);
2010-06-11 08:17:07 +02:00
assert(!m_map.count(address));
Cycles ready_time = m_clockobj_ptr->curCycle() + relative_latency;
2010-06-11 08:17:07 +02:00
m_map[address] = ready_time;
2010-03-23 02:43:53 +01:00
assert(m_consumer_ptr != NULL);
m_consumer_ptr->
scheduleEventAbsolute(m_clockobj_ptr->clockPeriod() * ready_time);
m_next_valid = false;
2010-03-23 02:43:53 +01:00
// Don't always recalculate the next ready address
if (ready_time <= m_next_time) {
m_next_valid = false;
}
}
2010-03-23 02:43:53 +01:00
void
TimerTable::unset(Addr address)
{
assert(address == makeLineAddress(address));
2010-06-11 08:17:07 +02:00
assert(m_map.count(address));
m_map.erase(address);
2010-03-23 02:43:53 +01:00
// Don't always recalculate the next ready address
if (address == m_next_address) {
m_next_valid = false;
}
}
2010-03-23 02:43:53 +01:00
void
TimerTable::print(std::ostream& out) const
{
}
2010-03-23 02:43:53 +01:00
void
TimerTable::updateNext() const
{
2010-06-11 08:17:07 +02:00
if (m_map.empty()) {
assert(!m_next_valid);
2010-03-23 02:43:53 +01:00
return;
}
2010-06-11 08:17:07 +02:00
AddressMap::const_iterator i = m_map.begin();
AddressMap::const_iterator end = m_map.end();
m_next_address = i->first;
m_next_time = i->second;
++i;
for (; i != end; ++i) {
if (i->second < m_next_time) {
m_next_address = i->first;
m_next_time = i->second;
2010-03-23 02:43:53 +01:00
}
}
2010-06-11 08:17:07 +02:00
2010-03-23 02:43:53 +01:00
m_next_valid = true;
}