2008-11-10 06:57:15 +01:00
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---------- Begin Simulation Statistics ----------
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2010-09-09 20:40:19 +02:00
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sim_seconds 0.000029 # Number of seconds simulated
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sim_ticks 28768000 # Number of ticks simulated
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2012-01-10 16:59:01 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 524711 # Simulator instruction rate (inst/s)
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host_tick_rate 1537080573 # Simulator tick rate (ticks/s)
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host_mem_usage 238628 # Number of bytes of host memory used
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host_seconds 0.02 # Real time elapsed on the host
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sim_insts 9810 # Number of instructions simulated
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system.cpu.workload.num_syscalls 11 # Number of system calls
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system.cpu.numCycles 57536 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.num_insts 9810 # Number of instructions executed
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system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
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system.cpu.num_func_calls 0 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls
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system.cpu.num_int_insts 9715 # number of integer instructions
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system.cpu.num_fp_insts 0 # number of float instructions
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system.cpu.num_int_register_reads 21313 # number of times the integer registers were read
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system.cpu.num_int_register_writes 9368 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
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system.cpu.num_mem_refs 1990 # number of memory refs
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system.cpu.num_load_insts 1056 # Number of load instructions
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system.cpu.num_store_insts 934 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 57536 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.replacements 0 # number of replacements
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system.cpu.icache.tagsinuse 105.363985 # Cycle average of tags in use
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system.cpu.icache.total_refs 6683 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 29.311404 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.occ_blocks::0 105.363985 # Average occupied blocks per context
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system.cpu.icache.occ_percent::0 0.051447 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits 6683 # number of ReadReq hits
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system.cpu.icache.demand_hits 6683 # number of demand (read+write) hits
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system.cpu.icache.overall_hits 6683 # number of overall hits
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system.cpu.icache.ReadReq_misses 228 # number of ReadReq misses
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system.cpu.icache.demand_misses 228 # number of demand (read+write) misses
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system.cpu.icache.overall_misses 228 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency 12726000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency 12726000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency 12726000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses 6911 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses 6911 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses 6911 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate 0.032991 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate 0.032991 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate 0.032991 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency 55815.789474 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency 55815.789474 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency 55815.789474 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.icache.ReadReq_mshr_misses 228 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses 228 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses 228 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.ReadReq_mshr_miss_latency 12042000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency 12042000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency 12042000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.032991 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate 0.032991 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate 0.032991 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 52815.789474 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.replacements 0 # number of replacements
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system.cpu.dcache.tagsinuse 80.668870 # Cycle average of tags in use
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system.cpu.dcache.total_refs 1856 # Total number of references to valid blocks.
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system.cpu.dcache.sampled_refs 134 # Sample count of references to valid blocks.
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system.cpu.dcache.avg_refs 13.850746 # Average number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.occ_blocks::0 80.668870 # Average occupied blocks per context
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system.cpu.dcache.occ_percent::0 0.019695 # Average percentage of cache occupancy
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2010-05-03 09:45:01 +02:00
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system.cpu.dcache.ReadReq_hits 1001 # number of ReadReq hits
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2010-09-09 20:40:19 +02:00
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system.cpu.dcache.WriteReq_hits 855 # number of WriteReq hits
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2012-01-10 16:59:01 +01:00
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system.cpu.dcache.demand_hits 1856 # number of demand (read+write) hits
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system.cpu.dcache.overall_hits 1856 # number of overall hits
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system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses
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system.cpu.dcache.WriteReq_misses 79 # number of WriteReq misses
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system.cpu.dcache.demand_misses 134 # number of demand (read+write) misses
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system.cpu.dcache.overall_misses 134 # number of overall misses
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system.cpu.dcache.ReadReq_miss_latency 3080000 # number of ReadReq miss cycles
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2010-09-09 20:40:19 +02:00
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system.cpu.dcache.WriteReq_miss_latency 4424000 # number of WriteReq miss cycles
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2012-01-10 16:59:01 +01:00
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system.cpu.dcache.demand_miss_latency 7504000 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency 7504000 # number of overall miss cycles
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system.cpu.dcache.ReadReq_accesses 1056 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.demand_accesses 1990 # number of demand (read+write) accesses
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system.cpu.dcache.overall_accesses 1990 # number of overall (read+write) accesses
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system.cpu.dcache.ReadReq_miss_rate 0.052083 # miss rate for ReadReq accesses
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2010-09-09 20:40:19 +02:00
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system.cpu.dcache.WriteReq_miss_rate 0.084582 # miss rate for WriteReq accesses
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2012-01-10 16:59:01 +01:00
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system.cpu.dcache.demand_miss_rate 0.067337 # miss rate for demand accesses
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system.cpu.dcache.overall_miss_rate 0.067337 # miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
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system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
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2009-04-22 19:25:17 +02:00
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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2012-01-10 16:59:01 +01:00
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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2008-11-10 06:57:15 +01:00
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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2012-01-10 16:59:01 +01:00
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system.cpu.dcache.writebacks 0 # number of writebacks
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2008-11-10 06:57:15 +01:00
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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2012-01-10 16:59:01 +01:00
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_misses 79 # number of WriteReq MSHR misses
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system.cpu.dcache.demand_mshr_misses 134 # number of demand (read+write) MSHR misses
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system.cpu.dcache.overall_mshr_misses 134 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.ReadReq_mshr_miss_latency 2915000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_latency 4187000 # number of WriteReq MSHR miss cycles
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2010-09-09 20:40:19 +02:00
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system.cpu.dcache.demand_mshr_miss_latency 7102000 # number of demand (read+write) MSHR miss cycles
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2012-01-10 16:59:01 +01:00
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system.cpu.dcache.overall_mshr_miss_latency 7102000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.052083 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.084582 # mshr miss rate for WriteReq accesses
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2010-09-09 20:40:19 +02:00
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system.cpu.dcache.demand_mshr_miss_rate 0.067337 # mshr miss rate for demand accesses
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2012-01-10 16:59:01 +01:00
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system.cpu.dcache.overall_mshr_miss_rate 0.067337 # mshr miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
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2008-11-10 06:57:15 +01:00
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system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
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2009-04-22 19:25:17 +02:00
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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2012-01-10 16:59:01 +01:00
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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2008-11-10 06:57:15 +01:00
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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2012-01-10 16:59:01 +01:00
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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|
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system.cpu.l2cache.replacements 0 # number of replacements
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system.cpu.l2cache.tagsinuse 133.809342 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
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system.cpu.l2cache.sampled_refs 282 # Sample count of references to valid blocks.
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system.cpu.l2cache.avg_refs 0.003546 # Average number of references to valid blocks.
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|
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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|
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system.cpu.l2cache.occ_blocks::0 133.809342 # Average occupied blocks per context
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system.cpu.l2cache.occ_percent::0 0.004084 # Average percentage of cache occupancy
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2008-11-10 06:57:15 +01:00
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|
|
system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
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2012-01-10 16:59:01 +01:00
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|
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system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
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|
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system.cpu.l2cache.overall_hits 1 # number of overall hits
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|
|
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system.cpu.l2cache.ReadReq_misses 282 # number of ReadReq misses
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|
|
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system.cpu.l2cache.ReadExReq_misses 79 # number of ReadExReq misses
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|
|
|
|
system.cpu.l2cache.demand_misses 361 # number of demand (read+write) misses
|
|
|
|
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system.cpu.l2cache.overall_misses 361 # number of overall misses
|
2010-05-03 09:45:01 +02:00
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 14664000 # number of ReadReq miss cycles
|
2012-01-10 16:59:01 +01:00
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|
|
system.cpu.l2cache.ReadExReq_miss_latency 4108000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 18772000 # number of demand (read+write) miss cycles
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|
|
|
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system.cpu.l2cache.overall_miss_latency 18772000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 283 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses 79 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses 362 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses 362 # number of overall (read+write) accesses
|
2010-05-03 09:45:01 +02:00
|
|
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system.cpu.l2cache.ReadReq_miss_rate 0.996466 # miss rate for ReadReq accesses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
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|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.997238 # miss rate for demand accesses
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|
|
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system.cpu.l2cache.overall_miss_rate 0.997238 # miss rate for overall accesses
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|
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system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
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|
|
|
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system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
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|
|
|
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system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
|
|
|
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system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2008-11-10 06:57:15 +01:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
2008-11-10 06:57:15 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 282 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 79 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 361 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 361 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 11280000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 3160000 # number of ReadExReq MSHR miss cycles
|
2010-05-03 09:45:01 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 14440000 # number of demand (read+write) MSHR miss cycles
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 14440000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.996466 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
2010-05-03 09:45:01 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.997238 # mshr miss rate for demand accesses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.997238 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
2008-11-10 06:57:15 +01:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2008-11-10 06:57:15 +01:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2008-11-10 06:57:15 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
