2013-09-28 21:25:17 +02:00
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Redirecting stdout to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem/simout
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Redirecting stderr to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem/simerr
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2012-09-21 17:48:11 +02:00
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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2013-09-28 21:25:17 +02:00
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gem5 compiled Sep 22 2013 05:53:51
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gem5 started Sep 22 2013 05:53:54
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gem5 executing on zizzer
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command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem -re tests/run.py build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem
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2012-09-21 17:48:11 +02:00
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Global frequency set at 1000000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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Exiting @ tick 100000000000 because simulate() limit reached
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