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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/system.terminal

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tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
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[ 0.000000] Linux version 2.6.38.8-gem5 (saidi@zeep) (gcc version 4.5.2 (Sourcery G++ Lite 2011.03-41) ) #1 SMP Mon Aug 15 21:18:38 EDT 2011
[ 0.000000] CPU: ARMv7 Processor [350fc000] revision 0 (ARMv7), cr=10c53c7f
[ 0.000000] CPU: VIPT nonaliasing data cache, VIPT nonaliasing instruction cache
[ 0.000000] Machine: ARM-RealView PBX
[ 0.000000] Ignoring unrecognised tag 0x00000000
[ 0.000000] bootconsole [earlycon0] enabled
[ 0.000000] Memory policy: ECC disabled, Data cache writealloc
[ 0.000000] On node 0 totalpages: 32768
[ 0.000000] DMA zone: 256 pages used for memmap
[ 0.000000] DMA zone: 0 pages reserved
[ 0.000000] DMA zone: 32512 pages, LIFO batch:7
[ 0.000000] PERCPU: Embedded 7 pages/cpu @c0556000 s6272 r8192 d14208 u32768
[ 0.000000] pcpu-alloc: s6272 r8192 d14208 u32768 alloc=8*4096
[ 0.000000] pcpu-alloc: [0] 0
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 32512
[ 0.000000] Kernel command line: earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
[ 0.000000] PID hash table entries: 512 (order: -1, 2048 bytes)
[ 0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
[ 0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
[ 0.000000] Memory: 128MB = 128MB total
[ 0.000000] Memory: 125408k/125408k available, 5664k reserved, 0K highmem
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
[ 0.000000] fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
[ 0.000000] DMA : 0xffc00000 - 0xffe00000 ( 2 MB)
[ 0.000000] vmalloc : 0xc8800000 - 0xf8000000 ( 760 MB)
[ 0.000000] lowmem : 0xc0000000 - 0xc8000000 ( 128 MB)
[ 0.000000] modules : 0xbf000000 - 0xc0000000 ( 16 MB)
[ 0.000000] .init : 0xc0008000 - 0xc0029000 ( 132 kB)
[ 0.000000] .text : 0xc0029000 - 0xc031c044 (3021 kB)
[ 0.000000] .data : 0xc031e000 - 0xc0336b40 ( 99 kB)
[ 0.000000] Hierarchical RCU implementation.
[ 0.000000] RCU-based detection of stalled CPUs is disabled.
[ 0.000000] NR_IRQS:128
[ 0.000000] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 178956ms
[ 0.000000] Console: colour dummy device 80x30
[ 0.000051] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
[ 0.000059] pid_max: default: 32768 minimum: 301
[ 0.000116] Mount-cache hash table entries: 512
[ 0.000218] CPU: Testing write buffer coherency: ok
[ 0.000283] Brought up 1 CPUs
[ 0.000287] SMP: Total of 1 processors activated (3997.69 BogoMIPS).
[ 0.000332] devtmpfs: initialized
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
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[ 0.000872] NET: Registered protocol family 16
[ 0.001905] Serial: AMBA PL011 UART driver
[ 0.001964] dev:uart0: ttyAMA0 at MMIO 0x10009000 (irq = 44) is a PL011 rev3
[ 0.002027] console [ttyAMA0] enabled, bootconsole disabled
[ 0.002027] console [ttyAMA0] enabled, bootconsole disabled
[ 0.003753] bio: create slab <bio-0> at 0
[ 0.004009] SCSI subsystem initialized
[ 0.004256] libata version 3.00 loaded.
[ 0.004825] Switching to clocksource timer3
[ 0.008499] NET: Registered protocol family 2
[ 0.008565] IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
[ 0.008702] TCP established hash table entries: 4096 (order: 3, 32768 bytes)
[ 0.008769] TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
[ 0.008829] TCP: Hash tables configured (established 4096 bind 4096)
[ 0.008867] TCP reno registered
[ 0.008888] UDP hash table entries: 128 (order: 0, 4096 bytes)
[ 0.008929] UDP-Lite hash table entries: 128 (order: 0, 4096 bytes)
[ 0.009005] NET: Registered protocol family 1
[ 0.009320] msgmni has been set to 244
[ 0.009328] io scheduler noop registered (default)
[ 0.009793] CLCD: RealView hardware, XVGA display
[ 0.033369] Console: switching to colour frame buffer device 128x48
[ 0.039947] brd: module loaded
[ 0.041488] loop: module loaded
[ 0.041967] scsi0 : pata_platform
[ 0.042070] ata1: PATA max PIO0 no IRQ, using PIO polling mmio cmd 0x18000000 ctl 0x18000100
[ 0.042294] slram: not enough parameters.
[ 0.042478] mousedev: PS/2 mouse device common for all mice
[ 0.042567] TCP cubic registered
[ 0.042570] NET: Registered protocol family 17
[ 0.042574] VFP support v0.3: implementor 41 architecture 4 part 30 variant a rev 0
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
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[ 0.200102] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
[ 0.200107] ata1.00: 1048320 sectors, multi 0: LBA
[ 0.200112] ata1.00: configured for PIO
[ 0.200167] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
[ 0.200318] sd 0:0:0:0: [sda] 1048320 512-byte logical blocks: (536 MB/511 MiB)
[ 0.200360] sd 0:0:0:0: [sda] Write Protect is off
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[ 0.200365] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
[ 0.200384] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
[ 0.200740] sda: sda1
[ 0.200792] sd 0:0:0:0: Attached scsi generic sg0 type 0
[ 0.200930] sd 0:0:0:0: [sda] Attached SCSI disk
[ 0.640109] input: AT Raw Set 2 keyboard as /devices/fpga:kmi0/serio0/input/input0
[ 2.240093] input: touchkitPS/2 eGalax Touchscreen as /devices/fpga:kmi1/serio1/input/input1
[ 2.260514] VFS: Mounted root (ext2 filesystem) on device 8:1.
[ 2.260711] devtmpfs: mounted
[ 2.260723] Freeing init memory: 132K
init started: BusyBox v1.15.3 (2010-05-07 01:27:07 BST)
starting pid 331, tty '': '/etc/rc.d/rc.local'
warning: can't open /etc/mtab: No such file or directory
Thu Jan 1 00:00:02 UTC 1970
S: devpts
Thu Jan 1 00:00:02 UTC 1970
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