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gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt

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cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
---------- Begin Simulation Statistics ----------
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
sim_seconds 1.883224 # Number of seconds simulated
sim_ticks 1883223940000 # Number of ticks simulated
final_tick 1883223940000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
host_inst_rate 180615 # Simulator instruction rate (inst/s)
host_op_rate 180615 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 6060637883 # Simulator tick rate (ticks/s)
host_mem_usage 316396 # Number of bytes of host memory used
host_seconds 310.73 # Real time elapsed on the host
sim_insts 56122642 # Number of instructions simulated
sim_ops 56122642 # Number of ops (including micro ops) simulated
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.voltage_domain.voltage 1 # Voltage in Volts
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
system.clk_domain.clock 1000 # Clock period in ticks
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.bytes_read::cpu.inst 25930944 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::total 25931904 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1052544 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1052544 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4902720 # Number of bytes written to this memory
system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory
system.physmem.bytes_written::total 7562048 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 405171 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
system.physmem.num_reads::total 405186 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 76605 # Number of write requests responded to by this memory
system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory
system.physmem.num_writes::total 118157 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 13769443 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 510 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 13769952 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 558905 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 558905 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2603365 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::tsunami.ide 1412115 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 4015480 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2603365 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 13769443 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1412624 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 17785432 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 405186 # Number of read requests accepted
system.physmem.writeReqs 118157 # Number of write requests accepted
system.physmem.readBursts 405186 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 118157 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 25919424 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 12480 # Total number of bytes read from write queue
system.physmem.bytesWritten 7560064 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 25931904 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 7562048 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 195 # Number of DRAM read bursts serviced by the write queue
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.neitherReadNorWriteReqs 157 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 25480 # Per bank write bursts
system.physmem.perBankRdBursts::1 25741 # Per bank write bursts
system.physmem.perBankRdBursts::2 25855 # Per bank write bursts
system.physmem.perBankRdBursts::3 25788 # Per bank write bursts
system.physmem.perBankRdBursts::4 25233 # Per bank write bursts
system.physmem.perBankRdBursts::5 24956 # Per bank write bursts
system.physmem.perBankRdBursts::6 24811 # Per bank write bursts
system.physmem.perBankRdBursts::7 24586 # Per bank write bursts
system.physmem.perBankRdBursts::8 25127 # Per bank write bursts
system.physmem.perBankRdBursts::9 25280 # Per bank write bursts
system.physmem.perBankRdBursts::10 25532 # Per bank write bursts
system.physmem.perBankRdBursts::11 24857 # Per bank write bursts
system.physmem.perBankRdBursts::12 24547 # Per bank write bursts
system.physmem.perBankRdBursts::13 25588 # Per bank write bursts
system.physmem.perBankRdBursts::14 25870 # Per bank write bursts
system.physmem.perBankRdBursts::15 25740 # Per bank write bursts
system.physmem.perBankWrBursts::0 7812 # Per bank write bursts
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.perBankWrBursts::1 7677 # Per bank write bursts
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.perBankWrBursts::2 8067 # Per bank write bursts
system.physmem.perBankWrBursts::3 7744 # Per bank write bursts
system.physmem.perBankWrBursts::4 7318 # Per bank write bursts
system.physmem.perBankWrBursts::5 6954 # Per bank write bursts
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.perBankWrBursts::6 6788 # Per bank write bursts
system.physmem.perBankWrBursts::7 6406 # Per bank write bursts
system.physmem.perBankWrBursts::8 7235 # Per bank write bursts
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.perBankWrBursts::9 6889 # Per bank write bursts
system.physmem.perBankWrBursts::10 7393 # Per bank write bursts
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.perBankWrBursts::11 6865 # Per bank write bursts
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.perBankWrBursts::12 7045 # Per bank write bursts
system.physmem.perBankWrBursts::13 8007 # Per bank write bursts
system.physmem.perBankWrBursts::14 7989 # Per bank write bursts
system.physmem.perBankWrBursts::15 7937 # Per bank write bursts
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.numWrRetry 5 # Number of times write queue was full causing retry
system.physmem.totGap 1883215178500 # Total gap between requests
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.readPktSize::6 405186 # Read request sizes (log2)
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.writePktSize::6 118157 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 402670 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 2243 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 66 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.wrQLenPdf::15 1541 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 2210 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5693 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 5920 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 6144 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6907 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 7208 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 8408 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 8700 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 8681 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 8384 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 8515 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 7009 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 6582 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 5776 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 5533 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 5557 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 5513 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 225 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 212 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 188 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 177 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 158 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 137 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 112 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 118 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 140 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 127 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 148 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 178 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 193 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 184 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 166 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 173 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 163 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 137 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 123 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 131 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 125 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 108 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 101 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 82 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 73 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 59 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 34 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 18 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 12 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 62955 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 531.800302 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 324.503879 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 415.177975 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 14434 22.93% 22.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 10626 16.88% 39.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 4984 7.92% 47.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3035 4.82% 52.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2479 3.94% 56.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 2063 3.28% 59.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1365 2.17% 61.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1615 2.57% 64.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 22354 35.51% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 62955 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 5310 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 76.265725 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 2898.384419 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-8191 5307 99.94% 99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 5310 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 5310 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 22.245951 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.963647 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 20.434666 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 4660 87.76% 87.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 16 0.30% 88.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 15 0.28% 88.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 227 4.27% 92.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 38 0.72% 93.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 5 0.09% 93.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 8 0.15% 93.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 6 0.11% 93.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 26 0.49% 94.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 4 0.08% 94.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 5 0.09% 94.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 14 0.26% 94.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 2 0.04% 94.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 5 0.09% 94.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 26 0.49% 95.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 9 0.17% 95.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91 5 0.09% 95.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 6 0.11% 95.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 182 3.43% 99.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 6 0.11% 99.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111 1 0.02% 99.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 2 0.04% 99.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123 3 0.06% 99.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 2 0.04% 99.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 6 0.11% 99.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 5 0.09% 99.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139 4 0.08% 99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 2 0.04% 99.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 7 0.13% 99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155 1 0.02% 99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 1 0.02% 99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163 5 0.09% 99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179 2 0.04% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183 1 0.02% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-227 3 0.06% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 5310 # Writes before turning the bus around for reads
system.physmem.totQLat 2131293750 # Total ticks spent queuing
system.physmem.totMemAccLat 9724875000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2024955000 # Total ticks spent in databus transfers
system.physmem.avgQLat 5262.57 # Average queueing delay per DRAM burst
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.avgMemAccLat 24012.57 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 13.76 # Average DRAM read bandwidth in MiByte/s
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.avgWrBW 4.01 # Average achieved write bandwidth in MiByte/s
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.avgRdBWSys 13.77 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 4.02 # Average system write bandwidth in MiByte/s
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.busUtil 0.14 # Data bus utilization in percentage
system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 24.54 # Average write queue length when enqueuing
system.physmem.readRowHits 364467 # Number of row buffer hits during reads
system.physmem.writeRowHits 95695 # Number of row buffer hits during writes
system.physmem.readRowHitRate 89.99 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 80.99 # Row buffer hit rate for writes
system.physmem.avgGap 3598433.87 # Average gap between requests
system.physmem.pageHitRate 87.96 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 1774121817500 # Time in different power states
system.physmem.memoryStateTime::REF 62884900000 # Time in different power states
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.memoryStateTime::ACT 46214912500 # Time in different power states
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.membus.throughput 17814330 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 295751 # Transaction distribution
system.membus.trans_dist::ReadResp 295735 # Transaction distribution
system.membus.trans_dist::WriteReq 9618 # Transaction distribution
system.membus.trans_dist::WriteResp 9618 # Transaction distribution
system.membus.trans_dist::Writeback 76605 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
system.membus.trans_dist::UpgradeReq 157 # Transaction distribution
system.membus.trans_dist::UpgradeResp 157 # Transaction distribution
system.membus.trans_dist::ReadExReq 116539 # Transaction distribution
system.membus.trans_dist::ReadExResp 116539 # Transaction distribution
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.membus.trans_dist::BadAddressError 16 # Transaction distribution
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33096 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887261 # Packet count per connected master and slave (bytes)
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920389 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83292 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 83292 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1003681 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44308 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30833664 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30877972 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 33538260 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 33538260 # Total data (bytes)
system.membus.snoop_data_through_bus 10112 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 29840000 # Layer occupancy (ticks)
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.membus.reqLayer1.occupancy 1547069500 # Layer occupancy (ticks)
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.membus.reqLayer2.occupancy 19500 # Layer occupancy (ticks)
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.membus.respLayer1.occupancy 3825068843 # Layer occupancy (ticks)
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.membus.respLayer2.occupancy 43112000 # Layer occupancy (ticks)
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 41685 # number of replacements
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.iocache.tags.tagsinuse 1.288165 # Cycle average of tags in use
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.iocache.tags.warmup_cycle 1728026235000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide 1.288165 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide 0.080510 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.080510 # Average percentage of cache occupancy
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.iocache.tags.tag_accesses 375533 # Number of tag accesses
system.iocache.tags.data_accesses 375533 # Number of data accesses
system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.iocache.WriteInvalidateReq_misses::tsunami.ide 1 # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total 1 # number of WriteInvalidateReq misses
system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses
system.iocache.demand_misses::total 173 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 173 # number of overall misses
system.iocache.overall_misses::total 173 # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 21132383 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 21132383 # number of ReadReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide 21132383 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 21132383 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide 21132383 # number of overall miss cycles
system.iocache.overall_miss_latency::total 21132383 # number of overall miss cycles
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41553 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 41553 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 0.000024 # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total 0.000024 # miss rate for WriteInvalidateReq accesses
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122152.502890 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 122152.502890 # average ReadReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 122152.502890 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 122152.502890 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 122152.502890 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 122152.502890 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.iocache.fast_writes 41552 # number of fast writes performed
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12135383 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 12135383 # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2514597305 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2514597305 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 12135383 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 12135383 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 12135383 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 12135383 # number of overall MSHR miss cycles
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.999976 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.999976 # mshr miss rate for WriteInvalidateReq accesses
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70146.722543 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 70146.722543 # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60516.877768 # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60516.877768 # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70146.722543 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 70146.722543 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70146.722543 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 70146.722543 # average overall mshr miss latency
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.branchPred.lookups 14964215 # Number of BP lookups
system.cpu.branchPred.condPredicted 12981470 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 376025 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 10003487 # Number of BTB lookups
system.cpu.branchPred.BTBHits 5188980 # Number of BTB hits
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.branchPred.BTBHitPct 51.871712 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 807651 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 32040 # Number of incorrect RAS predictions.
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dtb.read_hits 9238395 # DTB read hits
system.cpu.dtb.read_misses 17814 # DTB read misses
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
system.cpu.dtb.read_acv 211 # DTB read access violations
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dtb.read_accesses 766068 # DTB read accesses
system.cpu.dtb.write_hits 6385066 # DTB write hits
system.cpu.dtb.write_misses 2311 # DTB write misses
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
system.cpu.dtb.write_acv 159 # DTB write access violations
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dtb.write_accesses 298441 # DTB write accesses
system.cpu.dtb.data_hits 15623461 # DTB hits
system.cpu.dtb.data_misses 20125 # DTB misses
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.dtb.data_acv 370 # DTB access violations
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dtb.data_accesses 1064509 # DTB accesses
system.cpu.itb.fetch_hits 4000795 # ITB hits
system.cpu.itb.fetch_misses 6874 # ITB misses
system.cpu.itb.fetch_acv 703 # ITB acv
system.cpu.itb.fetch_accesses 4007669 # ITB accesses
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.numCycles 176776474 # number of cpu cycles simulated
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.committedInsts 56122642 # Number of instructions committed
system.cpu.committedOps 56122642 # Number of ops (including micro ops) committed
system.cpu.discardedOps 2532635 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 5494 # Number of times Execute suspended instruction fetching
system.cpu.quiesceCycles 3591582755 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.cpi 3.149825 # CPI: cycles per instruction
system.cpu.ipc 0.317478 # IPC: instructions per cycle
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
system.cpu.kern.inst.arm 0 # number of arm instructions executed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.kern.inst.quiesce 6375 # number of quiesce instructions executed
system.cpu.kern.inst.hwrei 211451 # number of hwrei instructions executed
system.cpu.kern.ipl_count::0 74783 40.94% 40.94% # number of times we switched to this ipl
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.kern.ipl_count::22 1900 1.04% 42.05% # number of times we switched to this ipl
system.cpu.kern.ipl_count::31 105851 57.95% 100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_count::total 182665 # number of times we switched to this ipl
system.cpu.kern.ipl_good::0 73416 49.32% 49.32% # number of times we switched to this ipl from a different ipl
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.kern.ipl_good::22 1900 1.28% 50.68% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31 73416 49.32% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total 148863 # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks::0 1832860357500 97.33% 97.33% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21 80169000 0.00% 97.33% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22 672803000 0.04% 97.37% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31 49609630000 2.63% 100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total 1883222959500 # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0 0.981720 # fraction of swpipl calls that actually changed the ipl
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.kern.ipl_used::31 0.693579 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::total 0.814951 # fraction of swpipl calls that actually changed the ipl
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
system.cpu.kern.syscall::total 326 # number of syscalls executed
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.kern.callpal::swpipl 175508 91.23% 93.43% # number of callpals executed
system.cpu.kern.callpal::rdps 6803 3.54% 96.96% # number of callpals executed
system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.kern.callpal::rti 5125 2.66% 99.64% # number of callpals executed
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.kern.callpal::total 192390 # number of callpals executed
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.kern.mode_switch::kernel 5869 # number of protection mode switches
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.kern.mode_switch::user 1741 # number of protection mode switches
system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches
system.cpu.kern.mode_good::kernel 1910
system.cpu.kern.mode_good::user 1741
system.cpu.kern.mode_good::idle 169
system.cpu.kern.mode_switch_good::kernel 0.325439 # fraction of useful protection mode switches
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.kern.mode_switch_good::idle 0.080630 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total 0.393571 # fraction of useful protection mode switches
system.cpu.kern.mode_ticks::kernel 36245351000 1.92% 1.92% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user 4057630500 0.22% 2.14% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle 1842919968000 97.86% 100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context 4175 # number of times the context was actually changed
system.cpu.tickCycles 85798616 # Number of cycles that the object actually ticked
system.cpu.idleCycles 90977858 # Total number of cycles that the object has spent stopped
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.iobus.throughput 1436853 # Throughput (bytes/s)
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.iobus.trans_dist::WriteReq 51169 # Transaction distribution
system.iobus.trans_dist::WriteResp 51170 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateReq 1 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5092 # Packet count per connected master and slave (bytes)
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.iobus.pkt_count_system.bridge.master::total 33096 # Packet count per connected master and slave (bytes)
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.iobus.pkt_count::total 116546 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20368 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.iobus.tot_pkt_size_system.bridge.master::total 44308 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.iobus.tot_pkt_size::total 2705916 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 2705916 # Total data (bytes)
system.iobus.reqLayer0.occupancy 4703000 # Layer occupancy (ticks)
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.iobus.reqLayer29.occupancy 374409688 # Layer occupancy (ticks)
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.iobus.respLayer0.occupancy 23478000 # Layer occupancy (ticks)
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.iobus.respLayer1.occupancy 42012000 # Layer occupancy (ticks)
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.tags.replacements 1458007 # number of replacements
system.cpu.icache.tags.tagsinuse 509.627041 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 18950160 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 1458518 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 12.992750 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 31562091250 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 509.627041 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.995365 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.995365 # Average percentage of cache occupancy
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::2 386 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.tags.tag_accesses 21867553 # Number of tag accesses
system.cpu.icache.tags.data_accesses 21867553 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 18950163 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 18950163 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 18950163 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 18950163 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 18950163 # number of overall hits
system.cpu.icache.overall_hits::total 18950163 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1458695 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1458695 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1458695 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1458695 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1458695 # number of overall misses
system.cpu.icache.overall_misses::total 1458695 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 20021954296 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 20021954296 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 20021954296 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 20021954296 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 20021954296 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 20021954296 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 20408858 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 20408858 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 20408858 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 20408858 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 20408858 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 20408858 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071474 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.071474 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.071474 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.071474 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.071474 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.071474 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13725.936057 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13725.936057 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13725.936057 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13725.936057 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13725.936057 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13725.936057 # average overall miss latency
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1458695 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1458695 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1458695 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1458695 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1458695 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1458695 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17097209704 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 17097209704 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17097209704 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 17097209704 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17097209704 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 17097209704 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071474 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071474 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071474 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.071474 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071474 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.071474 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11720.894158 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11720.894158 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11720.894158 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11720.894158 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11720.894158 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11720.894158 # average overall mshr miss latency
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.toL2Bus.throughput 126942050 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 2557486 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2557452 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 9618 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 9618 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 838282 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41557 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 24 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 24 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 304264 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 304264 # Transaction distribution
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2917328 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3663485 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 6580813 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93352512 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143044180 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 236396692 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 236386772 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 2673536 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 2697842997 # Layer occupancy (ticks)
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.toL2Bus.snoopLayer0.occupancy 232500 # Layer occupancy (ticks)
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.toL2Bus.respLayer0.occupancy 2191719796 # Layer occupancy (ticks)
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.toL2Bus.respLayer1.occupancy 2194901157 # Layer occupancy (ticks)
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.tags.replacements 339412 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65326.749870 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 2981869 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 404575 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 7.370374 # Average number of references to valid blocks.
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.l2cache.tags.warmup_cycle 5872511750 # Cycle when the warmup percentage was hit.
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.tags.occ_blocks::writebacks 54484.622776 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 10842.127094 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.831369 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.165438 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.996807 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1459 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5166 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2777 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55530 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 30252211 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 30252211 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 2261673 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2261673 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 838282 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 838282 # number of Writeback hits
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.l2cache.UpgradeReq_hits::cpu.inst 4 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.ReadExReq_hits::cpu.inst 187588 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 187588 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2449261 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2449261 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 2449261 # number of overall hits
system.cpu.l2cache.overall_hits::total 2449261 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 288648 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 288648 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.inst 20 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 20 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.inst 116676 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 116676 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 405324 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 405324 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 405324 # number of overall misses
system.cpu.l2cache.overall_misses::total 405324 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18909912500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 18909912500 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 115495 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 115495 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 8088441363 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 8088441363 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 26998353863 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 26998353863 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 26998353863 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 26998353863 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 2550321 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 2550321 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 838282 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 838282 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 24 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 24 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.inst 304264 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 304264 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 2854585 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2854585 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 2854585 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2854585 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.113181 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.113181 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.833333 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.833333 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.383470 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.383470 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.141991 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.141991 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.141991 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.141991 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65512.016366 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 65512.016366 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 5774.750000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 5774.750000 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69323.951481 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69323.951481 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66609.314679 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 66609.314679 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66609.314679 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 66609.314679 # average overall miss latency
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.writebacks::writebacks 76605 # number of writebacks
system.cpu.l2cache.writebacks::total 76605 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 288648 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 288648 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 20 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 20 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 116676 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 116676 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 405324 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 405324 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 405324 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 405324 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15301161000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15301161000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 201018 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 201018 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6587763637 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6587763637 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21888924637 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 21888924637 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21888924637 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 21888924637 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1333222000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333222000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 1887374000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1887374000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3220596000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3220596000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113181 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.113181 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.833333 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.833333 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.383470 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383470 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.141991 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.141991 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.141991 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.141991 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53009.759292 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53009.759292 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10050.900000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10050.900000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56462.028498 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56462.028498 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54003.524679 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54003.524679 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54003.524679 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54003.524679 # average overall mshr miss latency
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.tags.replacements 1395422 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.982303 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 13764943 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1395934 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 9.860741 # Average number of references to valid blocks.
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.dcache.tags.warmup_cycle 86814250 # Cycle when the warmup percentage was hit.
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.tags.occ_blocks::cpu.inst 511.982303 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.inst 0.999965 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999965 # Average percentage of cache occupancy
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 232 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 233 # Occupied blocks per task id
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.tags.tag_accesses 63626016 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 63626016 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.inst 7806784 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 7806784 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.inst 5576432 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 5576432 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.inst 182707 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 182707 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.inst 198983 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 198983 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.inst 13383216 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 13383216 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.inst 13383216 # number of overall hits
system.cpu.dcache.overall_hits::total 13383216 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.inst 1201616 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1201616 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.inst 573699 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 573699 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.inst 17299 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 17299 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.inst 1775315 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1775315 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.inst 1775315 # number of overall misses
system.cpu.dcache.overall_misses::total 1775315 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 31018318500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 31018318500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20748316044 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 20748316044 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 231689250 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 231689250 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.inst 51766634544 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 51766634544 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.inst 51766634544 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 51766634544 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.inst 9008400 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 9008400 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.inst 6150131 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 6150131 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 200006 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 200006 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.inst 198983 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 198983 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.inst 15158531 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 15158531 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.inst 15158531 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 15158531 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.133388 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.133388 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.093282 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.093282 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.086492 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086492 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.inst 0.117117 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.117117 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.inst 0.117117 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.117117 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25813.836117 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 25813.836117 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 36165.857085 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 36165.857085 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13393.216371 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13393.216371 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29159.126433 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 29159.126433 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29159.126433 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 29159.126433 # average overall miss latency
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.writebacks::writebacks 838282 # number of writebacks
system.cpu.dcache.writebacks::total 838282 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 127187 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 127187 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 269448 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 269448 # number of WriteReq MSHR hits
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.demand_mshr_hits::cpu.inst 396635 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 396635 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.inst 396635 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 396635 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1074429 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1074429 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 304251 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 304251 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 17296 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 17296 # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.inst 1378680 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1378680 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.inst 1378680 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1378680 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 26906996250 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 26906996250 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10272860843 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 10272860843 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 196930250 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 196930250 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 37179857093 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 37179857093 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 37179857093 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 37179857093 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 1423313500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423313500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 2002790500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2002790500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 3426104000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 3426104000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.119270 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119270 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.049471 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049471 # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.086477 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086477 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.090951 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.090951 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.090951 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.090951 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 25043.065898 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25043.065898 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 33764.427538 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33764.427538 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11385.884019 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11385.884019 # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26967.720641 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26967.720641 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26967.720641 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26967.720641 # average overall mshr miss latency
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink