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gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt

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cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
---------- Begin Simulation Statistics ----------
final_tick 1884223823500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
host_inst_rate 205086 # Simulator instruction rate (inst/s)
host_mem_usage 329500 # Number of bytes of host memory used
host_op_rate 205086 # Simulator op (including micro ops) rate (op/s)
host_seconds 273.72 # Real time elapsed on the host
host_tick_rate 6883774376 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 56136190 # Number of instructions simulated
sim_ops 56136190 # Number of ops (including micro ops) simulated
sim_seconds 1.884224 # Number of seconds simulated
sim_ticks 1884223823500 # Number of ticks simulated
system.clk_domain.clock 1000 # Clock period in ticks
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 52.670853 # BTB Hit Percentage
system.cpu.branchPred.BTBHits 5198600 # Number of BTB hits
system.cpu.branchPred.BTBLookups 9869975 # Number of BTB lookups
system.cpu.branchPred.RASInCorrect 32078 # Number of incorrect RAS predictions.
system.cpu.branchPred.condIncorrect 374087 # Number of conditional branches incorrect
system.cpu.branchPred.condPredicted 13023618 # Number of conditional branches predicted
system.cpu.branchPred.lookups 15007194 # Number of BP lookups
system.cpu.branchPred.usedRAS 808258 # Number of times the RAS was used to get a target.
system.cpu.committedInsts 56136190 # Number of instructions committed
system.cpu.committedOps 56136190 # Number of ops (including micro ops) committed
system.cpu.cpi 3.109494 # CPI: cycles per instruction
system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 200029 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 200029 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13395.968165 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13395.968165 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11388.427222 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11388.427222 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_hits::cpu.inst 182878 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 182878 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 229754250 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 229754250 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.085743 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085743 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_misses::cpu.inst 17151 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 17151 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 195288750 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 195288750 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.085728 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085728 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 17148 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 17148 # number of LoadLockedReq MSHR misses
system.cpu.dcache.ReadReq_accesses::cpu.inst 9013279 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 9013279 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25759.364421 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 25759.364421 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 25018.369561 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25018.369561 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_hits::cpu.inst 7812296 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 7812296 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 30936558760 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 30936558760 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.133246 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.133246 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses::cpu.inst 1200983 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1200983 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 127128 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 127128 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 26866101245 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 26866101245 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.119141 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119141 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1073855 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1073855 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 1423421000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423421000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.StoreCondReq_accesses::cpu.inst 199007 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 199007 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_hits::cpu.inst 199007 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 199007 # number of StoreCondReq hits
system.cpu.dcache.WriteReq_accesses::cpu.inst 6151468 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 6151468 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 36155.340979 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 36155.340979 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 33789.156794 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33789.156794 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_hits::cpu.inst 5578034 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 5578034 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20732701799 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 20732701799 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.093219 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.093219 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses::cpu.inst 573434 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 573434 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 269372 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 269372 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10273998593 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 10273998593 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.049429 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049429 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 304062 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 304062 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 2002985000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2002985000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses::cpu.inst 15164747 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 15164747 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29119.006727 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 29119.006727 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26953.800438 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26953.800438 # average overall mshr miss latency
system.cpu.dcache.demand_hits::cpu.inst 13390330 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 13390330 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency::cpu.inst 51669260559 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 51669260559 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate::cpu.inst 0.117009 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.117009 # miss rate for demand accesses
system.cpu.dcache.demand_misses::cpu.inst 1774417 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1774417 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits::cpu.inst 396500 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 396500 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 37140099838 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 37140099838 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.090863 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.090863 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses::cpu.inst 1377917 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1377917 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses::cpu.inst 15164747 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 15164747 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29119.006727 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 29119.006727 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26953.800438 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26953.800438 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits::cpu.inst 13390330 # number of overall hits
system.cpu.dcache.overall_hits::total 13390330 # number of overall hits
system.cpu.dcache.overall_miss_latency::cpu.inst 51669260559 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 51669260559 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate::cpu.inst 0.117009 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.117009 # miss rate for overall accesses
system.cpu.dcache.overall_misses::cpu.inst 1774417 # number of overall misses
system.cpu.dcache.overall_misses::total 1774417 # number of overall misses
system.cpu.dcache.overall_mshr_hits::cpu.inst 396500 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 396500 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 37140099838 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 37140099838 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.090863 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.090863 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses::cpu.inst 1377917 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1377917 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 3426406000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 3426406000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id
system.cpu.dcache.tags.avg_refs 9.872403 # Average number of references to valid blocks.
system.cpu.dcache.tags.data_accesses 63650159 # Number of data accesses
system.cpu.dcache.tags.occ_blocks::cpu.inst 511.982305 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.inst 0.999965 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999965 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.replacements 1394513 # number of replacements
system.cpu.dcache.tags.sampled_refs 1395025 # Sample count of references to valid blocks.
system.cpu.dcache.tags.tag_accesses 63650159 # Number of tag accesses
system.cpu.dcache.tags.tagsinuse 511.982305 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 13772249 # Total number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 86814250 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks::writebacks 837448 # number of writebacks
system.cpu.dcache.writebacks::total 837448 # number of writebacks
system.cpu.discardedOps 2565798 # Number of ops (including micro ops) which were discarded before commit
system.cpu.dtb.data_accesses 1069353 # DTB accesses
system.cpu.dtb.data_acv 370 # DTB access violations
system.cpu.dtb.data_hits 15629370 # DTB hits
system.cpu.dtb.data_misses 21396 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 770885 # DTB read accesses
system.cpu.dtb.read_acv 211 # DTB read access violations
system.cpu.dtb.read_hits 9243246 # DTB read hits
system.cpu.dtb.read_misses 19107 # DTB read misses
system.cpu.dtb.write_accesses 298468 # DTB write accesses
system.cpu.dtb.write_acv 159 # DTB write access violations
system.cpu.dtb.write_hits 6386124 # DTB write hits
system.cpu.dtb.write_misses 2289 # DTB write misses
system.cpu.icache.ReadReq_accesses::cpu.inst 20425038 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 20425038 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13727.021807 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13727.021807 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11722.006480 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11722.006480 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits::cpu.inst 18964885 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 18964885 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency::cpu.inst 20043552072 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 20043552072 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071488 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.071488 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses::cpu.inst 1460153 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1460153 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17115922928 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 17115922928 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071488 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071488 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1460153 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1460153 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses::cpu.inst 20425038 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 20425038 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13727.021807 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13727.021807 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11722.006480 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11722.006480 # average overall mshr miss latency
system.cpu.icache.demand_hits::cpu.inst 18964885 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 18964885 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency::cpu.inst 20043552072 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 20043552072 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate::cpu.inst 0.071488 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.071488 # miss rate for demand accesses
system.cpu.icache.demand_misses::cpu.inst 1460153 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1460153 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17115922928 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 17115922928 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071488 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.071488 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses::cpu.inst 1460153 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1460153 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses::cpu.inst 20425038 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 20425038 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13727.021807 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13727.021807 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11722.006480 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11722.006480 # average overall mshr miss latency
system.cpu.icache.overall_hits::cpu.inst 18964885 # number of overall hits
system.cpu.icache.overall_hits::total 18964885 # number of overall hits
system.cpu.icache.overall_miss_latency::cpu.inst 20043552072 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 20043552072 # number of overall miss cycles
system.cpu.icache.overall_miss_rate::cpu.inst 0.071488 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.071488 # miss rate for overall accesses
system.cpu.icache.overall_misses::cpu.inst 1460153 # number of overall misses
system.cpu.icache.overall_misses::total 1460153 # number of overall misses
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17115922928 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 17115922928 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071488 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.071488 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses::cpu.inst 1460153 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1460153 # number of overall MSHR misses
system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 386 # Occupied blocks per task id
system.cpu.icache.tags.avg_refs 12.989850 # Average number of references to valid blocks.
system.cpu.icache.tags.data_accesses 21885191 # Number of data accesses
system.cpu.icache.tags.occ_blocks::cpu.inst 509.631985 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.995375 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.995375 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
system.cpu.icache.tags.replacements 1459466 # number of replacements
system.cpu.icache.tags.sampled_refs 1459977 # Sample count of references to valid blocks.
system.cpu.icache.tags.tag_accesses 21885191 # Number of tag accesses
system.cpu.icache.tags.tagsinuse 509.631985 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 18964882 # Total number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 31504045250 # Cycle when the warmup percentage was hit.
system.cpu.idleCycles 90671171 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.ipc 0.321596 # IPC: instructions per cycle
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 4018394 # ITB accesses
system.cpu.itb.fetch_acv 700 # ITB acv
system.cpu.itb.fetch_hits 4011544 # ITB hits
system.cpu.itb.fetch_misses 6850 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::swpctx 4177 2.17% 2.17% # number of callpals executed
system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
system.cpu.kern.callpal::swpipl 175531 91.22% 93.43% # number of callpals executed
system.cpu.kern.callpal::rdps 6804 3.54% 96.96% # number of callpals executed
system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed
system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal::rti 5126 2.66% 99.64% # number of callpals executed
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
system.cpu.kern.callpal::total 192418 # number of callpals executed
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.hwrei 211480 # number of hwrei instructions executed
system.cpu.kern.inst.quiesce 6384 # number of quiesce instructions executed
system.cpu.kern.ipl_count::0 74792 40.94% 40.94% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22 1901 1.04% 42.05% # number of times we switched to this ipl
system.cpu.kern.ipl_count::31 105866 57.95% 100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_count::total 182690 # number of times we switched to this ipl
system.cpu.kern.ipl_good::0 73425 49.32% 49.32% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22 1901 1.28% 50.68% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31 73425 49.32% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total 148882 # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks::0 1833909486500 97.33% 97.33% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21 80399500 0.00% 97.33% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22 673524500 0.04% 97.37% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31 49559388000 2.63% 100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total 1884222798500 # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::31 0.693565 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::total 0.814943 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.mode_good::kernel 1910
system.cpu.kern.mode_good::user 1740
system.cpu.kern.mode_good::idle 170
system.cpu.kern.mode_switch::kernel 5873 # number of protection mode switches
system.cpu.kern.mode_switch::user 1740 # number of protection mode switches
system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches
system.cpu.kern.mode_switch_good::kernel 0.325217 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total 0.393449 # fraction of useful protection mode switches
system.cpu.kern.mode_ticks::kernel 36228247000 1.92% 1.92% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user 4082723500 0.22% 2.14% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle 1843911818000 97.86% 100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context 4178 # number of times the context was actually changed
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
system.cpu.kern.syscall::total 326 # number of syscalls executed
system.cpu.l2cache.ReadExReq_accesses::cpu.inst 304079 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 304079 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69348.639186 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69348.639186 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56485.106925 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56485.106925 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits::cpu.inst 187390 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 187390 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 8092223358 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 8092223358 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.383746 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.383746 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses::cpu.inst 116689 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 116689 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6591190642 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6591190642 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.383746 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383746 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 116689 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 116689 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses::cpu.inst 2551058 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 2551058 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65542.886814 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 65542.886814 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53041.655311 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53041.655311 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_hits::cpu.inst 2262409 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2262409 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18918888736 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 18918888736 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.113149 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.113149 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses::cpu.inst 288649 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 288649 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15310420764 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15310420764 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113149 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.113149 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 288649 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 288649 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1333330000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333330000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 21 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 21 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 12646.882353 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12646.882353 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 15971.411765 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15971.411765 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_hits::cpu.inst 4 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 214997 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 214997 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.809524 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.809524 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses::cpu.inst 17 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 17 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 271514 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 271514 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.809524 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.809524 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 17 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 17 # number of UpgradeReq MSHR misses
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 1887556500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1887556500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.Writeback_accesses::writebacks 837448 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 837448 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits::writebacks 837448 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 837448 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses::cpu.inst 2855137 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2855137 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66638.489591 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 66638.489591 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54032.958681 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54032.958681 # average overall mshr miss latency
system.cpu.l2cache.demand_hits::cpu.inst 2449799 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2449799 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency::cpu.inst 27011112094 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 27011112094 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.141968 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.141968 # miss rate for demand accesses
system.cpu.l2cache.demand_misses::cpu.inst 405338 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 405338 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21901611406 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 21901611406 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.141968 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.141968 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 405338 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 405338 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses::cpu.inst 2855137 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2855137 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66638.489591 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 66638.489591 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54032.958681 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54032.958681 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits::cpu.inst 2449799 # number of overall hits
system.cpu.l2cache.overall_hits::total 2449799 # number of overall hits
system.cpu.l2cache.overall_miss_latency::cpu.inst 27011112094 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 27011112094 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.141968 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.141968 # miss rate for overall accesses
system.cpu.l2cache.overall_misses::cpu.inst 405338 # number of overall misses
system.cpu.l2cache.overall_misses::total 405338 # number of overall misses
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21901611406 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 21901611406 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.141968 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.141968 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 405338 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 405338 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3220886500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3220886500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1457 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5165 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2777 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55533 # Occupied blocks per task id
system.cpu.l2cache.tags.avg_refs 7.369819 # Average number of references to valid blocks.
system.cpu.l2cache.tags.data_accesses 30249758 # Number of data accesses
system.cpu.l2cache.tags.occ_blocks::writebacks 54473.589189 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 10850.670788 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.831201 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.165568 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.996769 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.replacements 339425 # number of replacements
system.cpu.l2cache.tags.sampled_refs 404587 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.tag_accesses 30249758 # Number of tag accesses
system.cpu.l2cache.tags.tagsinuse 65324.259976 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 2981733 # Total number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 5872511750 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks::writebacks 76620 # number of writebacks
system.cpu.l2cache.writebacks::total 76620 # number of writebacks
system.cpu.numCycles 174555159 # number of cpu cycles simulated
system.cpu.numFetchSuspends 5529 # Number of times Execute suspended instruction fetching
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.quiesceCycles 3593892488 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.tickCycles 83883988 # Number of cycles that the CPU actually ticked
system.cpu.toL2Bus.data_through_bus 236368668 # Total data (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2920246 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3660834 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 6581080 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 2696865499 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 2193891072 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 2193491412 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy 237000 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.snoop_data_through_bus 13952 # Total snoop data (bytes)
system.cpu.toL2Bus.throughput 125453578 # Throughput (bytes/s)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93445952 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142932828 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 236378780 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.trans_dist::ReadReq 2558221 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2558187 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 9619 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 9619 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 837448 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 345631 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 304081 # Transaction distribution
system.cpu.toL2Bus.trans_dist::BadAddressError 17 # Transaction distribution
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.iobus.data_through_bus 2705924 # Total data (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5094 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 33098 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 116548 # Packet count per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 4705000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer29.occupancy 380176812 # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 23479000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer1.occupancy 43191500 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.throughput 1436095 # Throughput (bytes/s)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20376 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total 44316 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total 2705924 # Cumulative packet size per connected master and slave (bytes)
system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
system.iobus.trans_dist::WriteReq 51171 # Transaction distribution
system.iobus.trans_dist::WriteResp 51171 # Transaction distribution
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122164.063584 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 122164.063584 # average ReadReq miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70158.283237 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 70158.283237 # average ReadReq mshr miss latency
system.iocache.ReadReq_miss_latency::tsunami.ide 21134383 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 21134383 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12137383 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 12137383 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 301458.532177 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 301458.532177 # average WriteReq miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 249403.998099 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 249403.998099 # average WriteReq mshr miss latency
system.iocache.WriteReq_miss_latency::tsunami.ide 12526204929 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 12526204929 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10363234929 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 10363234929 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
system.iocache.avg_blocked_cycles::no_mshrs 12.981557 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.blocked::no_mshrs 28683 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_mshrs 372350 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
system.iocache.demand_avg_miss_latency::tsunami.ide 300715.142289 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 300715.142289 # average overall miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 248660.810354 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 248660.810354 # average overall mshr miss latency
system.iocache.demand_miss_latency::tsunami.ide 12547339312 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 12547339312 # number of demand (read+write) miss cycles
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
system.iocache.demand_mshr_miss_latency::tsunami.ide 10375372312 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 10375372312 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
system.iocache.overall_avg_miss_latency::tsunami.ide 300715.142289 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 300715.142289 # average overall miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 248660.810354 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 248660.810354 # average overall mshr miss latency
system.iocache.overall_miss_latency::tsunami.ide 12547339312 # number of overall miss cycles
system.iocache.overall_miss_latency::total 12547339312 # number of overall miss cycles
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
system.iocache.overall_misses::total 41725 # number of overall misses
system.iocache.overall_mshr_miss_latency::tsunami.ide 10375372312 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 10375372312 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.data_accesses 375525 # Number of data accesses
system.iocache.tags.occ_blocks::tsunami.ide 1.296002 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide 0.081000 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.081000 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.replacements 41685 # number of replacements
system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.tags.tag_accesses 375525 # Number of tag accesses
system.iocache.tags.tagsinuse 1.296002 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.warmup_cycle 1728023406000 # Cycle when the warmup percentage was hit.
system.iocache.writebacks::writebacks 41512 # number of writebacks
system.iocache.writebacks::total 41512 # number of writebacks
system.membus.data_through_bus 36171420 # Total data (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33098 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887021 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 34 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920153 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124680 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 124680 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1044833 # Packet count per connected master and slave (bytes)
system.membus.reqLayer0.occupancy 29924500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 1588463750 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
system.membus.reqLayer2.occupancy 21000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 3825251579 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.respLayer2.occupancy 376658500 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.snoop_data_through_bus 35520 # Total snoop data (bytes)
system.membus.throughput 19215838 # Throughput (bytes/s)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44316 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30817984 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30862300 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309120 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 5309120 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 36171420 # Cumulative packet size per connected master and slave (bytes)
system.membus.trans_dist::ReadReq 295752 # Transaction distribution
system.membus.trans_dist::ReadResp 295735 # Transaction distribution
system.membus.trans_dist::WriteReq 9619 # Transaction distribution
system.membus.trans_dist::WriteResp 9619 # Transaction distribution
system.membus.trans_dist::Writeback 118132 # Transaction distribution
system.membus.trans_dist::UpgradeReq 154 # Transaction distribution
system.membus.trans_dist::UpgradeResp 154 # Transaction distribution
system.membus.trans_dist::ReadExReq 158104 # Transaction distribution
system.membus.trans_dist::ReadExResp 158104 # Transaction distribution
system.membus.trans_dist::BadAddressError 17 # Transaction distribution
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgGap 3337930.50 # Average gap between requests
system.physmem.avgMemAccLat 35387.14 # Average memory access latency per DRAM burst
system.physmem.avgQLat 16637.14 # Average queueing delay per DRAM burst
system.physmem.avgRdBW 15.16 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgRdBWSys 15.16 # Average system read bandwidth in MiByte/s
system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
system.physmem.avgWrBW 4.01 # Average achieved write bandwidth in MiByte/s
system.physmem.avgWrBWSys 4.01 # Average system write bandwidth in MiByte/s
system.physmem.avgWrQLen 25.04 # Average write queue length when enqueuing
system.physmem.busUtil 0.15 # Data bus utilization in percentage
system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
system.physmem.bw_inst_read::cpu.inst 558643 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 558643 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 13753305 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 1407663 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 15160967 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 4012500 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 13753305 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1407663 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 19173467 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_write::writebacks 4012500 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 4012500 # Write bandwidth from this memory (bytes/s)
system.physmem.bytesPerActivate::samples 65544 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 551.049921 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 339.619427 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 417.892498 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 14350 21.89% 21.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 10693 16.31% 38.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 5022 7.66% 45.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3000 4.58% 50.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2439 3.72% 54.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 2123 3.24% 57.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1392 2.12% 59.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1695 2.59% 62.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 24830 37.88% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 65544 # Bytes accessed per row activation
system.physmem.bytesReadDRAM 28559488 # Total number of bytes read from DRAM
system.physmem.bytesReadSys 28566656 # Total read bytes from the system interface side
system.physmem.bytesReadWrQ 7168 # Total number of bytes read from write queue
system.physmem.bytesWritten 7558528 # Total number of bytes written to DRAM
system.physmem.bytesWrittenSys 7560448 # Total written bytes from the system interface side
system.physmem.bytes_inst_read::cpu.inst 1052608 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1052608 # Number of instructions bytes read from this memory
system.physmem.bytes_read::cpu.inst 25914304 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory
system.physmem.bytes_read::total 28566656 # Number of bytes read from this memory
system.physmem.bytes_written::writebacks 7560448 # Number of bytes written to this memory
system.physmem.bytes_written::total 7560448 # Number of bytes written to this memory
system.physmem.memoryStateTime::IDLE 1774858406250 # Time in different power states
system.physmem.memoryStateTime::REF 62918180000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 46441683750 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 152 # Number of requests that are neither read nor write
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 9 # Number of times write queue was full causing retry
system.physmem.num_reads::cpu.inst 404911 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory
system.physmem.num_reads::total 446354 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 118132 # Number of write requests responded to by this memory
system.physmem.num_writes::total 118132 # Number of write requests responded to by this memory
system.physmem.pageHitRate 88.38 # Row buffer hit rate, read and write combined
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.perBankRdBursts::0 28089 # Per bank write bursts
system.physmem.perBankRdBursts::1 28214 # Per bank write bursts
system.physmem.perBankRdBursts::2 28576 # Per bank write bursts
system.physmem.perBankRdBursts::3 28273 # Per bank write bursts
system.physmem.perBankRdBursts::4 27773 # Per bank write bursts
system.physmem.perBankRdBursts::5 27528 # Per bank write bursts
system.physmem.perBankRdBursts::6 27276 # Per bank write bursts
system.physmem.perBankRdBursts::7 26988 # Per bank write bursts
system.physmem.perBankRdBursts::8 27824 # Per bank write bursts
system.physmem.perBankRdBursts::9 27526 # Per bank write bursts
system.physmem.perBankRdBursts::10 28068 # Per bank write bursts
system.physmem.perBankRdBursts::11 27422 # Per bank write bursts
system.physmem.perBankRdBursts::12 27509 # Per bank write bursts
system.physmem.perBankRdBursts::13 28403 # Per bank write bursts
system.physmem.perBankRdBursts::14 28310 # Per bank write bursts
system.physmem.perBankRdBursts::15 28463 # Per bank write bursts
system.physmem.perBankWrBursts::0 7815 # Per bank write bursts
system.physmem.perBankWrBursts::1 7669 # Per bank write bursts
system.physmem.perBankWrBursts::2 8056 # Per bank write bursts
system.physmem.perBankWrBursts::3 7732 # Per bank write bursts
system.physmem.perBankWrBursts::4 7316 # Per bank write bursts
system.physmem.perBankWrBursts::5 6956 # Per bank write bursts
system.physmem.perBankWrBursts::6 6791 # Per bank write bursts
system.physmem.perBankWrBursts::7 6409 # Per bank write bursts
system.physmem.perBankWrBursts::8 7232 # Per bank write bursts
system.physmem.perBankWrBursts::9 6875 # Per bank write bursts
system.physmem.perBankWrBursts::10 7393 # Per bank write bursts
system.physmem.perBankWrBursts::11 6865 # Per bank write bursts
system.physmem.perBankWrBursts::12 7044 # Per bank write bursts
system.physmem.perBankWrBursts::13 8010 # Per bank write bursts
system.physmem.perBankWrBursts::14 7992 # Per bank write bursts
system.physmem.perBankWrBursts::15 7947 # Per bank write bursts
system.physmem.rdPerTurnAround::samples 6969 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 64.029703 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean 16.504435 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 2530.006276 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-8191 6966 99.96% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 6969 # Reads before turning the bus around for writes
system.physmem.rdQLenPdf::0 402867 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 3807 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 2662 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 1230 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1958 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 4351 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 3967 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 4001 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 2558 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 2209 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 2170 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 2129 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1643 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1639 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1928 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 1884 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 2114 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 1233 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 977 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 904 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.readBursts 446354 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 446354 # Read request sizes (log2)
system.physmem.readReqs 446354 # Number of read requests accepted
system.physmem.readRowHitRate 90.24 # Row buffer hit rate for reads
system.physmem.readRowHits 402699 # Number of row buffer hits during reads
system.physmem.servicedByWrQ 112 # Number of DRAM read bursts serviced by the write queue
system.physmem.totBusLat 2231210000 # Total ticks spent in databus transfers
system.physmem.totGap 1884215033500 # Total gap between requests
system.physmem.totMemAccLat 15791226000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totQLat 7424188500 # Total ticks spent queuing
system.physmem.wrPerTurnAround::samples 6969 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 16.946764 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.727841 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 3.644099 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 5693 81.69% 81.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17 31 0.44% 82.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 825 11.84% 93.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 64 0.92% 94.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 11 0.16% 95.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21 13 0.19% 95.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22 18 0.26% 95.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23 88 1.26% 96.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24 18 0.26% 97.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25 42 0.60% 97.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26 18 0.26% 97.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27 17 0.24% 98.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28 12 0.17% 98.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::29 10 0.14% 98.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30 5 0.07% 98.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::31 20 0.29% 98.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32 11 0.16% 98.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::34 4 0.06% 99.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::35 1 0.01% 99.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36 5 0.07% 99.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::37 3 0.04% 99.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::38 1 0.01% 99.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::39 1 0.01% 99.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40 4 0.06% 99.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::41 6 0.09% 99.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::42 2 0.03% 99.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::43 5 0.07% 99.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44 3 0.04% 99.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::45 2 0.03% 99.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::46 1 0.01% 99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::47 5 0.07% 99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48 2 0.03% 99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::49 5 0.07% 99.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::50 3 0.04% 99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::51 1 0.01% 99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52 3 0.04% 99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::53 1 0.01% 99.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56 5 0.07% 99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::57 7 0.10% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::58 3 0.04% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 6969 # Writes before turning the bus around for reads
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 1009 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 1042 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 4658 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 4777 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 4795 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 4798 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 4808 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 4914 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 5074 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 5164 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 5341 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 5549 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 5533 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 5670 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 5729 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 5848 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 5831 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 5897 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 883 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 930 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 931 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 875 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 964 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 972 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 1055 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 993 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 1195 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 1241 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 1213 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 1337 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 1445 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 1603 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 1865 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 2061 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 1878 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 1829 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 1679 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 1682 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 1830 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 1627 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 808 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 356 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 190 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 127 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 36 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 29 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 17 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see
system.physmem.writeBursts 118132 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 118132 # Write request sizes (log2)
system.physmem.writeReqs 118132 # Number of write requests accepted
system.physmem.writeRowHitRate 81.35 # Row buffer hit rate for writes
system.physmem.writeRowHits 96101 # Number of row buffer hits during writes
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.voltage_domain.voltage 1 # Voltage in Volts
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink