2006-04-13 11:42:18 +02:00
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/*
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2007-11-15 20:17:21 +01:00
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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2006-04-13 11:42:18 +02:00
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*
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2007-11-15 20:17:21 +01:00
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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2006-04-13 11:42:18 +02:00
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*
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2007-11-15 20:17:21 +01:00
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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2006-06-01 01:26:56 +02:00
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*
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2007-11-15 20:17:21 +01:00
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* Authors: Korey Sewell
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2006-04-13 11:42:18 +02:00
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*/
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2006-05-08 00:50:41 +02:00
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#ifndef __ARCH_MIPS_TYPES_HH__
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#define __ARCH_MIPS_TYPES_HH__
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2006-04-13 11:42:18 +02:00
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2006-05-08 00:50:41 +02:00
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#include "sim/host.hh"
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namespace MipsISA
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{
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typedef uint32_t MachInst;
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typedef uint64_t ExtMachInst;
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2007-11-13 22:58:16 +01:00
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typedef uint16_t RegIndex;
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2006-05-08 00:50:41 +02:00
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typedef uint32_t IntReg;
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2007-02-12 19:06:30 +01:00
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typedef uint64_t LargestRead;
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2006-05-08 00:50:41 +02:00
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// floating point register file entry type
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typedef uint32_t FloatReg32;
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typedef uint64_t FloatReg64;
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typedef uint64_t FloatRegBits;
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2006-06-15 07:00:15 +02:00
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typedef double FloatRegVal;
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typedef double FloatReg;
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2006-05-08 00:50:41 +02:00
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// cop-0/cop-1 system control register
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typedef uint64_t MiscReg;
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typedef union {
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IntReg intreg;
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FloatReg fpreg;
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MiscReg ctrlreg;
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} AnyReg;
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2006-04-13 11:42:18 +02:00
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2006-05-08 00:50:41 +02:00
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//used in FP convert & round function
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enum ConvertType{
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SINGLE_TO_DOUBLE,
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SINGLE_TO_WORD,
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SINGLE_TO_LONG,
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DOUBLE_TO_SINGLE,
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DOUBLE_TO_WORD,
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DOUBLE_TO_LONG,
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LONG_TO_SINGLE,
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LONG_TO_DOUBLE,
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LONG_TO_WORD,
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2006-05-11 02:54:03 +02:00
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LONG_TO_PS,
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WORD_TO_SINGLE,
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WORD_TO_DOUBLE,
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WORD_TO_LONG,
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WORD_TO_PS,
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2006-05-11 02:54:03 +02:00
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PL_TO_SINGLE,
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PU_TO_SINGLE
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};
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//used in FP convert & round function
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enum RoundMode{
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RND_ZERO,
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RND_DOWN,
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RND_UP,
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RND_NEAREST
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2007-11-13 22:58:16 +01:00
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};
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2007-08-27 05:33:57 +02:00
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2007-11-15 20:17:21 +01:00
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struct CoreSpecific {
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/* Note: It looks like it will be better to allow simulator users
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to specify the values of individual variables instead of requiring
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users to define the values of entire registers
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Especially since a lot of these variables can be created from other
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user parameters (cache descriptions)
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-jpp
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*/
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// MIPS CP0 State - First individual variables
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// Page numbers refer to revision 2.50 (July 2005) of the MIPS32 ARM, Volume III (PRA)
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unsigned CP0_IntCtl_IPTI; // Page 93, IP Timer Interrupt
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unsigned CP0_IntCtl_IPPCI; // Page 94, IP Performance Counter Interrupt
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unsigned CP0_SrsCtl_HSS; // Page 95, Highest Implemented Shadow Set
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unsigned CP0_PRId_CompanyOptions; // Page 105, Manufacture options
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unsigned CP0_PRId_CompanyID; // Page 105, Company ID - (0-255, 1=>MIPS)
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unsigned CP0_PRId_ProcessorID; // Page 105
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unsigned CP0_PRId_Revision; // Page 105
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unsigned CP0_EBase_CPUNum; // Page 106, CPU Number in a multiprocessor system
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unsigned CP0_Config_BE; // Page 108, Big/Little Endian mode
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unsigned CP0_Config_AT; //Page 109
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unsigned CP0_Config_AR; //Page 109
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unsigned CP0_Config_MT; //Page 109
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unsigned CP0_Config_VI; //Page 109
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unsigned CP0_Config1_M; // Page 110
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unsigned CP0_Config1_MMU; // Page 110
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unsigned CP0_Config1_IS; // Page 110
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unsigned CP0_Config1_IL; // Page 111
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unsigned CP0_Config1_IA; // Page 111
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unsigned CP0_Config1_DS; // Page 111
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unsigned CP0_Config1_DL; // Page 112
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unsigned CP0_Config1_DA; // Page 112
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bool CP0_Config1_C2; // Page 112
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bool CP0_Config1_MD;// Page 112 - Technically not used in MIPS32
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bool CP0_Config1_PC;// Page 112
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bool CP0_Config1_WR;// Page 113
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bool CP0_Config1_CA;// Page 113
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bool CP0_Config1_EP;// Page 113
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bool CP0_Config1_FP;// Page 113
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bool CP0_Config2_M; // Page 114
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unsigned CP0_Config2_TU;// Page 114
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unsigned CP0_Config2_TS;// Page 114
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unsigned CP0_Config2_TL;// Page 115
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unsigned CP0_Config2_TA;// Page 115
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unsigned CP0_Config2_SU;// Page 115
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unsigned CP0_Config2_SS;// Page 115
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unsigned CP0_Config2_SL;// Page 116
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unsigned CP0_Config2_SA;// Page 116
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bool CP0_Config3_M; //// Page 117
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bool CP0_Config3_DSPP;// Page 117
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bool CP0_Config3_LPA;// Page 117
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bool CP0_Config3_VEIC;// Page 118
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bool CP0_Config3_VInt; // Page 118
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bool CP0_Config3_SP;// Page 118
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bool CP0_Config3_MT;// Page 119
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bool CP0_Config3_SM;// Page 119
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bool CP0_Config3_TL;// Page 119
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bool CP0_WatchHi_M; // Page 124
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bool CP0_PerfCtr_M; // Page 130
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bool CP0_PerfCtr_W; // Page 130
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// Then, whole registers
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unsigned CP0_PRId;
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unsigned CP0_Config;
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unsigned CP0_Config1;
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unsigned CP0_Config2;
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unsigned CP0_Config3;
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};
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2006-05-08 00:50:41 +02:00
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} // namespace MipsISA
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#endif
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