2006-04-06 06:51:46 +02:00
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/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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2006-06-01 01:26:56 +02:00
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*
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* Authors: Ali Saidi
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2006-04-06 06:51:46 +02:00
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*/
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/**
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2006-08-15 01:25:07 +02:00
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* @file
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* Port object definitions.
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2006-04-06 06:51:46 +02:00
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*/
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#include "base/chunk_generator.hh"
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2009-09-23 17:34:21 +02:00
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#include "config/the_isa.hh"
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2007-02-19 01:57:46 +01:00
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#include "cpu/thread_context.hh"
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2006-04-06 06:51:46 +02:00
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#include "mem/vport.hh"
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void
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VirtualPort::readBlob(Addr addr, uint8_t *p, int size)
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{
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Addr paddr;
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for (ChunkGenerator gen(addr, size, TheISA::PageBytes); !gen.done();
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gen.next())
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{
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2006-06-06 23:32:21 +02:00
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if (tc)
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paddr = TheISA::vtophys(tc,gen.addr());
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2006-04-06 06:51:46 +02:00
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else
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paddr = TheISA::vtophys(gen.addr());
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FunctionalPort::readBlob(paddr, p, gen.size());
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p += gen.size();
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}
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}
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void
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VirtualPort::writeBlob(Addr addr, uint8_t *p, int size)
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{
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Addr paddr;
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for (ChunkGenerator gen(addr, size, TheISA::PageBytes); !gen.done();
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gen.next())
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{
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2006-06-06 23:32:21 +02:00
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if (tc)
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paddr = TheISA::vtophys(tc,gen.addr());
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2006-04-06 06:51:46 +02:00
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else
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paddr = TheISA::vtophys(gen.addr());
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FunctionalPort::writeBlob(paddr, p, gen.size());
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p += gen.size();
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}
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}
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2007-02-19 01:57:46 +01:00
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void
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CopyOut(ThreadContext *tc, void *dest, Addr src, size_t cplen)
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{
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uint8_t *dst = (uint8_t *)dest;
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2008-07-01 16:24:19 +02:00
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VirtualPort *vp = tc->getVirtPort();
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2007-02-19 01:57:46 +01:00
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vp->readBlob(src, dst, cplen);
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}
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void
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CopyIn(ThreadContext *tc, Addr dest, void *source, size_t cplen)
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{
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uint8_t *src = (uint8_t *)source;
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2008-07-01 16:24:19 +02:00
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VirtualPort *vp = tc->getVirtPort();
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2007-02-19 01:57:46 +01:00
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vp->writeBlob(dest, src, cplen);
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}
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void
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CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen)
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{
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int len = 0;
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char *start = dst;
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2008-07-01 16:24:19 +02:00
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VirtualPort *vp = tc->getVirtPort();
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2007-02-19 01:57:46 +01:00
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do {
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vp->readBlob(vaddr++, (uint8_t*)dst++, 1);
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} while (len < maxlen && start[len++] != 0 );
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dst[len] = 0;
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}
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void
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CopyStringIn(ThreadContext *tc, char *src, Addr vaddr)
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{
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2008-07-01 16:24:19 +02:00
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VirtualPort *vp = tc->getVirtPort();
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2007-02-19 01:57:46 +01:00
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for (ChunkGenerator gen(vaddr, strlen(src), TheISA::PageBytes); !gen.done();
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gen.next())
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{
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vp->writeBlob(gen.addr(), (uint8_t*)src, gen.size());
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src += gen.size();
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}
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}
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