66 lines
2.4 KiB
Text
66 lines
2.4 KiB
Text
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This directory contains a connector that allows gem5 to be used as a
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component in SST (Structural Simulation Toolkit, sst-simulator.org). More
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specifically, it creates a .so that wraps the libgem5_*.so library. At a
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high level, this allows memory traffic to pass between the two simulators.
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SST Links are roughly analogous to gem5 Ports, although Links do not have
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a notion of master and slave. This distinction is important to gem5, so
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when connecting a gem5 CPU to an SST cache, an ExternalSlave must be used,
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and similarly when connecting the memory side of SST cache to a gem5 port
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(for memory <-> I/O), an ExternalMaster must be used.
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The connector handles the administrative aspects of gem5
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(initialization, simulation, shutdown) as well as translating
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SST's MemEvents into gem5 Packets and vice-versa.
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Step-by-step instructions:
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0. install SST and its dependencies
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Note: the Makefile assumes you installed from an SVN checkout, not a release.
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If you install a release, modify SST_VERSION at the top of the Makefile.
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0b. set/append to the PKG_CONFIG_PATH variable the path where SST installed
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its pkgconfig, if not in a system-wide location.
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Then from gem5 root:
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1. build gem5 library:
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% scons build/ARM/libgem5_opt.so
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Note: if you would rather use a fast, debug, etc. variant instead,
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modify GEM5_LIB at the top of the Makefile.
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2. build gem5 SST component:
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% make -C ext/sst
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3. run SST like so:
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% sst --add-lib-path <path to ./ext/sst> <config script, e.g. ext/sst/*.py>
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===========
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Note: if you want to use an arch other than ARM (not tested/supported),
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tweak the Makefile to get includes from that build directory instead.
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===========
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This directory provides:
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1. an SST "Component" for gem5;
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2. a class that implements gem5's "ExternalMaster" interface to connect with
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SST "Link"s exchanging "memEvents"
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(sst/elements/memHierarchy stuff - caches, memories, etc.)
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This lets gem5 receive packets from SST, as in
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an SST LL$ (a master external to gem5) <-> I/O devices.
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3. a class that implements gem5's "ExternalSlave" interface to connect with
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SST "Link"s exchanging "memEvents" once again with the packet flow reversed:
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gem5 CPU <-> SST L1 cache (a slave external to gem5)
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4. an example configuration that uses both as follows:
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gem5 CPUs
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^
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| [ExternalSlave]
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v
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SST cache hierarchy <-> SST memory
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^
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| [ExternalMaster]
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v
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gem5 I/O devices (terminal, disk, etc.)
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