95 lines
3.9 KiB
Text
95 lines
3.9 KiB
Text
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____ _ ____ _____ ___ __ ____
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/ ___| / \ / ___|_ _|_ _| / /_ | ___|
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| | / _ \| | | | | | | '_ \ |___ \
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| |___ / ___ \ |___ | | | | | (_) | ___) |
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\____/_/ \_\____| |_| |___| \___(_)____/
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A Tool to Model Caches/Memories
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CACTI is an analytical tool that takes a set of cache/memory para-
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meters as input and calculates its access time, power, cycle
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time, and area.
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CACTI was originally developed by Dr. Jouppi and Dr. Wilton
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in 1993 and since then it has undergone five major
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revisions.
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List of features (version 1-6.5):
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===============================
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The following is the list of features supported by the tool.
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* Power, delay, area, and cycle time model for
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direct mapped caches
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set-associative caches
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fully associative caches
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Embedded DRAM memories
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Commodity DRAM memories
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* Support for modeling multi-ported uniform cache access (UCA)
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and multi-banked, multi-ported non-uniform cache access (NUCA).
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* Leakage power calculation that also considers the operating
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temperature of the cache.
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* Router power model.
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* Interconnect model with different delay, power, and area
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properties including low-swing wire model.
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* An interface to perform trade-off analysis involving power, delay,
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area, and bandwidth.
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* All process specific values used by the tool are obtained
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from ITRS and currently, the tool supports 90nm, 65nm, 45nm,
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and 32nm technology nodes.
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Version 6.5 has a new c++ code base and includes numerous bug fixes.
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CACTI 5.3 and 6.0 activate an entire row of mats to read/write a single
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block of data. This technique improves reliability at the cost of
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power. CACTI 6.5 activates minimum number of mats just enough to retrieve
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a block to minimize power.
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How to use the tool?
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====================
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Prior versions of CACTI take input parameters such as cache
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size and technology node as a set of command line arguments.
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To avoid a long list of command line arguments,
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CACTI 6.5 lets users specify their cache model in a more
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detailed manner by using a config file (cache.cfg).
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-> define the cache model using cache.cfg
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-> run the "cacti" binary <./cacti -infile cache.cfg>
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CACTI6.5 also provides a command line interface similar to earlier versions
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of CACTI. The command line interface can be used as
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./cacti cache_size line_size associativity rw_ports excl_read_ports excl_write_ports
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single_ended_read_ports search_ports banks tech_node output_width specific_tag tag_width
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access_mode cache main_mem obj_func_delay obj_func_dynamic_power obj_func_leakage_power
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obj_func_cycle_time obj_func_area dev_func_delay dev_func_dynamic_power dev_func_leakage_power
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dev_func_area dev_func_cycle_time ed_ed2_none temp wt data_arr_ram_cell_tech_flavor_in
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data_arr_peri_global_tech_flavor_in tag_arr_ram_cell_tech_flavor_in tag_arr_peri_global_tech_flavor_in
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interconnect_projection_type_in wire_inside_mat_type_in wire_outside_mat_type_in
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REPEATERS_IN_HTREE_SEGMENTS_in VERTICAL_HTREE_WIRES_OVER_THE_ARRAY_in
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BROADCAST_ADDR_DATAIN_OVER_VERTICAL_HTREES_in PAGE_SIZE_BITS_in BURST_LENGTH_in
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INTERNAL_PREFETCH_WIDTH_in force_wiretype wiretype force_config ndwl ndbl nspd ndcm
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ndsam1 ndsam2 ecc
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For complete documentation of the tool, please refer CACTI-5.3 and 6.0
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technical reports and the following paper,
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"Optimizing NUCA Organizations and Wiring Alternatives for
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Large Caches With CACTI 6.0", that appears in MICRO 2007.
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We are still improving the tool and refining the code. If you
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have any comments, questions, or suggestions please write to
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us.
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Naveen Muralimanohar Jung Ho Ahn Sheng Li
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naveen.muralimanohar@hp.com gajh@snu.ac.kr sheng.li@hp.com
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