479 lines
15 KiB
C++
479 lines
15 KiB
C++
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/*
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* Copyright (c) 2012 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Andreas Hansson
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* Ani Udipi
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*/
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/**
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* @file
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* SimpleDRAM declaration
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*/
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#ifndef __MEM_SIMPLE_DRAM_HH__
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#define __MEM_SIMPLE_DRAM_HH__
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#include "base/statistics.hh"
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#include "enums/AddrMap.hh"
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#include "enums/MemSched.hh"
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#include "enums/PageManage.hh"
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#include "mem/abstract_mem.hh"
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#include "mem/qport.hh"
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#include "params/SimpleDRAM.hh"
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#include "sim/eventq.hh"
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/**
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* The simple DRAM is a basic single-channel memory controller aiming
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* to mimic a high-level DRAM controller and the most important timing
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* constraints associated with the DRAM. The focus is really on
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* modelling the impact on the system rather than the DRAM itself,
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* hence the focus is on the controller model and not on the
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* memory. By adhering to the correct timing constraints, ultimately
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* there is no need for a memory model in addition to the controller
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* model.
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*
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* As a basic design principle, this controller is not cycle callable,
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* but instead uses events to decide when new decisions can be made,
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* when resources become available, when things are to be considered
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* done, and when to send things back. Through these simple
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* principles, we achieve a performant model that is not
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* cycle-accurate, but enables us to evaluate the system impact of a
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* wide range of memory technologies, and also collect statistics
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* about the use of the memory.
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*/
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class SimpleDRAM : public AbstractMemory
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{
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private:
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// For now, make use of a queued slave port to avoid dealing with
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// flow control for the responses being sent back
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class MemoryPort : public QueuedSlavePort
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{
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SlavePacketQueue queue;
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SimpleDRAM& memory;
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public:
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MemoryPort(const std::string& name, SimpleDRAM& _memory);
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protected:
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Tick recvAtomic(PacketPtr pkt);
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void recvFunctional(PacketPtr pkt);
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bool recvTimingReq(PacketPtr);
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virtual AddrRangeList getAddrRanges() const;
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};
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/**
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* Our incoming port, for a multi-ported controller add a crossbar
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* in front of it
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*/
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MemoryPort port;
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/**
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* Remember if we have to retry a request when available.
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*/
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bool retryRdReq;
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bool retryWrReq;
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/**
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* Remember that a row buffer hit occured
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*/
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bool rowHitFlag;
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/**
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* Use this flag to shutoff reads, i.e. do not schedule any reads
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* beyond those already done so that we can turn the bus around
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* and do a few writes, or refresh, or whatever
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*/
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bool stopReads;
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/**
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* A basic class to track the bank state indirectly via
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* times "freeAt" and "tRASDoneAt" and what page is currently open
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*/
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class Bank
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{
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public:
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static const uint32_t INVALID_ROW = -1;
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uint32_t openRow;
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Tick freeAt;
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Tick tRASDoneAt;
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Bank() : openRow(INVALID_ROW), freeAt(0), tRASDoneAt(0)
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{ }
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};
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/**
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* A DRAM packet stores packets along with the timestamp of when
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* the packet entered the queue, and also the decoded address.
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*/
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class DRAMPacket {
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public:
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/** When did request enter the controller */
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const Tick entryTime;
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/** When will request leave the controller */
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Tick readyTime;
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/** This comes from the outside world */
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const PacketPtr pkt;
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/** Will be populated by address decoder */
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const uint8_t rank;
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const uint16_t bank;
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const uint16_t row;
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const Addr addr;
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Bank& bank_ref;
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DRAMPacket(PacketPtr _pkt, uint8_t _rank,
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uint16_t _bank, uint16_t _row, Addr _addr, Bank& _bank_ref)
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: entryTime(curTick()), readyTime(curTick()),
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pkt(_pkt), rank(_rank), bank(_bank), row(_row), addr(_addr),
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bank_ref(_bank_ref)
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{ }
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};
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/**
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* Bunch of things requires to setup "events" in gem5
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* When event "writeEvent" occurs for example, the method
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* processWriteEvent is called; no parameters are allowed
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* in these methods
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*/
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void processWriteEvent();
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EventWrapper<SimpleDRAM, &SimpleDRAM::processWriteEvent> writeEvent;
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void processRespondEvent();
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EventWrapper<SimpleDRAM, &SimpleDRAM::processRespondEvent> respondEvent;
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void processRefreshEvent();
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EventWrapper<SimpleDRAM, &SimpleDRAM::processRefreshEvent> refreshEvent;
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void processNextReqEvent();
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EventWrapper<SimpleDRAM,&SimpleDRAM::processNextReqEvent> nextReqEvent;
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/**
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* Check if the read queue has room for more entries
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*
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* @return true if read queue is full, false otherwise
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*/
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bool readQueueFull() const;
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/**
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* Check if the write queue has room for more entries
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*
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* @return true if write queue is full, false otherwise
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*/
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bool writeQueueFull() const;
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/**
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* When a new read comes in, first check if the write q has a
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* pending request to the same address.\ If not, decode the
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* address to populate rank/bank/row, create a "dram_pkt", and
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* push it to the back of the read queue.\ If this is the only
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* read request in the system, schedule an event to start
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* servicing it.
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*
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* @param pkt The request packet from the outside world
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*/
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void addToReadQueue(PacketPtr pkt);
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/**
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* Decode the incoming pkt, create a dram_pkt and push to the
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* back of the write queue. \If the write q length is more than
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* the threshold specified by the user, ie the queue is beginning
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* to get full, stop reads, and start draining writes.
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*
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* @param pkt The request packet from the outside world
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*/
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void addToWriteQueue(PacketPtr pkt);
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/**
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* Actually do the DRAM access - figure out the latency it
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* will take to service the req based on bank state, channel state etc
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* and then update those states to account for this request.\ Based
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* on this, update the packet's "readyTime" and move it to the
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* response q from where it will eventually go back to the outside
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* world.
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*
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* @param pkt The DRAM packet created from the outside world pkt
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*/
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void doDRAMAccess(DRAMPacket* dram_pkt);
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/**
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* Check when the channel is free to turnaround, add turnaround
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* delay and schedule a whole bunch of writes.
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*/
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void triggerWrites();
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/**
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* When a packet reaches its "readyTime" in the response Q,
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* use the "access()" method in AbstractMemory to actually
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* create the response packet, and send it back to the outside
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* world requestor.
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*
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* @param pkt The packet from the outside world
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*/
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void accessAndRespond(PacketPtr pkt);
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/**
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* Address decoder to figure out physical mapping onto ranks,
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* banks, and rows.
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*
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* @param pkt The packet from the outside world
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* @return A DRAMPacket pointer with the decoded information
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*/
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DRAMPacket* decodeAddr(PacketPtr pkt);
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/**
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* The memory schduler/arbiter - picks which request needs to
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* go next, based on the specified policy such as fcfs or frfcfs
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* and moves it to the head of the read queue
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*
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* @return True if a request was chosen, False if Q is empty
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*/
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bool chooseNextReq();
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/**
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* Calls chooseNextReq() to pick the right request, then calls
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* doDRAMAccess on that request in order to actually service
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* that request
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*/
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void scheduleNextReq();
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/**
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*Looks at the state of the banks, channels, row buffer hits etc
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* to estimate how long a request will take to complete.
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*
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* @param dram_pkt The request for which we want to estimate latency
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* @param inTime The tick at which you want to probe the memory
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*
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* @return A pair of ticks, one indicating how many ticks *after*
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* inTime the request require, and the other indicating how
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* much of that was just the bank access time, ignoring the
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* ticks spent simply waiting for resources to become free
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*/
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std::pair<Tick, Tick> estimateLatency(DRAMPacket* dram_pkt, Tick inTime);
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/**
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* Move the request at the head of the read queue to the response
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* queue, sorting by readyTime.\ If it is the only packet in the
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* response queue, schedule a respond event to send it back to the
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* outside world
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*/
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void moveToRespQ();
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/**
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* Scheduling policy within the write Q
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*/
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void chooseNextWrite();
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/**
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* Looking at all banks, determine the moment in time when they
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* are all free.
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*
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* @return The tick when all banks are free
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*/
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Tick maxBankFreeAt() const;
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void printParams() const;
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void printQs() const;
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/**
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* The controller's main read and write queues
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*/
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std::list<DRAMPacket*> dramReadQueue;
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std::list<DRAMPacket*> dramWriteQueue;
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/**
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* Response queue where read packets wait after we're done working
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* with them, but it's not time to send the response yet.\ It is
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* seperate mostly to keep the code clean and help with gem5 events,
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* but for all logical purposes such as sizing the read queue, this
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* and the main read queue need to be added together.
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*/
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std::list<DRAMPacket*> dramRespQueue;
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/** If we need to drain, keep the drain event around until we're done
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* here.
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*/
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Event *drainEvent;
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/**
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* Multi-dimensional vector of banks, first dimension is ranks,
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* second is bank
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*/
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std::vector<std::vector<Bank> > banks;
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/**
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* The following are basic design parameters of the memory
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* controller, and are initialized based on parameter values. The
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* bytesPerCacheLine is based on the neighbouring port and thus
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* determined outside the constructor. Similarly, the rowsPerBank
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* is determined based on the capacity, number of ranks and banks,
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* the cache line size, and the row buffer size.
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*/
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uint32_t bytesPerCacheLine;
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const uint32_t linesPerRowBuffer;
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const uint32_t ranksPerChannel;
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const uint32_t banksPerRank;
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uint32_t rowsPerBank;
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const uint32_t readBufferSize;
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const uint32_t writeBufferSize;
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const double writeThresholdPerc;
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uint32_t writeThreshold;
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/**
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* Basic memory timing parameters initialized based on parameter
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* values.
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*/
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const Tick tWTR;
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const Tick tBURST;
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const Tick tRCD;
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const Tick tCL;
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const Tick tRP;
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const Tick tRFC;
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const Tick tREFI;
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/**
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* Memory controller configuration initialized based on parameter
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* values.
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*/
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Enums::MemSched memSchedPolicy;
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Enums::AddrMap addrMapping;
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Enums::PageManage pageMgmt;
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/**
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* Till when has the main data bus been spoken for already?
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*/
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Tick busBusyUntil;
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Tick prevdramaccess;
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Tick writeStartTime;
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Tick prevArrival;
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int numReqs;
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// All statistics that the model needs to capture
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Stats::Scalar readReqs;
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Stats::Scalar writeReqs;
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Stats::Scalar cpuReqs;
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Stats::Scalar bytesRead;
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Stats::Scalar bytesWritten;
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Stats::Scalar bytesConsumedRd;
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Stats::Scalar bytesConsumedWr;
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Stats::Scalar servicedByWrQ;
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Stats::Scalar neitherReadNorWrite;
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Stats::Vector perBankRdReqs;
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Stats::Vector perBankWrReqs;
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Stats::Scalar numRdRetry;
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Stats::Scalar numWrRetry;
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Stats::Scalar totGap;
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Stats::Vector readPktSize;
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Stats::Vector writePktSize;
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Stats::Vector neitherPktSize;
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Stats::Vector rdQLenPdf;
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Stats::Vector wrQLenPdf;
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// Latencies summed over all requests
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Stats::Scalar totQLat;
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Stats::Scalar totMemAccLat;
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Stats::Scalar totBusLat;
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Stats::Scalar totBankLat;
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// Average latencies per request
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Stats::Formula avgQLat;
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Stats::Formula avgBankLat;
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Stats::Formula avgBusLat;
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Stats::Formula avgMemAccLat;
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// Average bandwidth
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Stats::Formula avgRdBW;
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Stats::Formula avgWrBW;
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Stats::Formula avgConsumedRdBW;
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Stats::Formula avgConsumedWrBW;
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Stats::Formula peakBW;
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Stats::Formula busUtil;
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// Average queue lengths
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Stats::Average avgRdQLen;
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Stats::Average avgWrQLen;
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// Row hit count and rate
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Stats::Scalar readRowHits;
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Stats::Scalar writeRowHits;
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Stats::Formula readRowHitRate;
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Stats::Formula writeRowHitRate;
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Stats::Formula avgGap;
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public:
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void regStats();
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SimpleDRAM(const SimpleDRAMParams* p);
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unsigned int drain(Event* de);
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virtual SlavePort& getSlavePort(const std::string& if_name,
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|
int idx = InvalidPortID);
|
||
|
|
||
|
virtual void init();
|
||
|
virtual void startup();
|
||
|
|
||
|
protected:
|
||
|
|
||
|
Tick recvAtomic(PacketPtr pkt);
|
||
|
void recvFunctional(PacketPtr pkt);
|
||
|
bool recvTimingReq(PacketPtr pkt);
|
||
|
|
||
|
};
|
||
|
|
||
|
#endif //__MEM_SIMPLE_DRAM_HH__
|