2008-11-10 06:57:15 +01:00
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---------- Begin Simulation Statistics ----------
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2009-02-25 19:18:45 +01:00
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host_inst_rate 929786 # Simulator instruction rate (inst/s)
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host_mem_usage 204596 # Number of bytes of host memory used
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host_seconds 5004.56 # Real time elapsed on the host
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host_tick_rate 1196520405 # Simulator tick rate (ticks/s)
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2008-11-10 06:57:15 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2009-02-02 02:02:16 +01:00
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sim_insts 4653176258 # Number of instructions simulated
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2009-02-25 19:18:45 +01:00
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sim_seconds 5.988064 # Number of seconds simulated
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sim_ticks 5988064029000 # Number of ticks simulated
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2008-11-10 06:57:15 +01:00
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system.cpu.dcache.ReadReq_accesses 1239184742 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 25017.713978 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22017.713978 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 1231961294 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 180714156000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.005829 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 7223448 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_miss_latency 159043812000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.005829 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 7223448 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 438528336 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 55999.834453 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.834453 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 436281234 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 125837340000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.005124 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 2247102 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_miss_latency 119096034000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.005124 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 2247102 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 183.099497 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 1677713078 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 32368.922185 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 29368.922185 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 1668242528 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 306551496000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.005645 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 9470550 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 278139846000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.005645 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 9470550 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 1677713078 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 32368.922185 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 29368.922185 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 1668242528 # number of overall hits
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system.cpu.dcache.overall_miss_latency 306551496000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.005645 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 9470550 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 278139846000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.005645 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 9470550 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 9108982 # number of replacements
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system.cpu.dcache.sampled_refs 9113078 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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2009-02-25 19:18:45 +01:00
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system.cpu.dcache.tagsinuse 4084.778559 # Cycle average of tags in use
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2008-11-10 06:57:15 +01:00
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system.cpu.dcache.total_refs 1668600000 # Total number of references to valid blocks.
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2009-02-25 19:18:45 +01:00
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system.cpu.dcache.warmup_cycle 58863922000 # Cycle when the warmup percentage was hit.
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2008-11-10 06:57:15 +01:00
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system.cpu.dcache.writebacks 2244013 # number of writebacks
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2009-02-25 19:18:45 +01:00
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system.cpu.icache.ReadReq_accesses 4013232881 # number of ReadReq accesses(hits+misses)
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2008-11-10 06:57:15 +01:00
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system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
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2009-02-25 19:18:45 +01:00
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system.cpu.icache.ReadReq_hits 4013232206 # number of ReadReq hits
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2008-11-10 06:57:15 +01:00
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system.cpu.icache.ReadReq_miss_latency 37800000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 675 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_miss_latency 35775000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 675 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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2009-02-25 19:18:45 +01:00
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system.cpu.icache.avg_refs 5945529.194074 # Average number of references to valid blocks.
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2008-11-10 06:57:15 +01:00
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system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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2009-02-25 19:18:45 +01:00
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system.cpu.icache.demand_accesses 4013232881 # number of demand (read+write) accesses
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2008-11-10 06:57:15 +01:00
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system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
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2009-02-25 19:18:45 +01:00
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system.cpu.icache.demand_hits 4013232206 # number of demand (read+write) hits
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2008-11-10 06:57:15 +01:00
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system.cpu.icache.demand_miss_latency 37800000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
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system.cpu.icache.demand_misses 675 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 35775000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 675 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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2009-02-25 19:18:45 +01:00
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system.cpu.icache.overall_accesses 4013232881 # number of overall (read+write) accesses
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2008-11-10 06:57:15 +01:00
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system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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2009-02-25 19:18:45 +01:00
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system.cpu.icache.overall_hits 4013232206 # number of overall hits
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2008-11-10 06:57:15 +01:00
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system.cpu.icache.overall_miss_latency 37800000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
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system.cpu.icache.overall_misses 675 # number of overall misses
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system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 35775000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 675 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.replacements 10 # number of replacements
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system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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2009-02-25 19:18:45 +01:00
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system.cpu.icache.tagsinuse 555.573306 # Cycle average of tags in use
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system.cpu.icache.total_refs 4013232206 # Total number of references to valid blocks.
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2008-11-10 06:57:15 +01:00
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.l2cache.ReadExReq_accesses 1889630 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
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system.cpu.l2cache.ReadExReq_miss_latency 98260760000 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_misses 1889630 # number of ReadExReq misses
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system.cpu.l2cache.ReadExReq_mshr_miss_latency 75585200000 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_mshr_misses 1889630 # number of ReadExReq MSHR misses
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system.cpu.l2cache.ReadReq_accesses 7224123 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadReq_hits 5328546 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_miss_latency 98570004000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_rate 0.262395 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_misses 1895577 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency 75823080000 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate 0.262395 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_mshr_misses 1895577 # number of ReadReq MSHR misses
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system.cpu.l2cache.UpgradeReq_accesses 357472 # number of UpgradeReq accesses(hits+misses)
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system.cpu.l2cache.UpgradeReq_avg_miss_latency 51945.886671 # average UpgradeReq miss latency
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system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
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system.cpu.l2cache.UpgradeReq_miss_latency 18569200000 # number of UpgradeReq miss cycles
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system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_misses 357472 # number of UpgradeReq misses
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system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14298880000 # number of UpgradeReq MSHR miss cycles
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system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_mshr_misses 357472 # number of UpgradeReq MSHR misses
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system.cpu.l2cache.Writeback_accesses 2244013 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.Writeback_hits 2244013 # number of Writeback hits
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system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.l2cache.avg_refs 2.381201 # Average number of references to valid blocks.
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system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
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|
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system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
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|
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system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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|
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system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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|
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system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.demand_accesses 9113753 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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system.cpu.l2cache.demand_hits 5328546 # number of demand (read+write) hits
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system.cpu.l2cache.demand_miss_latency 196830764000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_rate 0.415329 # miss rate for demand accesses
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system.cpu.l2cache.demand_misses 3785207 # number of demand (read+write) misses
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system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.l2cache.demand_mshr_miss_latency 151408280000 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.demand_mshr_miss_rate 0.415329 # mshr miss rate for demand accesses
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system.cpu.l2cache.demand_mshr_misses 3785207 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.overall_accesses 9113753 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.l2cache.overall_hits 5328546 # number of overall hits
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|
|
system.cpu.l2cache.overall_miss_latency 196830764000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.415329 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_misses 3785207 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 151408280000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.415329 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 3785207 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.l2cache.replacements 2772128 # number of replacements
|
|
|
|
|
system.cpu.l2cache.sampled_refs 2798338 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2009-02-25 19:18:45 +01:00
|
|
|
system.cpu.l2cache.tagsinuse 25742.940427 # Cycle average of tags in use
|
2008-11-10 06:57:15 +01:00
|
|
|
system.cpu.l2cache.total_refs 6663406 # Total number of references to valid blocks.
|
2009-02-25 19:18:45 +01:00
|
|
|
system.cpu.l2cache.warmup_cycle 4737814303000 # Cycle when the warmup percentage was hit.
|
2008-11-10 06:57:15 +01:00
|
|
|
system.cpu.l2cache.writebacks 1199171 # number of writebacks
|
|
|
|
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
2009-02-25 19:18:45 +01:00
|
|
|
system.cpu.numCycles 11976128058 # number of cpu cycles simulated
|
2009-02-02 02:02:16 +01:00
|
|
|
system.cpu.num_insts 4653176258 # Number of instructions executed
|
2009-02-25 19:16:29 +01:00
|
|
|
system.cpu.num_refs 1677713078 # Number of memory references
|
2008-11-10 06:57:15 +01:00
|
|
|
system.cpu.workload.PROG:num_syscalls 46 # Number of system calls
|
|
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
