2011-01-18 23:30:06 +01:00
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---------- Begin Simulation Statistics ----------
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2011-05-23 17:59:13 +02:00
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sim_seconds 0.000011 # Number of seconds simulated
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sim_ticks 10758500 # Number of ticks simulated
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2011-01-18 23:30:06 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-05-23 17:59:13 +02:00
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host_inst_rate 88454 # Simulator instruction rate (inst/s)
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host_tick_rate 165780634 # Simulator tick rate (ticks/s)
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host_mem_usage 251164 # Number of bytes of host memory used
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host_seconds 0.07 # Real time elapsed on the host
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2011-03-18 01:20:22 +01:00
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sim_insts 5739 # Number of instructions simulated
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2011-05-23 17:59:13 +02:00
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 13 # Number of system calls
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system.cpu.numCycles 21518 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.BPredUnit.lookups 2191 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 1669 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 423 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 1853 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 732 # Number of BTB hits
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2011-01-18 23:30:06 +01:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2011-05-23 17:59:13 +02:00
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system.cpu.BPredUnit.usedRAS 242 # Number of times the RAS was used to get a target.
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2011-05-14 00:29:27 +02:00
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system.cpu.BPredUnit.RASInCorrect 63 # Number of incorrect RAS predictions.
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2011-05-23 17:59:13 +02:00
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system.cpu.fetch.icacheStallCycles 1618 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 11168 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 2191 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 974 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 2422 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 514 # Number of cycles fetch has spent squashing
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system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.CacheLines 1618 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 231 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 11665 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 1.190999 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.598414 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 9243 79.24% 79.24% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 226 1.94% 81.17% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 153 1.31% 82.49% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 215 1.84% 84.33% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 195 1.67% 86.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 261 2.24% 88.24% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 124 1.06% 89.30% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 97 0.83% 90.13% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 1151 9.87% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 11665 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.101822 # Number of branch fetches per cycle
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system.cpu.fetch.rate 0.519007 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 7384 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 1181 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 2267 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 47 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 786 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 350 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 158 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 12143 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 552 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 786 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 7644 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 280 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 712 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 2054 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 189 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 11385 # Number of instructions processed by rename
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system.cpu.rename.IQFullEvents 38 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 124 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.RenamedOperands 11181 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 51901 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 51381 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 520 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 5684 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 5492 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 15 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 13 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 493 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 2353 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 1452 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 10217 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 24 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 8487 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 3978 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 11076 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.issued_per_cycle::samples 11665 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 0.727561 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.389080 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::0 8112 69.54% 69.54% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 1403 12.03% 81.57% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 820 7.03% 88.60% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 520 4.46% 93.06% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 393 3.37% 96.43% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 236 2.02% 98.45% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 143 1.23% 99.67% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 30 0.26% 99.93% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 8 0.07% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::total 11665 # Number of insts issued each cycle
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntAlu 11 6.01% 6.01% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 0 0.00% 6.01% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 6.01% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.01% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.01% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.01% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 6.01% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.01% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.01% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.01% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.01% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.01% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.01% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.01% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.01% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 6.01% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.01% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 6.01% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.01% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.01% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.01% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.01% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.01% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.01% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.01% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.01% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.01% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.01% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.01% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 116 63.39% 69.40% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 56 30.60% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
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system.cpu.iq.FU_type_0::IntAlu 5246 61.81% 61.81% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 6 0.07% 61.88% # Type of FU issued
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system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.88% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.88% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.88% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.88% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.88% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.88% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.88% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.88% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.88% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.88% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.88% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.88% # Type of FU issued
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|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.88% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.88% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.88% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.88% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.88% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.88% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.88% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.88% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.88% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.88% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.88% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 61.92% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.92% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.92% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.92% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemRead 2078 24.48% 86.40% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 1154 13.60% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::total 8487 # Type of FU issued
|
|
|
|
|
system.cpu.iq.rate 0.394414 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 183 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.021562 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 28807 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 14215 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 7753 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_alu_accesses 8650 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 50 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 1152 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 14 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 514 # Number of stores squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
|
|
|
system.cpu.iew.iewSquashCycles 786 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 166 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 27 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 10244 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 136 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 2353 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 1452 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 19 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 14 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 128 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 243 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 371 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 8154 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 1932 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 333 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
|
|
|
system.cpu.iew.exec_nop 3 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_refs 3053 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 1361 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 1121 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 0.378939 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 7896 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 7769 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 3570 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 7022 # num instructions consuming a value
|
|
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu.iew.wb_rate 0.361047 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.508402 # average fanout of values written-back
|
|
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.commit.commitCommittedInsts 5739 # The number of committed instructions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.commitSquashedInsts 4400 # The number of squashed insts skipped by commit
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.commit.commitNonSpecStalls 24 # The number of times commit has been forced to stall to communicate backwards
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.branchMispredicts 334 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 10880 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 0.527482 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 1.289859 # Number of insts commited each cycle
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::0 8406 77.26% 77.26% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 1187 10.91% 88.17% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 477 4.38% 92.56% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 317 2.91% 95.47% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 170 1.56% 97.03% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 153 1.41% 98.44% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 62 0.57% 99.01% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 34 0.31% 99.32% # Number of insts commited each cycle
|
2011-05-14 00:29:27 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::8 74 0.68% 100.00% # Number of insts commited each cycle
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::total 10880 # Number of insts commited each cycle
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.count 5739 # Number of instructions committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
|
|
|
system.cpu.commit.refs 2139 # Number of memory references committed
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.loads 1201 # Number of loads committed
|
|
|
|
|
system.cpu.commit.membars 12 # Number of memory barriers committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.branches 945 # Number of branches committed
|
|
|
|
|
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
|
|
|
|
|
system.cpu.commit.int_insts 4985 # Number of committed integer instructions.
|
|
|
|
|
system.cpu.commit.function_calls 82 # Number of function calls committed.
|
|
|
|
|
system.cpu.commit.bw_lim_events 74 # number cycles where commit BW limit reached
|
|
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
|
|
|
system.cpu.rob.rob_reads 20788 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 21080 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 199 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 9853 # Total number of cycles that the CPU has spent unscheduled due to idling
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.committedInsts 5739 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 5739 # Number of Instructions Simulated
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.cpi 3.749434 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 3.749434 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 0.266707 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 0.266707 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 37248 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 7653 # number of integer regfile writes
|
|
|
|
|
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
|
|
|
|
system.cpu.misc_regfile_reads 13970 # number of misc regfile reads
|
|
|
|
|
system.cpu.misc_regfile_writes 24 # number of misc regfile writes
|
|
|
|
|
system.cpu.icache.replacements 2 # number of replacements
|
|
|
|
|
system.cpu.icache.tagsinuse 146.709916 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 1288 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.sampled_refs 285 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.avg_refs 4.519298 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.occ_blocks::0 146.709916 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.occ_percent::0 0.071636 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits 1288 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits 1288 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits 1288 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses 330 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses 330 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses 330 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 11562500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency 11562500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency 11562500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 1618 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses 1618 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses 1618 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.203956 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.203956 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.203956 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 35037.878788 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 35037.878788 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 35037.878788 # average overall miss latency
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits 45 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 45 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 45 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 285 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 285 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 285 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 9568500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 9568500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 9568500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.176143 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.176143 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.176143 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 33573.684211 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 33573.684211 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 33573.684211 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.dcache.replacements 0 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 89.574063 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 2279 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 149 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 15.295302 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.occ_blocks::0 89.574063 # Average occupied blocks per context
|
|
|
|
|
system.cpu.dcache.occ_percent::0 0.021869 # Average percentage of cache occupancy
|
2011-05-14 00:29:27 +02:00
|
|
|
system.cpu.dcache.ReadReq_hits 1637 # number of ReadReq hits
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.WriteReq_hits 622 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.dcache.StoreCondReq_hits 11 # number of StoreCondReq hits
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.demand_hits 2259 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits 2259 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses 159 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 291 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu.dcache.demand_misses 450 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses 450 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 5132500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency 10420500 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency 76500 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency 15553000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 15553000 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 1796 # number of ReadReq accesses(hits+misses)
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.dcache.WriteReq_accesses 913 # number of WriteReq accesses(hits+misses)
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses 11 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.demand_accesses 2709 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses 2709 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.088530 # miss rate for ReadReq accesses
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.318729 # miss rate for WriteReq accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate 0.181818 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate 0.166113 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.166113 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 32279.874214 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 35809.278351 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency 38250 # average LoadLockedReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency 34562.222222 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 34562.222222 # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.writebacks 0 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 52 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 249 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits
|
2011-05-14 00:29:27 +02:00
|
|
|
system.cpu.dcache.demand_mshr_hits 301 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 301 # number of overall MSHR hits
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 107 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 42 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses 149 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 149 # number of overall MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 3099500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 1507500 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 4607000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 4607000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.059577 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.046002 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.055002 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.055002 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 28967.289720 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35892.857143 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 30919.463087 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 30919.463087 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 185.420659 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 39 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 347 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 0.112392 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.occ_blocks::0 185.420659 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_percent::0 0.005659 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 39 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits 39 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits 39 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 353 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 42 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses 395 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses 395 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 12138500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 1447000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 13585500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 13585500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 392 # number of ReadReq accesses(hits+misses)
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_accesses 42 # number of ReadExReq accesses(hits+misses)
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.demand_accesses 434 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses 434 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.900510 # miss rate for ReadReq accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.demand_miss_rate 0.910138 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.910138 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34386.685552 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34452.380952 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34393.670886 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34393.670886 # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits
|
2011-05-14 00:29:27 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 6 # number of overall MSHR hits
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 347 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 42 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 389 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 389 # number of overall MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 10837500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1315000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 12152500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 12152500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.885204 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.896313 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.896313 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31231.988473 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31309.523810 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31240.359897 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31240.359897 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-01-18 23:30:06 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
