2014-07-23 23:09:04 +02:00
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# Copyright (c) 2012-2014 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Gabe Black
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# Nathan Binkert
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# Andrew Bardsley
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from m5.defines import buildEnv
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from m5.params import *
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from m5.proxy import *
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from m5.SimObject import SimObject
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from BaseCPU import BaseCPU
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from DummyChecker import DummyChecker
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2015-04-14 00:33:57 +02:00
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from BranchPredictor import *
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2014-07-23 23:09:04 +02:00
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from TimingExpr import TimingExpr
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from FuncUnit import OpClass
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class MinorOpClass(SimObject):
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"""Boxing of OpClass to get around build problems and provide a hook for
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future additions to OpClass checks"""
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type = 'MinorOpClass'
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cxx_header = "cpu/minor/func_unit.hh"
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opClass = Param.OpClass("op class to match")
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class MinorOpClassSet(SimObject):
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"""A set of matchable op classes"""
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type = 'MinorOpClassSet'
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cxx_header = "cpu/minor/func_unit.hh"
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opClasses = VectorParam.MinorOpClass([], "op classes to be matched."
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" An empty list means any class")
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class MinorFUTiming(SimObject):
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type = 'MinorFUTiming'
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cxx_header = "cpu/minor/func_unit.hh"
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mask = Param.UInt64(0, "mask for testing ExtMachInst")
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match = Param.UInt64(0, "match value for testing ExtMachInst:"
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" (ext_mach_inst & mask) == match")
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suppress = Param.Bool(False, "if true, this inst. is not executed by"
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" this FU")
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extraCommitLat = Param.Cycles(0, "extra cycles to stall commit for"
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" this inst.")
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extraCommitLatExpr = Param.TimingExpr(NULL, "extra cycles as a"
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" run-time evaluated expression")
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extraAssumedLat = Param.Cycles(0, "extra cycles to add to scoreboard"
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" retire time for this insts dest registers once it leaves the"
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" functional unit. For mem refs, if this is 0, the result's time"
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" is marked as unpredictable and no forwarding can take place.")
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srcRegsRelativeLats = VectorParam.Cycles("the maximum number of cycles"
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" after inst. issue that each src reg can be available for this"
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" inst. to issue")
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opClasses = Param.MinorOpClassSet(MinorOpClassSet(),
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"op classes to be considered for this decode. An empty set means any"
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" class")
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description = Param.String('', "description string of the decoding/inst."
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" class")
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def minorMakeOpClassSet(op_classes):
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"""Make a MinorOpClassSet from a list of OpClass enum value strings"""
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def boxOpClass(op_class):
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return MinorOpClass(opClass=op_class)
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return MinorOpClassSet(opClasses=map(boxOpClass, op_classes))
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class MinorFU(SimObject):
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type = 'MinorFU'
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cxx_header = "cpu/minor/func_unit.hh"
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opClasses = Param.MinorOpClassSet(MinorOpClassSet(), "type of operations"
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" allowed on this functional unit")
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opLat = Param.Cycles(1, "latency in cycles")
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issueLat = Param.Cycles(1, "cycles until another instruction can be"
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" issued")
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timings = VectorParam.MinorFUTiming([], "extra decoding rules")
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cantForwardFromFUIndices = VectorParam.Unsigned([],
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"list of FU indices from which this FU can't receive and early"
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" (forwarded) result")
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class MinorFUPool(SimObject):
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type = 'MinorFUPool'
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cxx_header = "cpu/minor/func_unit.hh"
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funcUnits = VectorParam.MinorFU("functional units")
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class MinorDefaultIntFU(MinorFU):
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opClasses = minorMakeOpClassSet(['IntAlu'])
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timings = [MinorFUTiming(description="Int",
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srcRegsRelativeLats=[2])]
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opLat = 3
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class MinorDefaultIntMulFU(MinorFU):
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opClasses = minorMakeOpClassSet(['IntMult'])
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timings = [MinorFUTiming(description='Mul',
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srcRegsRelativeLats=[0])]
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opLat = 3
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class MinorDefaultIntDivFU(MinorFU):
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opClasses = minorMakeOpClassSet(['IntDiv'])
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issueLat = 9
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opLat = 9
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class MinorDefaultFloatSimdFU(MinorFU):
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opClasses = minorMakeOpClassSet([
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'FloatAdd', 'FloatCmp', 'FloatCvt', 'FloatMult', 'FloatDiv',
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'FloatSqrt',
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'SimdAdd', 'SimdAddAcc', 'SimdAlu', 'SimdCmp', 'SimdCvt',
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'SimdMisc', 'SimdMult', 'SimdMultAcc', 'SimdShift', 'SimdShiftAcc',
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'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu', 'SimdFloatCmp',
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'SimdFloatCvt', 'SimdFloatDiv', 'SimdFloatMisc', 'SimdFloatMult',
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'SimdFloatMultAcc', 'SimdFloatSqrt'])
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timings = [MinorFUTiming(description='FloatSimd',
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srcRegsRelativeLats=[2])]
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opLat = 6
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class MinorDefaultMemFU(MinorFU):
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opClasses = minorMakeOpClassSet(['MemRead', 'MemWrite'])
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timings = [MinorFUTiming(description='Mem',
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srcRegsRelativeLats=[1], extraAssumedLat=2)]
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opLat = 1
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class MinorDefaultMiscFU(MinorFU):
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opClasses = minorMakeOpClassSet(['IprAccess', 'InstPrefetch'])
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opLat = 1
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class MinorDefaultFUPool(MinorFUPool):
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funcUnits = [MinorDefaultIntFU(), MinorDefaultIntFU(),
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MinorDefaultIntMulFU(), MinorDefaultIntDivFU(),
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MinorDefaultFloatSimdFU(), MinorDefaultMemFU(),
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MinorDefaultMiscFU()]
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class MinorCPU(BaseCPU):
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type = 'MinorCPU'
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cxx_header = "cpu/minor/cpu.hh"
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@classmethod
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def memory_mode(cls):
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return 'timing'
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@classmethod
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def require_caches(cls):
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return True
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@classmethod
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def support_take_over(cls):
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return True
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fetch1FetchLimit = Param.Unsigned(1,
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"Number of line fetches allowable in flight at once")
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fetch1LineSnapWidth = Param.Unsigned(0,
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"Fetch1 'line' fetch snap size in bytes"
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" (0 means use system cache line size)")
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fetch1LineWidth = Param.Unsigned(0,
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"Fetch1 maximum fetch size in bytes (0 means use system cache"
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" line size)")
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fetch1ToFetch2ForwardDelay = Param.Cycles(1,
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"Forward cycle delay from Fetch1 to Fetch2 (1 means next cycle)")
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fetch1ToFetch2BackwardDelay = Param.Cycles(1,
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"Backward cycle delay from Fetch2 to Fetch1 for branch prediction"
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" signalling (0 means in the same cycle, 1 mean the next cycle)")
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fetch2InputBufferSize = Param.Unsigned(2,
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"Size of input buffer to Fetch2 in cycles-worth of insts.")
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fetch2ToDecodeForwardDelay = Param.Cycles(1,
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"Forward cycle delay from Fetch2 to Decode (1 means next cycle)")
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fetch2CycleInput = Param.Bool(True,
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"Allow Fetch2 to cross input lines to generate full output each"
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" cycle")
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decodeInputBufferSize = Param.Unsigned(3,
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"Size of input buffer to Decode in cycles-worth of insts.")
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decodeToExecuteForwardDelay = Param.Cycles(1,
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"Forward cycle delay from Decode to Execute (1 means next cycle)")
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decodeInputWidth = Param.Unsigned(2,
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"Width (in instructions) of input to Decode (and implicitly"
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" Decode's own width)")
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decodeCycleInput = Param.Bool(True,
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"Allow Decode to pack instructions from more than one input cycle"
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" to fill its output each cycle")
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executeInputWidth = Param.Unsigned(2,
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"Width (in instructions) of input to Execute")
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executeCycleInput = Param.Bool(True,
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"Allow Execute to use instructions from more than one input cycle"
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" each cycle")
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executeIssueLimit = Param.Unsigned(2,
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"Number of issuable instructions in Execute each cycle")
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executeMemoryIssueLimit = Param.Unsigned(1,
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"Number of issuable memory instructions in Execute each cycle")
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executeCommitLimit = Param.Unsigned(2,
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"Number of committable instructions in Execute each cycle")
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executeMemoryCommitLimit = Param.Unsigned(1,
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"Number of committable memory references in Execute each cycle")
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executeInputBufferSize = Param.Unsigned(7,
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"Size of input buffer to Execute in cycles-worth of insts.")
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executeMemoryWidth = Param.Unsigned(0,
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"Width (and snap) in bytes of the data memory interface. (0 mean use"
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" the system cacheLineSize)")
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executeMaxAccessesInMemory = Param.Unsigned(2,
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"Maximum number of concurrent accesses allowed to the memory system"
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" from the dcache port")
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executeLSQMaxStoreBufferStoresPerCycle = Param.Unsigned(2,
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"Maximum number of stores that the store buffer can issue per cycle")
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executeLSQRequestsQueueSize = Param.Unsigned(1,
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"Size of LSQ requests queue (address translation queue)")
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executeLSQTransfersQueueSize = Param.Unsigned(2,
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"Size of LSQ transfers queue (memory transaction queue)")
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executeLSQStoreBufferSize = Param.Unsigned(5,
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"Size of LSQ store buffer")
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executeBranchDelay = Param.Cycles(1,
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"Delay from Execute deciding to branch and Fetch1 reacting"
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" (1 means next cycle)")
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executeFuncUnits = Param.MinorFUPool(MinorDefaultFUPool(),
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"FUlines for this processor")
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executeSetTraceTimeOnCommit = Param.Bool(True,
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"Set inst. trace times to be commit times")
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executeSetTraceTimeOnIssue = Param.Bool(False,
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"Set inst. trace times to be issue times")
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executeAllowEarlyMemoryIssue = Param.Bool(True,
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"Allow mem refs to be issued to the LSQ before reaching the head of"
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" the in flight insts queue")
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enableIdling = Param.Bool(True,
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"Enable cycle skipping when the processor is idle\n");
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2015-04-14 00:33:57 +02:00
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branchPred = Param.BranchPredictor(TournamentBP(
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2014-07-23 23:09:04 +02:00
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numThreads = Parent.numThreads), "Branch Predictor")
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def addCheckerCpu(self):
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print "Checker not yet supported by MinorCPU"
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exit(1)
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