2007-03-11 08:00:54 +01:00
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# -*- mode:python -*-
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# Copyright (c) 2006 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Nathan Binkert
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Import('*')
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2012-08-21 11:49:01 +02:00
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SimObject('ClockedObject.py')
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2014-07-23 23:09:04 +02:00
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SimObject('TickedObject.py')
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2007-05-28 04:21:17 +02:00
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SimObject('Root.py')
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sim: Add the notion of clock domains to all ClockedObjects
This patch adds the notion of source- and derived-clock domains to the
ClockedObjects. As such, all clock information is moved to the clock
domain, and the ClockedObjects are grouped into domains.
The clock domains are either source domains, with a specific clock
period, or derived domains that have a parent domain and a divider
(potentially chained). For piece of logic that runs at a derived clock
(a ratio of the clock its parent is running at) the necessary derived
clock domain is created from its corresponding parent clock
domain. For now, the derived clock domain only supports a divider,
thus ensuring a lower speed compared to its parent. Multiplier
functionality implies a PLL logic that has not been modelled yet
(create a separate clock instead).
The clock domains should be used as a mechanism to provide a
controllable clock source that affects clock for every clocked object
lying beneath it. The clock of the domain can (in a future patch) be
controlled by a handler responsible for dynamic frequency scaling of
the respective clock domains.
All the config scripts have been retro-fitted with clock domains. For
the System a default SrcClockDomain is created. For CPUs that run at a
different speed than the system, there is a seperate clock domain
created. This domain incorporates the CPU and the associated
caches. As before, Ruby runs under its own clock domain.
The clock period of all domains are pre-computed, such that no virtual
functions or multiplications are needed when calling
clockPeriod. Instead, the clock period is pre-computed when any
changes occur. For this to be possible, each clock domain tracks its
children.
2013-06-27 11:49:49 +02:00
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SimObject('ClockDomain.py')
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2013-08-19 09:52:28 +02:00
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SimObject('VoltageDomain.py')
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2013-09-04 19:22:57 +02:00
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SimObject('System.py')
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power: Add basic DVFS support for gem5
Adds DVFS capabilities to gem5, by allowing users to specify lists for
frequencies and voltages in SrcClockDomains and VoltageDomains respectively.
A separate component, DVFSHandler, provides a small interface to change
operating points of the associated domains.
Clock domains will be linked to voltage domains and thus allow separate clock,
but shared voltage lines.
Currently all the valid performance-level updates are performed with a fixed
transition latency as specified for the domain.
Config file example:
...
vd = VoltageDomain(voltage = ['1V','0.95V','0.90V','0.85V'])
tsys.cluster1.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz']
tsys.cluster2.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz']
tsys.cluster1.clk_domain.domain_id = 0
tsys.cluster2.clk_domain.domain_id = 1
tsys.cluster1.clk_domain.voltage_domain = vd
tsys.cluster2.clk_domain.voltage_domain = vd
tsys.dvfs_handler.domains = [tsys.cluster1.clk_domain,
tsys.cluster2.clk_domain]
tsys.dvfs_handler.enable = True
2014-06-30 19:56:06 +02:00
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SimObject('DVFSHandler.py')
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2014-08-10 11:39:16 +02:00
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SimObject('SubSystem.py')
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2007-05-28 04:21:17 +02:00
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2011-10-31 01:38:11 +01:00
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Source('arguments.cc')
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2007-03-11 08:00:54 +01:00
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Source('async.cc')
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Source('core.cc')
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2015-09-02 22:23:30 +02:00
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Source('tags.cc')
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2014-10-16 11:49:37 +02:00
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Source('cxx_config.cc')
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Source('cxx_manager.cc')
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Source('cxx_config_ini.cc')
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2007-03-11 08:00:54 +01:00
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Source('debug.cc')
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2014-10-16 11:49:32 +02:00
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Source('py_interact.cc', skip_no_python=True)
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2007-03-11 08:00:54 +01:00
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Source('eventq.cc')
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2013-11-25 18:21:00 +01:00
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Source('global_event.cc')
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2014-10-16 11:49:32 +02:00
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Source('init.cc', skip_no_python=True)
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Source('init_signals.cc')
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2011-04-15 19:44:44 +02:00
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Source('main.cc', main=True, skip_lib=True)
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2007-03-11 08:00:54 +01:00
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Source('root.cc')
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Source('serialize.cc')
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2012-11-02 17:32:01 +01:00
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Source('drain.cc')
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2007-03-11 08:00:54 +01:00
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Source('sim_events.cc')
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Source('sim_object.cc')
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2014-08-10 11:39:16 +02:00
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Source('sub_system.cc')
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2014-07-23 23:09:04 +02:00
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Source('ticked_object.cc')
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2007-03-11 08:00:54 +01:00
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Source('simulate.cc')
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Source('stat_control.cc')
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2014-10-16 11:49:32 +02:00
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Source('stat_register.cc', skip_no_python=True)
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sim: Add the notion of clock domains to all ClockedObjects
This patch adds the notion of source- and derived-clock domains to the
ClockedObjects. As such, all clock information is moved to the clock
domain, and the ClockedObjects are grouped into domains.
The clock domains are either source domains, with a specific clock
period, or derived domains that have a parent domain and a divider
(potentially chained). For piece of logic that runs at a derived clock
(a ratio of the clock its parent is running at) the necessary derived
clock domain is created from its corresponding parent clock
domain. For now, the derived clock domain only supports a divider,
thus ensuring a lower speed compared to its parent. Multiplier
functionality implies a PLL logic that has not been modelled yet
(create a separate clock instead).
The clock domains should be used as a mechanism to provide a
controllable clock source that affects clock for every clocked object
lying beneath it. The clock of the domain can (in a future patch) be
controlled by a handler responsible for dynamic frequency scaling of
the respective clock domains.
All the config scripts have been retro-fitted with clock domains. For
the System a default SrcClockDomain is created. For CPUs that run at a
different speed than the system, there is a seperate clock domain
created. This domain incorporates the CPU and the associated
caches. As before, Ruby runs under its own clock domain.
The clock period of all domains are pre-computed, such that no virtual
functions or multiplications are needed when calling
clockPeriod. Instead, the clock period is pre-computed when any
changes occur. For this to be possible, each clock domain tracks its
children.
2013-06-27 11:49:49 +02:00
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Source('clock_domain.cc')
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2013-08-19 09:52:28 +02:00
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Source('voltage_domain.cc')
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2013-09-04 19:22:57 +02:00
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Source('system.cc')
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power: Add basic DVFS support for gem5
Adds DVFS capabilities to gem5, by allowing users to specify lists for
frequencies and voltages in SrcClockDomains and VoltageDomains respectively.
A separate component, DVFSHandler, provides a small interface to change
operating points of the associated domains.
Clock domains will be linked to voltage domains and thus allow separate clock,
but shared voltage lines.
Currently all the valid performance-level updates are performed with a fixed
transition latency as specified for the domain.
Config file example:
...
vd = VoltageDomain(voltage = ['1V','0.95V','0.90V','0.85V'])
tsys.cluster1.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz']
tsys.cluster2.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz']
tsys.cluster1.clk_domain.domain_id = 0
tsys.cluster2.clk_domain.domain_id = 1
tsys.cluster1.clk_domain.voltage_domain = vd
tsys.cluster2.clk_domain.voltage_domain = vd
tsys.dvfs_handler.domains = [tsys.cluster1.clk_domain,
tsys.cluster2.clk_domain]
tsys.dvfs_handler.enable = True
2014-06-30 19:56:06 +02:00
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Source('dvfs_handler.cc')
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2010-11-20 01:00:39 +01:00
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2013-09-04 19:22:57 +02:00
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if env['TARGET_ISA'] != 'null':
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SimObject('InstTracer.py')
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2011-10-30 08:32:54 +01:00
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SimObject('Process.py')
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2010-11-20 01:00:39 +01:00
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Source('faults.cc')
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2011-10-30 08:32:54 +01:00
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Source('process.cc')
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2015-07-24 21:25:22 +02:00
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Source('fd_entry.cc')
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2010-11-20 01:00:39 +01:00
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Source('pseudo_inst.cc')
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2013-09-04 19:22:57 +02:00
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Source('syscall_emul.cc')
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2007-05-28 04:21:17 +02:00
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2011-06-03 02:36:21 +02:00
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DebugFlag('Checkpoint')
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DebugFlag('Config')
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2014-10-16 11:49:37 +02:00
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DebugFlag('CxxConfig')
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2012-08-15 16:38:08 +02:00
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DebugFlag('Drain')
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2011-06-03 02:36:21 +02:00
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DebugFlag('Event')
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DebugFlag('Fault')
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DebugFlag('Flow')
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DebugFlag('IPI')
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DebugFlag('IPR')
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DebugFlag('Interrupt')
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DebugFlag('Loader')
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2013-06-03 13:21:21 +02:00
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DebugFlag('PseudoInst')
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2011-06-03 02:36:21 +02:00
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DebugFlag('Stack')
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DebugFlag('SyscallVerbose')
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DebugFlag('TimeSync')
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DebugFlag('Thread')
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DebugFlag('Timer')
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DebugFlag('VtoPhys')
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DebugFlag('WorkItems')
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sim: Add the notion of clock domains to all ClockedObjects
This patch adds the notion of source- and derived-clock domains to the
ClockedObjects. As such, all clock information is moved to the clock
domain, and the ClockedObjects are grouped into domains.
The clock domains are either source domains, with a specific clock
period, or derived domains that have a parent domain and a divider
(potentially chained). For piece of logic that runs at a derived clock
(a ratio of the clock its parent is running at) the necessary derived
clock domain is created from its corresponding parent clock
domain. For now, the derived clock domain only supports a divider,
thus ensuring a lower speed compared to its parent. Multiplier
functionality implies a PLL logic that has not been modelled yet
(create a separate clock instead).
The clock domains should be used as a mechanism to provide a
controllable clock source that affects clock for every clocked object
lying beneath it. The clock of the domain can (in a future patch) be
controlled by a handler responsible for dynamic frequency scaling of
the respective clock domains.
All the config scripts have been retro-fitted with clock domains. For
the System a default SrcClockDomain is created. For CPUs that run at a
different speed than the system, there is a seperate clock domain
created. This domain incorporates the CPU and the associated
caches. As before, Ruby runs under its own clock domain.
The clock period of all domains are pre-computed, such that no virtual
functions or multiplications are needed when calling
clockPeriod. Instead, the clock period is pre-computed when any
changes occur. For this to be possible, each clock domain tracks its
children.
2013-06-27 11:49:49 +02:00
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DebugFlag('ClockDomain')
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2013-08-19 09:52:28 +02:00
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DebugFlag('VoltageDomain')
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power: Add basic DVFS support for gem5
Adds DVFS capabilities to gem5, by allowing users to specify lists for
frequencies and voltages in SrcClockDomains and VoltageDomains respectively.
A separate component, DVFSHandler, provides a small interface to change
operating points of the associated domains.
Clock domains will be linked to voltage domains and thus allow separate clock,
but shared voltage lines.
Currently all the valid performance-level updates are performed with a fixed
transition latency as specified for the domain.
Config file example:
...
vd = VoltageDomain(voltage = ['1V','0.95V','0.90V','0.85V'])
tsys.cluster1.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz']
tsys.cluster2.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz']
tsys.cluster1.clk_domain.domain_id = 0
tsys.cluster2.clk_domain.domain_id = 1
tsys.cluster1.clk_domain.voltage_domain = vd
tsys.cluster2.clk_domain.voltage_domain = vd
tsys.dvfs_handler.domains = [tsys.cluster1.clk_domain,
tsys.cluster2.clk_domain]
tsys.dvfs_handler.enable = True
2014-06-30 19:56:06 +02:00
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DebugFlag('DVFS')
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